1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 */
5#include <common.h>
6#include <fdt_support.h>
7#include <net.h>
8#include <asm/io.h>
9#include <netdev.h>
10#include <fm_eth.h>
11#include <fsl_dtsec.h>
12#include <fsl_mdio.h>
13#include <malloc.h>
14
15#include "../common/fman.h"
16
17int board_eth_init(struct bd_info *bis)
18{
19#ifdef CONFIG_FMAN_ENET
20	int i;
21	struct memac_mdio_info dtsec_mdio_info;
22	struct memac_mdio_info tgec_mdio_info;
23	struct mii_dev *dev;
24	u32 srds_s1;
25	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
26
27	srds_s1 = in_be32(&gur->rcwsr[4]) &
28			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
29	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
30
31	dtsec_mdio_info.regs =
32		(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;
33
34	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
35
36	/* Register the 1G MDIO bus */
37	fm_memac_mdio_init(bis, &dtsec_mdio_info);
38
39	tgec_mdio_info.regs =
40		(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;
41	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
42
43	/* Register the 10G MDIO bus */
44	fm_memac_mdio_init(bis, &tgec_mdio_info);
45
46	/* Set the two on-board RGMII PHY address */
47	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
48	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
49
50	/* Set the two on-board SGMII PHY address */
51	fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);
52	fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);
53
54	/* Set the on-board AQ PHY address */
55	fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
56
57	switch (srds_s1) {
58	case 0x1133:
59		break;
60	default:
61		printf("Invalid SerDes protocol 0x%x for LS1046ARDB\n",
62		       srds_s1);
63		break;
64	}
65
66	dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
67	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++)
68		fm_info_set_mdio(i, dev);
69
70	/* 10GBase-R on lane A, MAC 9 */
71	dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
72	fm_info_set_mdio(FM1_10GEC1, dev);
73
74	cpu_eth_init(bis);
75#endif
76
77	return pci_eth_init(bis);
78}
79
80#ifdef CONFIG_FMAN_ENET
81int fdt_update_ethernet_dt(void *blob)
82{
83	u32 srds_s1;
84	int i, prop;
85	int offset, nodeoff;
86	const char *path;
87	struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
88
89	srds_s1 = in_be32(&gur->rcwsr[4]) &
90			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
91	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
92
93	/* Cycle through all aliases */
94	for (prop = 0; ; prop++) {
95		const char *name;
96
97		/* FDT might have been edited, recompute the offset */
98		offset = fdt_first_property_offset(blob,
99						   fdt_path_offset(blob,
100								   "/aliases")
101						   );
102		/* Select property number 'prop' */
103		for (i = 0; i < prop; i++)
104			offset = fdt_next_property_offset(blob, offset);
105
106		if (offset < 0)
107			break;
108
109		path = fdt_getprop_by_offset(blob, offset, &name, NULL);
110		nodeoff = fdt_path_offset(blob, path);
111
112		switch (srds_s1) {
113		case 0x1133:
114			if (!strcmp(name, "ethernet0"))
115				fdt_status_disabled(blob, nodeoff);
116
117			if (!strcmp(name, "ethernet1"))
118				fdt_status_disabled(blob, nodeoff);
119		break;
120		default:
121			printf("%s: Invalid SerDes prtcl 0x%x for LS1046ARDB\n",
122			       __func__, srds_s1);
123		break;
124		}
125	}
126
127	return 0;
128}
129#endif
130