Searched refs:enable (Results 76 - 100 of 551) sorted by relevance

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/u-boot/arch/x86/include/asm/arch-broadwell/
H A Dpei_data.h50 uint8_t enable; member in struct:usb2_port_setting
56 uint8_t enable; member in struct:usb3_port_setting
/u-boot/drivers/ddr/marvell/a38x/
H A Dxor.h30 int enable; /* Address decode window is enabled/disabled */ member in struct:unit_win_info
87 int enable);
H A Dmv_ddr4_mpr_pda_if.h48 int enable);
57 int mv_ddr4_pda_ctrl(u8 dev_num, u8 if_id, u8 cs_num, int enable);
/u-boot/include/power/
H A Dacpi_pmc.h32 * @pm1_en: PM1 enable
38 * @gpe0_en_req: GPE0 enable register offset
40 * @gpe0_en: GPE0 enable values
130 * @enable: true to enable global reset, false to disable
133 int (*global_reset_set_enable)(struct udevice *dev, bool enable);
178 * @enable: true to enable global reset, false to disable
181 int pmc_global_reset_set_enable(struct udevice *dev, bool enable);
/u-boot/scripts/
H A Dconfig19 --enable|-e option Enable option
29 --enable-after|-E beforeopt option
165 --enable|-e)
208 --enable-after|-E)
/u-boot/arch/arm/mach-tegra/
H A Dcpu.h66 void clock_enable_coresight(int enable);
67 void enable_cpu_clock(int enable);
H A Dxusb-padctl-common.h30 int (*enable)(struct tegra_xusb_phy *phy); member in struct:tegra_xusb_phy_ops
81 unsigned int enable; member in struct:tegra_xusb_padctl
/u-boot/include/
H A Dclk-uclass.h25 * @enable: Enable a clock.
39 int (*enable)(struct clk *clk); member in struct:clk_ops
130 * enable(clk)
194 * enable() - Enable a clock.
208 int enable(struct clk *clk);
/u-boot/arch/arm/mach-imx/
H A Dvideo.c50 if (displays[i].enable)
51 displays[i].enable(displays + i);
/u-boot/arch/arm/mach-socfpga/
H A Dreset_manager_gen5.c90 void socfpga_bridges_reset(int enable) argument
96 if (enable) {
H A Dsystem_manager_gen5.c82 void sysmgr_config_warmrstcfgio(int enable) argument
84 if (enable)
/u-boot/test/dm/
H A Dpwm.c20 bool enable; local
34 &enable, &polarity));
/u-boot/arch/arm/mach-nexell/include/mach/
H A Dnx_gpio.h88 void nx_gpio_set_pull_select(u32 module_index, u32 bit_number, int enable);
93 void nx_gpio_set_fast_slew(u32 module_index, u32 bit_number, int enable);
95 u32 bit_number, int enable);
97 u32 bit_number, int enable);
101 u32 bit_number, int enable);
/u-boot/drivers/pwm/
H A Dpwm-at91.c85 static bool at91_pwm_set(void __iomem *base, uint channel, bool enable) argument
93 if (!(enable ^ cur_status))
96 if (enable)
106 static int at91_pwm_set_enable(struct udevice *dev, uint channel, bool enable) argument
110 at91_pwm_set(priv->base, channel, enable);
/u-boot/drivers/i2c/muxes/
H A Dpca954x.c31 u8 enable; /* Enable mask in ctl register (used for muxes only) */ member in struct:chip_desc
51 .enable = 0x4,
60 .enable = 0x8,
73 .enable = 0x8,
96 byte = channel | chip->enable;
/u-boot/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier-core.c98 unsigned int pin, int enable)
108 if (enable)
118 unsigned int pin, int enable)
123 * Multiple pins share one input enable, per-pin disabling is
126 if (!enable)
136 unsigned int pin, int enable)
141 return uniphier_pinconf_input_enable_perpin(dev, pin, enable);
143 return uniphier_pinconf_input_enable_legacy(dev, pin, enable);
154 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
176 unsigned int enable local
97 uniphier_pinconf_input_enable_perpin(struct udevice *dev, unsigned int pin, int enable) argument
117 uniphier_pinconf_input_enable_legacy(struct udevice *dev, unsigned int pin, int enable) argument
135 uniphier_pinconf_input_enable(struct udevice *dev, unsigned int pin, int enable) argument
[all...]
/u-boot/drivers/power/regulator/
H A Dpbias_regulator.c29 u32 enable; member in struct:pbias_reg_info
140 .enable = BIT(1),
149 .enable = BIT(9),
157 .enable = BIT(26) | BIT(22),
166 .enable = BIT(27) | BIT(26),
292 static int pbias_regulator_set_enable(struct udevice *dev, bool enable) argument
301 debug("Turning %s %s\n", enable ? "on" : "off", p->name);
316 if (enable)
317 reg |= p->enable;
335 if (enable)
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H A Dpfuze100.c384 static int pfuze100_regulator_enable(struct udevice *dev, int op, bool *enable) argument
398 *enable = true;
400 *enable = false;
409 *enable = false;
412 *enable = true;
430 on_off = *enable ? LDO_MODE_ON : LDO_MODE_OFF;
433 on_off = *enable ? SWBST_MODE_AUTO :
436 on_off = *enable ? APS_PFM : OFF_OFF;
529 bool enable = false; local
531 ret = pfuze100_regulator_enable(dev, PMIC_OP_GET, &enable);
538 pfuze100_regulator_set_enable(struct udevice *dev, bool enable) argument
[all...]
H A Ds5m8767.c46 * | voltage ----| | enable -| voltage
157 bool enable; local
164 enable = (ret >> ENABLE_SHIFT) & ENABLE_MASK;
166 return enable;
170 bool enable)
180 enable ? param->reg_enbiton << ENABLE_SHIFT : 0);
192 static int ldo_set_enable(struct udevice *dev, bool enable) argument
196 return reg_set_enable(dev, &ldo_param[ldo], enable);
232 static int buck_set_enable(struct udevice *dev, bool enable) argument
236 return reg_set_enable(dev, &buck_param[buck], enable);
169 reg_set_enable(struct udevice *dev, const struct s5m8767_para *param, bool enable) argument
[all...]
/u-boot/drivers/video/exynos/
H A Dexynos_mipi_dsi_lowlevel.c243 unsigned int lane, unsigned int enable)
251 if (enable)
273 unsigned int enable, unsigned int afc_code)
281 if (enable) {
292 unsigned int enable)
299 reg |= enable << DSIM_PLL_BYPASS_SHIFT;
343 unsigned int enable)
350 reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT);
369 unsigned int enable)
376 reg |= enable << DSIM_BYTE_CLKEN_SHIF
242 exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane, unsigned int enable) argument
272 exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable, unsigned int afc_code) argument
291 exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim, unsigned int enable) argument
342 exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, unsigned int enable) argument
368 exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim, unsigned int enable) argument
381 exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim, unsigned int enable, unsigned int prs_val) argument
396 exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim, unsigned int lane_sel, unsigned int enable) argument
411 exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim, unsigned int enable) argument
513 exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim, unsigned int enable) argument
[all...]
/u-boot/drivers/net/octeontx/
H A Dnicvf_queues.c91 rbdr->enable = true;
126 rbdr->enable = false;
153 if (!rbdr->enable) {
325 int qidx, bool enable)
335 rq->enable = enable;
340 if (!rq->enable) {
383 int qidx, bool enable)
392 cq->enable = enable;
324 nicvf_rcv_queue_config(struct nicvf *nic, struct queue_set *qs, int qidx, bool enable) argument
382 nicvf_cmp_queue_config(struct nicvf *nic, struct queue_set *qs, int qidx, bool enable) argument
424 nicvf_snd_queue_config(struct nicvf *nic, struct queue_set *qs, int qidx, bool enable) argument
474 nicvf_rbdr_config(struct nicvf *nic, struct queue_set *qs, int qidx, bool enable) argument
513 nicvf_qset_config(struct nicvf *nic, bool enable) argument
620 nicvf_config_data_transfer(struct nicvf *nic, bool enable) argument
[all...]
/u-boot/arch/arm/include/asm/arch-imx9/
H A Dclock.h219 int enable_i2c_clk(unsigned char enable, u32 i2c_num);
229 int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
230 int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
231 int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable);
238 int ccm_lpcg_on(u32 lpcg, bool enable);
239 int ccm_lpcg_lpm(u32 lpcg, bool enable);
247 void enable_usboh3_clk(unsigned char enable);
/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dclock.c79 int enable_i2c_clk(unsigned char enable, unsigned i2c_num) argument
92 if (enable) {
179 void enable_ocotp_clk(unsigned char enable) argument
199 void enable_usboh3_clk(unsigned char enable) argument
201 if (enable) {
274 * Hard code to enable RGPIO2P0 clock since it is not
321 void hab_caam_clock_enable(unsigned char enable) argument
323 if (enable)
/u-boot/arch/arm/mach-nexell/
H A Dnx_gpio.c30 void nx_gpio_set_bit(u32 *value, u32 bit, int enable) argument
36 newvalue |= (u32)enable << bit;
254 void nx_gpio_set_pull_select(u32 module_index, u32 bit_number, int enable) argument
261 bit_number, enable);
308 int enable)
314 (int)(!enable));
330 u32 bit_number, int enable)
336 (int)(enable));
338 (int)(enable));
307 nx_gpio_set_fast_slew(u32 module_index, u32 bit_number, int enable) argument
329 nx_gpio_set_drive_strength_disable_default(u32 module_index, u32 bit_number, int enable) argument
/u-boot/drivers/video/nexell/soc/
H A Ds5pxx18_soc_mipi.c65 void nx_mipi_set_interrupt_enable(u32 module_index, u32 int_num, int enable) argument
74 regvalue |= (u32)enable << int_num;
79 regvalue |= (u32)enable << (int_num - 32);
125 void nx_mipi_set_interrupt_enable_all(u32 module_index, int enable) argument
130 if (enable)
498 void nx_mipi_dsi_set_enable(u32 module_index, int enable) argument
504 writereg(dsim_mdresol, (1 << 31), (enable << 31));
530 void nx_mipi_dsi_set_pll(u32 module_index, int enable, u32 pllstabletimer, argument
539 if (!enable) {
540 newvalue = (enable << 2
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