Searched refs:bit (Results 51 - 75 of 216) sorted by relevance

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/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk322x.c152 u8 bit; local
161 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
163 data = (mask << (bit + 16));
164 data |= (mux & mask) << bit;
174 int *reg, u8 *bit)
183 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
184 *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
192 u8 bit, type; local
198 rk3228_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
207 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit
172 rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) argument
216 rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) argument
237 u8 bit; local
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H A Dpinctrl-rk3568.c117 u8 bit; local
128 bit = (pin % 4) * 4;
131 data = (mask << (bit + 16));
133 data |= (mux & mask) << bit;
146 int *reg, u8 *bit)
161 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
162 *bit *= RK3568_PULL_BITS_PER_PIN;
173 int *reg, u8 *bit)
188 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
189 *bit *
144 rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) argument
171 rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) argument
198 rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) argument
225 u8 bit, type; local
269 u8 bit; local
311 u8 bit; local
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/u-boot/board/qualcomm/dragonboard820c/
H A Ddragonboard820c.c36 u32 bit; /* bit in the register */ member in struct:tlmm_cfg
41 /* bit offsets in the sdc tlmm register */
84 hdrv[i].mask << hdrv[i].bit,
85 hdrv[i].val << hdrv[i].bit);
89 pull[i].mask << pull[i].bit,
90 pull[i].val << pull[i].bit);
94 rclk[i].mask << rclk[i].bit,
95 rclk[i].val << rclk[i].bit);
/u-boot/lib/zstd/common/
H A Dcpu.h91 #define X(name, r, bit) \
93 return ((cpuid.r) & (1U << bit)) != 0; \
97 #define C(name, bit) X(name, f1c, bit)
128 #define D(name, bit) X(name, f1d, bit)
161 #define B(name, bit) X(name, f7b, bit)
187 #define C(name, bit) X(name, f7c, bit)
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/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_pbs.c48 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; local
101 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) {
106 bit + pup * BUS_WIDTH_IN_BITS],
112 ("FP I/F %d, bit:%d, pup:%d res0 0x%x\n",
113 if_id, bit, pup,
132 if_id, bit, pup,
219 for (bit = 0; bit < BUS_WIDTH_IN_BIT
942 u32 data_value = 0, bit = 0, if_id = 0, pup = 0; local
992 u32 if_id, pup, bit; local
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H A Dmv_ddr_spd.c18 unsigned int byte, bit, start_cl; local
23 for (bit = 0; bit < 8; bit++) {
24 if (spd_data->all_bytes[byte] & (1 << bit))
25 mv_ddr_spd_supported_cls[(byte - 20) * 8 + bit] = start_cl + (byte - 20) * 8 + bit;
27 mv_ddr_spd_supported_cls[(byte - 20) * 8 + bit] = 0;
31 for (byte = 23, bit = 0; bit <
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/u-boot/drivers/gpio/
H A Dadp5585_gpio.c107 unsigned int bank, bit; local
111 bit = ADP5585_BIT(offset);
113 plat->dir[bank] |= bit;
116 plat->dat_out[bank] |= bit;
118 plat->dat_out[bank] &= ~bit;
130 unsigned int bit = ADP5585_BIT(offset); local
133 if (plat->dir[bank] & bit)
138 return !!(val & bit);
144 unsigned int bank, bit; local
148 bit
162 unsigned int bank, bit, dir; local
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H A Dmscc_sgpio.c111 u32 bit = gpio / MSCC_SGPIOS_PER_BANK; local
113 priv->mode[port] |= BIT(bit);
123 u32 bit = gpio / MSCC_SGPIOS_PER_BANK; local
124 u32 mask = 3 << (3 * bit);
126 debug("set: port %d, bit %d, mask 0x%08x, value %d\n",
127 port, bit, mask, value);
129 value = (value & 3) << (3 * bit);
133 clrbits_le32(&priv->mode[port], BIT(bit));
142 u32 bit = gpio / MSCC_SGPIOS_PER_BANK; local
143 u32 val = priv->mode[port] & BIT(bit);
161 u32 bit = gpio / MSCC_SGPIOS_PER_BANK; local
[all...]
/u-boot/arch/arm/mach-mvebu/
H A Dsystem-controller.c113 uint bit; local
118 bit = MVEBU_GLOBAL_SOFT_RST_BIT;
120 regmap_update_bits(regmap, MVEBU_RSTOUTN_MASK_REG, bit, bit);
121 regmap_update_bits(regmap, MVEBU_SYS_SOFT_RST_REG, bit, bit);
/u-boot/drivers/clk/meson/
H A Dclk_meson.h16 unsigned int bit; member in struct:meson_gate
22 .bit = (_bit), \
/u-boot/drivers/reset/
H A Dreset-sunxi.c48 reset_ctl->id, reset->off, ilog2(reset->bit));
52 reg |= reset->bit;
54 reg &= ~reset->bit;
H A Dreset-imx7.c24 unsigned int offset, bit; member in struct:imx7_src_signal
88 val |= sig[rst->id].bit;
91 val &= ~sig[rst->id].bit;
111 val &= ~sig[rst->id].bit;
114 val |= sig[rst->id].bit;
216 val |= sig[rst->id].bit;
219 val &= ~sig[rst->id].bit;
245 val &= ~sig[rst->id].bit;
248 val |= sig[rst->id].bit;
312 unsigned int bit, valu local
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/u-boot/arch/arm/mach-lpc32xx/
H A Dtimer.c19 static void lpc32xx_timer_clock(u32 bit, int enable) argument
22 setbits_le32(&clk->timclk_ctrl1, bit);
24 clrbits_le32(&clk->timclk_ctrl1, bit);
/u-boot/test/py/tests/
H A Dtest_fpga.py48 'bitstream_loadb': 'compress.bit',
50 'bitstream_loadbp': 'compress_pr.bit',
86 bit = f['%s' % (name)]
90 output = u_boot_console.run_command('tftpboot %x %s' % (addr, bit))
93 return f, dev, addr, bit, bit_size
175 f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_load')
205 f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_load')
215 f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_load')
222 f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'bitstream_loadp')
231 f, dev, addr, bit, bit_siz
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/u-boot/drivers/pinctrl/mtmips/
H A Dpinctrl-mt7628.c447 static int mt7628_set_drv_strength(void __iomem *base, u32 val, u32 bit, argument
459 clrsetbits_32(base + reg_lo, BIT(bit), (i & 1) << bit);
460 clrsetbits_32(base + reg_hi, BIT(bit), ((i >> 1) & 1) << bit);
480 u32 offs, bit; local
484 bit = pin_selector % 32;
488 clrbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit));
489 clrbits_32(priv->pcbase + offs + PAD_PD_G0_REG, BIT(bit));
492 setbits_32(priv->pcbase + offs + PAD_PU_G0_REG, BIT(bit));
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/u-boot/board/keymile/common/
H A Dqrio.c133 void qrio_wdmask(u8 bit, bool wden) argument
141 wdmask |= (1 << bit);
143 wdmask &= ~(1 << bit);
150 void qrio_prst(u8 bit, bool en, bool wden) argument
155 qrio_wdmask(bit, wden);
160 prst &= ~(1 << bit);
162 prst |= (1 << bit);
169 void qrio_prstcfg(u8 bit, u8 mode) argument
179 __set_bit(2 * bit + i, &prstcfg);
181 __clear_bit(2 * bit
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/u-boot/fs/yaffs2/
H A Dyaffs_ecc.c18 * The two unused bit are set to 1.
19 * The ECC can correct single bit errors in a 256-byte page of data. Thus, two
150 /* Single bit (recoverable) error in data */
153 unsigned bit; local
155 bit = byte = 0;
175 bit |= 0x04;
177 bit |= 0x02;
179 bit |= 0x01;
181 data[byte] ^= (1 << bit);
238 unsigned bit; local
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/u-boot/include/jffs2/
H A Dmini_inflate.h21 int bits; /* maximum bit length */
23 int *lengths; /* The bit length of symbols */
25 int *count; /* the number of codes of this bit length */
26 int *first; /* the first code of this bit length */
33 unsigned char bit; /* 0 to 7 */ member in struct:bitstream
/u-boot/drivers/rtc/
H A Dht1380.c64 for (int bit = 0; bit < 8; bit++) {
65 ret = dm_gpio_set_value(&priv->dat_desc, byte >> bit & 1);
122 int ret, i, bit, reg[N_REGS]; local
147 for (bit = 0; bit < 8; bit++) {
155 reg[i] |= dm_gpio_get_value(&priv->dat_desc) << bit;
213 ret = ht1380_send_byte(priv, 0); /* WP bit i
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/u-boot/drivers/bios_emulator/x86emu/
H A Dops2.c296 int bit,disp; local
310 bit = *shiftreg & 0x1F;
313 CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
321 bit = *shiftreg & 0xF;
324 CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
334 bit = *shiftreg & 0x1F;
335 CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF);
343 bit = *shiftreg & 0xF;
344 CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF);
520 int bit,dis local
846 int bit,disp; local
1075 int bit; local
1210 int bit,disp; local
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/u-boot/drivers/misc/
H A Dnpcm_otp.c91 /* Description: Read 8-bit data from an OTP storage array. */
124 /* Returns: Nonzero if bit is programmed, zero otherwise. */
126 /* Description: Check if a bit is programmed in an OTP storage array. */
136 /* Check whether the bit is already programmed */
151 /* Description: Program (set to 1) a bit in an OTP storage array. */
163 /* Make sure the bit is not already programmed */
167 /* Configure the bit address in the fuse array for program operation */
191 /* If the bit is set the sequence ended correctly */
248 /* Program (set to 1) the relevant bit */
283 /* Do not destroy ECCDIS bit */
367 u32 bit; local
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/u-boot/drivers/clk/uniphier/
H A Dclk-uniphier.h29 u8 bit; member in struct:uniphier_clk_gate_data
66 .bit = (_bit), \
/u-boot/tools/
H A Dzynqmpbif.c456 /* Add .bit bitstream */
459 char *bit = read_full_file(bf->filename, NULL); local
467 if (!bit)
471 if (memcmp(bit, initial_header, sizeof(initial_header)))
474 bit += sizeof(initial_header);
477 len = be16_to_cpu(*(uint16_t *)bit);
478 bit += sizeof(uint16_t);
479 debug("Design: %s\n", bit);
480 bit += len;
483 if (*bit !
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/u-boot/arch/arm/cpu/arm1136/
H A Dstart.S80 orr r0, r0, #0x00000002 @ set bit 1 (A) Align
81 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
/u-boot/arch/arm/mach-uniphier/debug-uart/
H A Ddebug-uart.c47 unsigned int bit = pin % 32; local
52 tmp |= 1 << bit;

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