1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4 */ 5 6#include <common.h> 7#include <dm.h> 8#include <dm/pinctrl.h> 9#include <regmap.h> 10#include <syscon.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12 13#include "pinctrl-rockchip.h" 14 15static struct rockchip_mux_route_data rk3568_mux_route_data[] = { 16 MR_PMUGRF(RK_GPIO0, RK_PB7, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(1, 0, 0)), /* PWM0 IO mux selection M0 */ 17 MR_PMUGRF(RK_GPIO0, RK_PC7, RK_FUNC_2, 0x0110, RK_GENMASK_VAL(1, 0, 1)), /* PWM0 IO mux selection M1 */ 18 MR_PMUGRF(RK_GPIO0, RK_PC0, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(3, 2, 0)), /* PWM1 IO mux selection M0 */ 19 MR_PMUGRF(RK_GPIO0, RK_PB5, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(3, 2, 1)), /* PWM1 IO mux selection M1 */ 20 MR_PMUGRF(RK_GPIO0, RK_PC1, RK_FUNC_1, 0x0110, RK_GENMASK_VAL(5, 4, 0)), /* PWM2 IO mux selection M0 */ 21 MR_PMUGRF(RK_GPIO0, RK_PB6, RK_FUNC_4, 0x0110, RK_GENMASK_VAL(5, 4, 1)), /* PWM2 IO mux selection M1 */ 22 MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ 23 MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ 24 MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ 25 MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */ 26 MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */ 27 MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */ 28 MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */ 29 MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */ 30 MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */ 31 MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */ 32 MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */ 33 MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */ 34 MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */ 35 MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */ 36 MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */ 37 MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */ 38 MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */ 39 MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ 40 MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ 41 MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ 42 MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_5, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ 43 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ 44 MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ 45 MR_TOPGRF(RK_GPIO1, RK_PD6, RK_FUNC_4, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ 46 MR_TOPGRF(RK_GPIO3, RK_PB5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ 47 MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ 48 MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ 49 MR_TOPGRF(RK_GPIO4, RK_PC0, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ 50 MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ 51 MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ 52 MR_TOPGRF(RK_GPIO3, RK_PC0, RK_FUNC_2, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ 53 MR_TOPGRF(RK_GPIO4, RK_PC6, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ 54 MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ 55 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ 56 MR_TOPGRF(RK_GPIO3, RK_PC5, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ 57 MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ 58 MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ 59 MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ 60 MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ 61 MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */ 62 MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */ 63 MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */ 64 MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */ 65 MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */ 66 MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ 67 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ 68 MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ 69 MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ 70 MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ 71 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ 72 MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ 73 MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */ 74 MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */ 75 MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */ 76 MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */ 77 MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */ 78 MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */ 79 MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ 80 MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ 81 MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ 82 MR_TOPGRF(RK_GPIO4, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ 83 MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ 84 MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ 85 MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ 86 MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */ 87 MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */ 88 MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */ 89 MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */ 90 MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */ 91 MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */ 92 MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ 93 MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ 94 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ 95 MR_TOPGRF(RK_GPIO1, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ 96 MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(1, 0, 0)), /* PDM IO mux selection M0 */ 97 MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ 98 MR_TOPGRF(RK_GPIO4, RK_PA0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(1, 0, 1)), /* PDM IO mux selection M1 */ 99 MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(1, 0, 2)), /* PDM IO mux selection M2 */ 100 MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ 101 MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ 102 MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ 103 MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */ 104 MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */ 105 MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */ 106 MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */ 107 MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */ 108 MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */ 109}; 110 111static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 112{ 113 struct rockchip_pinctrl_priv *priv = bank->priv; 114 int iomux_num = (pin / 8); 115 struct regmap *regmap; 116 int reg, mask; 117 u8 bit; 118 u32 data, rmask; 119 120 if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 121 regmap = priv->regmap_pmu; 122 else 123 regmap = priv->regmap_base; 124 125 reg = bank->iomux[iomux_num].offset; 126 if ((pin % 8) >= 4) 127 reg += 0x4; 128 bit = (pin % 4) * 4; 129 mask = 0xf; 130 131 data = (mask << (bit + 16)); 132 rmask = data | (data >> 16); 133 data |= (mux & mask) << bit; 134 135 return regmap_update_bits(regmap, reg, rmask, data); 136} 137 138#define RK3568_PULL_PMU_OFFSET 0x20 139#define RK3568_PULL_GRF_OFFSET 0x80 140#define RK3568_PULL_BITS_PER_PIN 2 141#define RK3568_PULL_PINS_PER_REG 8 142#define RK3568_PULL_BANK_STRIDE 0x10 143 144static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 145 int pin_num, struct regmap **regmap, 146 int *reg, u8 *bit) 147{ 148 struct rockchip_pinctrl_priv *info = bank->priv; 149 150 if (bank->bank_num == 0) { 151 *regmap = info->regmap_pmu; 152 *reg = RK3568_PULL_PMU_OFFSET; 153 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; 154 } else { 155 *regmap = info->regmap_base; 156 *reg = RK3568_PULL_GRF_OFFSET; 157 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; 158 } 159 160 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); 161 *bit = (pin_num % RK3568_PULL_PINS_PER_REG); 162 *bit *= RK3568_PULL_BITS_PER_PIN; 163} 164 165#define RK3568_DRV_PMU_OFFSET 0x70 166#define RK3568_DRV_GRF_OFFSET 0x200 167#define RK3568_DRV_BITS_PER_PIN 8 168#define RK3568_DRV_PINS_PER_REG 2 169#define RK3568_DRV_BANK_STRIDE 0x40 170 171static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 172 int pin_num, struct regmap **regmap, 173 int *reg, u8 *bit) 174{ 175 struct rockchip_pinctrl_priv *info = bank->priv; 176 177 /* The first 32 pins of the first bank are located in PMU */ 178 if (bank->bank_num == 0) { 179 *regmap = info->regmap_pmu; 180 *reg = RK3568_DRV_PMU_OFFSET; 181 } else { 182 *regmap = info->regmap_base; 183 *reg = RK3568_DRV_GRF_OFFSET; 184 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; 185 } 186 187 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); 188 *bit = (pin_num % RK3568_DRV_PINS_PER_REG); 189 *bit *= RK3568_DRV_BITS_PER_PIN; 190} 191 192#define RK3568_SCHMITT_BITS_PER_PIN 2 193#define RK3568_SCHMITT_PINS_PER_REG 8 194#define RK3568_SCHMITT_BANK_STRIDE 0x10 195#define RK3568_SCHMITT_GRF_OFFSET 0xc0 196#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 197 198static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 199 int pin_num, struct regmap **regmap, 200 int *reg, u8 *bit) 201{ 202 struct rockchip_pinctrl_priv *info = bank->priv; 203 204 if (bank->bank_num == 0) { 205 *regmap = info->regmap_pmu; 206 *reg = RK3568_SCHMITT_PMUGRF_OFFSET; 207 } else { 208 *regmap = info->regmap_base; 209 *reg = RK3568_SCHMITT_GRF_OFFSET; 210 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; 211 } 212 213 *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); 214 *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; 215 *bit *= RK3568_SCHMITT_BITS_PER_PIN; 216 217 return 0; 218} 219 220static int rk3568_set_pull(struct rockchip_pin_bank *bank, 221 int pin_num, int pull) 222{ 223 struct regmap *regmap; 224 int reg, ret; 225 u8 bit, type; 226 u32 data, rmask; 227 228 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) 229 return -ENOTSUPP; 230 231 rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); 232 type = bank->pull_type[pin_num / 8]; 233 ret = rockchip_translate_pull_value(type, pull); 234 if (ret < 0) { 235 debug("unsupported pull setting %d\n", pull); 236 return ret; 237 } 238 239 /* 240 * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6, 241 * where that pull up value becomes 3. 242 */ 243 if (bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) { 244 if (ret == 1) 245 ret = 3; 246 } 247 248 /* enable the write to the equivalent lower bits */ 249 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); 250 rmask = data | (data >> 16); 251 data |= (ret << bit); 252 253 return regmap_update_bits(regmap, reg, rmask, data); 254} 255 256#define GRF_GPIO1C5_DS 0x0840 257#define GRF_GPIO2A2_DS 0x0844 258#define GRF_GPIO2B0_DS 0x0848 259#define GRF_GPIO3A0_DS 0x084c 260#define GRF_GPIO3A6_DS 0x0850 261#define GRF_GPIO4A0_DS 0x0854 262 263static int rk3568_set_drive(struct rockchip_pin_bank *bank, 264 int pin_num, int strength) 265{ 266 struct regmap *regmap; 267 int reg, ret; 268 u32 data, rmask; 269 u8 bit; 270 int drv = (1 << (strength + 1)) - 1; 271 272 rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 273 274 /* enable the write to the equivalent lower bits */ 275 data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16); 276 rmask = data | (data >> 16); 277 data |= (drv << bit); 278 279 ret = regmap_update_bits(regmap, reg, rmask, data); 280 if (ret) 281 return ret; 282 283 if (bank->bank_num == 1 && pin_num == 21) 284 reg = GRF_GPIO1C5_DS; 285 else if (bank->bank_num == 2 && pin_num == 2) 286 reg = GRF_GPIO2A2_DS; 287 else if (bank->bank_num == 2 && pin_num == 8) 288 reg = GRF_GPIO2B0_DS; 289 else if (bank->bank_num == 3 && pin_num == 0) 290 reg = GRF_GPIO3A0_DS; 291 else if (bank->bank_num == 3 && pin_num == 6) 292 reg = GRF_GPIO3A6_DS; 293 else if (bank->bank_num == 4 && pin_num == 0) 294 reg = GRF_GPIO4A0_DS; 295 else 296 return 0; 297 298 data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16; 299 rmask = data | (data >> 16); 300 data |= drv >> 6; 301 302 return regmap_update_bits(regmap, reg, rmask, data); 303} 304 305static int rk3568_set_schmitt(struct rockchip_pin_bank *bank, 306 int pin_num, int enable) 307{ 308 struct regmap *regmap; 309 int reg; 310 u32 data, rmask; 311 u8 bit; 312 313 rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); 314 315 /* enable the write to the equivalent lower bits */ 316 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); 317 rmask = data | (data >> 16); 318 data |= ((enable ? 0x2 : 0x1) << bit); 319 320 return regmap_update_bits(regmap, reg, rmask, data); 321} 322 323static struct rockchip_pin_bank rk3568_pin_banks[] = { 324 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 325 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 326 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, 327 IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), 328 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 329 IOMUX_WIDTH_4BIT, 330 IOMUX_WIDTH_4BIT, 331 IOMUX_WIDTH_4BIT), 332 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 333 IOMUX_WIDTH_4BIT, 334 IOMUX_WIDTH_4BIT, 335 IOMUX_WIDTH_4BIT), 336 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 337 IOMUX_WIDTH_4BIT, 338 IOMUX_WIDTH_4BIT, 339 IOMUX_WIDTH_4BIT), 340 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 341 IOMUX_WIDTH_4BIT, 342 IOMUX_WIDTH_4BIT, 343 IOMUX_WIDTH_4BIT), 344}; 345 346static const struct rockchip_pin_ctrl rk3568_pin_ctrl = { 347 .pin_banks = rk3568_pin_banks, 348 .nr_banks = ARRAY_SIZE(rk3568_pin_banks), 349 .nr_pins = 160, 350 .grf_mux_offset = 0x0, 351 .pmu_mux_offset = 0x0, 352 .iomux_routes = rk3568_mux_route_data, 353 .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), 354 .set_mux = rk3568_set_mux, 355 .set_pull = rk3568_set_pull, 356 .set_drive = rk3568_set_drive, 357 .set_schmitt = rk3568_set_schmitt, 358}; 359 360static const struct udevice_id rk3568_pinctrl_ids[] = { 361 { 362 .compatible = "rockchip,rk3568-pinctrl", 363 .data = (ulong)&rk3568_pin_ctrl 364 }, 365 { } 366}; 367 368U_BOOT_DRIVER(pinctrl_rk3568) = { 369 .name = "rockchip_rk3568_pinctrl", 370 .id = UCLASS_PINCTRL, 371 .of_match = rk3568_pinctrl_ids, 372 .priv_auto = sizeof(struct rockchip_pinctrl_priv), 373 .ops = &rockchip_pinctrl_ops, 374#if CONFIG_IS_ENABLED(OF_REAL) 375 .bind = dm_scan_fdt_dev, 376#endif 377 .probe = rockchip_pinctrl_probe, 378}; 379