1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2017, Impinj, Inc. 4 */ 5 6#include <log.h> 7#include <malloc.h> 8#include <asm/io.h> 9#include <common.h> 10#include <dm.h> 11#include <dt-bindings/reset/imx7-reset.h> 12#include <dt-bindings/reset/imx8mp-reset.h> 13#include <dt-bindings/reset/imx8mq-reset.h> 14#include <reset-uclass.h> 15#include <linux/bitops.h> 16#include <linux/delay.h> 17 18struct imx_reset_priv { 19 void __iomem *base; 20 struct reset_ops ops; 21}; 22 23struct imx7_src_signal { 24 unsigned int offset, bit; 25}; 26 27enum imx7_src_registers { 28 SRC_A7RCR0 = 0x0004, 29 SRC_M4RCR = 0x000c, 30 SRC_ERCR = 0x0014, 31 SRC_HSICPHY_RCR = 0x001c, 32 SRC_USBOPHY1_RCR = 0x0020, 33 SRC_USBOPHY2_RCR = 0x0024, 34 SRC_MIPIPHY_RCR = 0x0028, 35 SRC_PCIEPHY_RCR = 0x002c, 36 SRC_DDRC_RCR = 0x1000, 37}; 38 39static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = { 40 [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) }, 41 [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) }, 42 [IMX7_RESET_A7_CORE_RESET0] = { SRC_A7RCR0, BIT(4) }, 43 [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) }, 44 [IMX7_RESET_A7_DBG_RESET0] = { SRC_A7RCR0, BIT(8) }, 45 [IMX7_RESET_A7_DBG_RESET1] = { SRC_A7RCR0, BIT(9) }, 46 [IMX7_RESET_A7_ETM_RESET0] = { SRC_A7RCR0, BIT(12) }, 47 [IMX7_RESET_A7_ETM_RESET1] = { SRC_A7RCR0, BIT(13) }, 48 [IMX7_RESET_A7_SOC_DBG_RESET] = { SRC_A7RCR0, BIT(20) }, 49 [IMX7_RESET_A7_L2RESET] = { SRC_A7RCR0, BIT(21) }, 50 [IMX7_RESET_SW_M4C_RST] = { SRC_M4RCR, BIT(1) }, 51 [IMX7_RESET_SW_M4P_RST] = { SRC_M4RCR, BIT(2) }, 52 [IMX7_RESET_EIM_RST] = { SRC_ERCR, BIT(0) }, 53 [IMX7_RESET_HSICPHY_PORT_RST] = { SRC_HSICPHY_RCR, BIT(1) }, 54 [IMX7_RESET_USBPHY1_POR] = { SRC_USBOPHY1_RCR, BIT(0) }, 55 [IMX7_RESET_USBPHY1_PORT_RST] = { SRC_USBOPHY1_RCR, BIT(1) }, 56 [IMX7_RESET_USBPHY2_POR] = { SRC_USBOPHY2_RCR, BIT(0) }, 57 [IMX7_RESET_USBPHY2_PORT_RST] = { SRC_USBOPHY2_RCR, BIT(1) }, 58 [IMX7_RESET_MIPI_PHY_MRST] = { SRC_MIPIPHY_RCR, BIT(1) }, 59 [IMX7_RESET_MIPI_PHY_SRST] = { SRC_MIPIPHY_RCR, BIT(2) }, 60 [IMX7_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) }, 61 [IMX7_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, 62 [IMX7_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, 63 [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, 64 [IMX7_RESET_DDRC_PRST] = { SRC_DDRC_RCR, BIT(0) }, 65 [IMX7_RESET_DDRC_CORE_RST] = { SRC_DDRC_RCR, BIT(1) }, 66}; 67 68static int imx7_reset_deassert(struct reset_ctl *rst) 69{ 70 struct imx_reset_priv *priv = dev_get_priv(rst->dev); 71 const struct imx7_src_signal *sig = imx7_src_signals; 72 u32 val; 73 74 if (rst->id >= IMX7_RESET_NUM) 75 return -EINVAL; 76 77 if (rst->id == IMX7_RESET_PCIEPHY) { 78 /* 79 * wait for more than 10us to release phy g_rst and 80 * btnrst 81 */ 82 udelay(10); 83 } 84 85 val = readl(priv->base + sig[rst->id].offset); 86 switch (rst->id) { 87 case IMX7_RESET_PCIE_CTRL_APPS_EN: 88 val |= sig[rst->id].bit; 89 break; 90 default: 91 val &= ~sig[rst->id].bit; 92 break; 93 } 94 writel(val, priv->base + sig[rst->id].offset); 95 96 return 0; 97} 98 99static int imx7_reset_assert(struct reset_ctl *rst) 100{ 101 struct imx_reset_priv *priv = dev_get_priv(rst->dev); 102 const struct imx7_src_signal *sig = imx7_src_signals; 103 u32 val; 104 105 if (rst->id >= IMX7_RESET_NUM) 106 return -EINVAL; 107 108 val = readl(priv->base + sig[rst->id].offset); 109 switch (rst->id) { 110 case IMX7_RESET_PCIE_CTRL_APPS_EN: 111 val &= ~sig[rst->id].bit; 112 break; 113 default: 114 val |= sig[rst->id].bit; 115 break; 116 } 117 writel(val, priv->base + sig[rst->id].offset); 118 119 return 0; 120} 121 122enum imx8mq_src_registers { 123 SRC_A53RCR0 = 0x0004, 124 SRC_HDMI_RCR = 0x0030, 125 SRC_DISP_RCR = 0x0034, 126 SRC_GPU_RCR = 0x0040, 127 SRC_VPU_RCR = 0x0044, 128 SRC_PCIE2_RCR = 0x0048, 129 SRC_MIPIPHY1_RCR = 0x004c, 130 SRC_MIPIPHY2_RCR = 0x0050, 131 SRC_DDRC2_RCR = 0x1004, 132}; 133 134static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = { 135 [IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) }, 136 [IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) }, 137 [IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) }, 138 [IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) }, 139 [IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) }, 140 [IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) }, 141 [IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) }, 142 [IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) }, 143 [IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) }, 144 [IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) }, 145 [IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) }, 146 [IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) }, 147 [IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) }, 148 [IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) }, 149 [IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) }, 150 [IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) }, 151 [IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) }, 152 [IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) }, 153 [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) }, 154 [IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) }, 155 [IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, 156 [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) }, 157 [IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) }, 158 [IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) }, 159 [IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) }, 160 [IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) }, 161 [IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, 162 BIT(2) | BIT(1) }, 163 [IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, 164 [IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, 165 [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, 166 [IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) }, 167 [IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) }, 168 [IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) }, 169 [IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) }, 170 [IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR, 171 BIT(2) | BIT(1) }, 172 [IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) }, 173 [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) }, 174 [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) }, 175 [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) }, 176 [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) }, 177 [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) }, 178 [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) }, 179 [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) }, 180 [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) }, 181 [IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) }, 182 [IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) }, 183 [IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) }, 184 [IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) }, 185 [IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) }, 186 [IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) }, 187}; 188 189static int imx8mq_reset_deassert(struct reset_ctl *rst) 190{ 191 struct imx_reset_priv *priv = dev_get_priv(rst->dev); 192 const struct imx7_src_signal *sig = imx8mq_src_signals; 193 u32 val; 194 195 if (rst->id >= IMX8MQ_RESET_NUM) 196 return -EINVAL; 197 198 if (rst->id == IMX8MQ_RESET_PCIEPHY || 199 rst->id == IMX8MQ_RESET_PCIEPHY2) { 200 /* 201 * wait for more than 10us to release phy g_rst and 202 * btnrst 203 */ 204 udelay(10); 205 } 206 207 val = readl(priv->base + sig[rst->id].offset); 208 switch (rst->id) { 209 case IMX8MQ_RESET_PCIE_CTRL_APPS_EN: 210 case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */ 211 case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */ 212 case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */ 213 case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */ 214 case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */ 215 case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */ 216 val |= sig[rst->id].bit; 217 break; 218 default: 219 val &= ~sig[rst->id].bit; 220 break; 221 } 222 writel(val, priv->base + sig[rst->id].offset); 223 224 return 0; 225} 226 227static int imx8mq_reset_assert(struct reset_ctl *rst) 228{ 229 struct imx_reset_priv *priv = dev_get_priv(rst->dev); 230 const struct imx7_src_signal *sig = imx8mq_src_signals; 231 u32 val; 232 233 if (rst->id >= IMX8MQ_RESET_NUM) 234 return -EINVAL; 235 236 val = readl(priv->base + sig[rst->id].offset); 237 switch (rst->id) { 238 case IMX8MQ_RESET_PCIE_CTRL_APPS_EN: 239 case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */ 240 case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N: /* fallthrough */ 241 case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N: /* fallthrough */ 242 case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N: /* fallthrough */ 243 case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */ 244 case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */ 245 val &= ~sig[rst->id].bit; 246 break; 247 default: 248 val |= sig[rst->id].bit; 249 break; 250 } 251 writel(val, priv->base + sig[rst->id].offset); 252 253 return 0; 254} 255 256enum imx8mp_src_registers { 257 SRC_SUPERMIX_RCR = 0x0018, 258 SRC_AUDIOMIX_RCR = 0x001c, 259 SRC_MLMIX_RCR = 0x0028, 260 SRC_GPU2D_RCR = 0x0038, 261 SRC_GPU3D_RCR = 0x003c, 262 SRC_VPU_G1_RCR = 0x0048, 263 SRC_VPU_G2_RCR = 0x004c, 264 SRC_VPUVC8KE_RCR = 0x0050, 265 SRC_NOC_RCR = 0x0054, 266}; 267 268static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = { 269 [IMX8MP_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) }, 270 [IMX8MP_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) }, 271 [IMX8MP_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) }, 272 [IMX8MP_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) }, 273 [IMX8MP_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) }, 274 [IMX8MP_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) }, 275 [IMX8MP_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) }, 276 [IMX8MP_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) }, 277 [IMX8MP_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) }, 278 [IMX8MP_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) }, 279 [IMX8MP_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) }, 280 [IMX8MP_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) }, 281 [IMX8MP_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) }, 282 [IMX8MP_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) }, 283 [IMX8MP_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) }, 284 [IMX8MP_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) }, 285 [IMX8MP_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) }, 286 [IMX8MP_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) }, 287 [IMX8MP_RESET_SW_NON_SCLR_M7C_RST] = { SRC_M4RCR, BIT(0) }, 288 [IMX8MP_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) }, 289 [IMX8MP_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) }, 290 [IMX8MP_RESET_SUPERMIX_RESET] = { SRC_SUPERMIX_RCR, BIT(0) }, 291 [IMX8MP_RESET_AUDIOMIX_RESET] = { SRC_AUDIOMIX_RCR, BIT(0) }, 292 [IMX8MP_RESET_MLMIX_RESET] = { SRC_MLMIX_RCR, BIT(0) }, 293 [IMX8MP_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR, BIT(2) }, 294 [IMX8MP_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) }, 295 [IMX8MP_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) }, 296 [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) }, 297 [IMX8MP_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) }, 298 [IMX8MP_RESET_MEDIA_RESET] = { SRC_DISP_RCR, BIT(0) }, 299 [IMX8MP_RESET_GPU2D_RESET] = { SRC_GPU2D_RCR, BIT(0) }, 300 [IMX8MP_RESET_GPU3D_RESET] = { SRC_GPU3D_RCR, BIT(0) }, 301 [IMX8MP_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) }, 302 [IMX8MP_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) }, 303 [IMX8MP_RESET_VPU_G1_RESET] = { SRC_VPU_G1_RCR, BIT(0) }, 304 [IMX8MP_RESET_VPU_G2_RESET] = { SRC_VPU_G2_RCR, BIT(0) }, 305 [IMX8MP_RESET_VPUVC8KE_RESET] = { SRC_VPUVC8KE_RCR, BIT(0) }, 306 [IMX8MP_RESET_NOC_RESET] = { SRC_NOC_RCR, BIT(0) }, 307}; 308 309static int imx8mp_reset_set(struct reset_ctl *rst, bool assert) 310{ 311 struct imx_reset_priv *priv = dev_get_priv(rst->dev); 312 unsigned int bit, value; 313 314 if (rst->id >= IMX8MP_RESET_NUM) 315 return -EINVAL; 316 317 bit = imx8mp_src_signals[rst->id].bit; 318 value = assert ? bit : 0; 319 320 switch (rst->id) { 321 case IMX8MP_RESET_PCIEPHY: 322 /* 323 * wait for more than 10us to release phy g_rst and 324 * btnrst 325 */ 326 if (!assert) 327 udelay(10); 328 break; 329 330 case IMX8MP_RESET_PCIE_CTRL_APPS_EN: 331 case IMX8MP_RESET_PCIEPHY_PERST: 332 value = assert ? 0 : bit; 333 break; 334 } 335 336 clrsetbits_le32(priv->base + imx8mp_src_signals[rst->id].offset, bit, 337 value); 338 339 return 0; 340} 341 342static int imx8mp_reset_assert(struct reset_ctl *rst) 343{ 344 return imx8mp_reset_set(rst, true); 345} 346 347static int imx8mp_reset_deassert(struct reset_ctl *rst) 348{ 349 return imx8mp_reset_set(rst, false); 350} 351 352static int imx_reset_assert(struct reset_ctl *rst) 353{ 354 struct imx_reset_priv *priv = dev_get_priv(rst->dev); 355 return priv->ops.rst_assert(rst); 356} 357 358static int imx_reset_deassert(struct reset_ctl *rst) 359{ 360 struct imx_reset_priv *priv = dev_get_priv(rst->dev); 361 return priv->ops.rst_deassert(rst); 362} 363 364static const struct reset_ops imx7_reset_reset_ops = { 365 .rst_assert = imx_reset_assert, 366 .rst_deassert = imx_reset_deassert, 367}; 368 369static const struct udevice_id imx7_reset_ids[] = { 370 { .compatible = "fsl,imx7d-src" }, 371 { .compatible = "fsl,imx8mq-src" }, 372 { .compatible = "fsl,imx8mp-src" }, 373 { } 374}; 375 376static int imx7_reset_probe(struct udevice *dev) 377{ 378 struct imx_reset_priv *priv = dev_get_priv(dev); 379 380 priv->base = dev_remap_addr(dev); 381 if (!priv->base) 382 return -ENOMEM; 383 384 if (device_is_compatible(dev, "fsl,imx8mq-src")) { 385 priv->ops.rst_assert = imx8mq_reset_assert; 386 priv->ops.rst_deassert = imx8mq_reset_deassert; 387 } else if (device_is_compatible(dev, "fsl,imx7d-src")) { 388 priv->ops.rst_assert = imx7_reset_assert; 389 priv->ops.rst_deassert = imx7_reset_deassert; 390 } else if (device_is_compatible(dev, "fsl,imx8mp-src")) { 391 priv->ops.rst_assert = imx8mp_reset_assert; 392 priv->ops.rst_deassert = imx8mp_reset_deassert; 393 } 394 395 return 0; 396} 397 398U_BOOT_DRIVER(imx7_reset) = { 399 .name = "imx7_reset", 400 .id = UCLASS_RESET, 401 .of_match = imx7_reset_ids, 402 .ops = &imx7_reset_reset_ops, 403 .probe = imx7_reset_probe, 404 .priv_auto = sizeof(struct imx_reset_priv), 405}; 406