Searched refs:bit (Results 176 - 200 of 216) sorted by relevance

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/u-boot/drivers/clk/uniphier/
H A Dclk-uniphier-core.c36 val |= BIT(gate->bit);
/u-boot/drivers/soc/ti/
H A Dk3-navss-ringacc.c29 #define set_bit(bit, bitmap) __set_bit(bit, bitmap)
30 #define clear_bit(bit, bitmap) __clear_bit(bit, bitmap)
/u-boot/drivers/pinctrl/nuvoton/
H A Dpinctrl-npcm8xx.c62 * name, register, enable bit, pin list
308 .bit = _bit, \
319 * @bit: offset of enable bit in the register
327 u32 bit; member in struct:group_info
645 BIT(group->bit), BIT(group->bit));
648 BIT(group->bit), 0);
/u-boot/drivers/clk/stm32/
H A Dclk-stm32mp1.c400 u8 bit; member in struct:stm32mp1_clk_gate
443 .bit = (b), \
453 .bit = (b), \
463 .bit = (b), \
473 .bit = (b), \
1180 writel(BIT(gate[i].bit), priv->base + gate[i].offset);
1182 setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
1199 writel(BIT(gate[i].bit),
1203 clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
2031 /* no ready bit whe
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/u-boot/arch/arm/
H A Dconfig.mk132 # The movt / movw can hardcode 16 bit parts of the addresses in the
/u-boot/include/
H A Dusb.h122 /* one bit for each endpoint ([0] = IN, [1] = OUT) */
124 /* endpoint halts; one bit per endpoint # & direction;
148 unsigned long int_pending; /* 1 bit per ep, used by int_queue */
335 * - current Data0/1 state (1 bit)
336 * - direction (1 bit)
349 * - direction: bit 7 (0 = Host-to-Device [Out],
353 * - Data0/1: bit 19
358 * up to us. This one happens to share a lot of bit positions with the UHCI
397 #define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = \
399 ~(1 << ep)) | ((bit) << e
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/u-boot/drivers/mmc/
H A Ddw_mmc.c104 static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len) argument
109 while (--timeout && (*len & bit)) {
H A Dmtk-sd.c1015 static u32 test_delay_bit(u32 delay, u32 bit) argument
1017 bit %= PAD_DELAY_MAX;
1018 return delay & (1 << bit);
/u-boot/drivers/i2c/
H A Di2c-uclass.c580 static void i2c_gpio_set_pin(struct gpio_desc *pin, int bit) argument
582 if (bit)
/u-boot/arch/x86/lib/
H A Dzimage.c500 uint bit; member in struct:flag_info
512 { XLF_KERNEL_64, "64-bit-entry" },
525 uint mask = flags[i].bit;
/u-boot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S87 mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set)
/u-boot/arch/x86/include/asm/
H A Dcoreboot_tables.h213 * 1 << 31 - Valid bit, PCI UART in use
310 * output will wrap back around to the start of the buffer. The high bit of the
456 u32 bit; member in struct:cb_cmos_entries
/u-boot/drivers/mtd/nand/raw/
H A Domap_gpmc.c40 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
68 /* We are wasting a bit of memory but al least we are safe */
126 * registers values and corrects one bit error if it has occurred
143 uint8_t bit; local
153 /* Single bit errors can be corrected! */
157 bit = (parity_bits & 0x7);
159 /* Flip the bit to correct */
160 dat[byte] ^= (0x1 << bit);
167 * hm distance != parity pairs OR one, could mean 2 bit
182 /* detected 2 bit erro
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/u-boot/drivers/pinctrl/
H A Dpinctrl-k210.c616 u32 bit = BIT(group_selector); local
618 regmap_update_bits(priv->sysctl, priv->power_offset, bit,
619 argument ? bit : 0);
/u-boot/arch/mips/mach-octeon/include/mach/
H A Dcvmx-pow.h790 * 64-bit store was used for all these stores.
795 * NOTE: The following is the behavior of the pending switch bit at the PP
797 * - did<2:0> == 0 => pending switch bit is set
798 * - did<2:0> == 1 => no affect on the pending switch bit
799 * - did<2:0> == 3 => pending switch bit is cleared
800 * - did<2:0> == 7 => no affect on the pending switch bit
802 * - No other loads/stores have an affect on the pending switch bit
803 * - The switch bus from POW can clear the pending switch bit
1027 * Waits for a tag switch to complete by polling the completion bit.
1150 * which is either a valid WQE, or a response with the invalid bit se
1694 unsigned int bit; /* bit index */ local
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/u-boot/drivers/net/octeontx/
H A Dbgx.c115 static int gser_poll_reg(u64 reg, int bit, u64 mask, u64 expected_val, argument
121 debug(" expected_val = %#llx, bit = %d\n", expected_val, bit);
123 reg_val = readq(reg) >> bit;
784 /* Clear rcvflt bit (latching high) and read it back */
/u-boot/drivers/pinctrl/renesas/
H A Dpfc-r8a779f0.c1921 int bit = pin & 0x1f; local
1925 return bit;
1929 return bit;
1933 return bit;
H A Dpfc-r8a77970.c2367 int bit = pin & 0x1f; local
2372 return bit;
2376 return bit + 22;
2380 return bit - 10;
2384 return bit + 7;
H A Dpfc-r8a779a0.c3972 int bit = pin & 0x1f; local
3976 return bit;
3980 return bit;
3984 return bit;
3988 return bit;
3992 return bit;
3996 return bit;
4000 return bit;
4004 return bit;
4008 return bit;
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/u-boot/drivers/ram/octeon/
H A Docteon3_lmc.c317 // loops are ordered so that only a single 64-bit slot is written to
444 // error bit
465 // move bit into next
755 * bit-dskew training. So for that reason, these steps below have
991 // set bit number and start read sequence
1057 int bit, byte_lane, byte_limit; local
1082 for (bit = 0; bit < 8; ++bit) {
1084 u64 bits = (dskdat->bytes[byte_lane].bits[bit] >>
1192 int rankx, lane, bit; local
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/u-boot/drivers/video/
H A Ddw_hdmi.c298 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, uint bit) argument
301 bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
/u-boot/drivers/clk/meson/
H A Dgxbb.c226 BIT(gate->bit), on ? BIT(gate->bit) : 0);
H A Dg12a.c175 BIT(gate->bit), on ? BIT(gate->bit) : 0);
/u-boot/cmd/
H A Defidebug.c534 const u64 bit; member in struct:efi_mem_attrs
565 if (attributes & efi_mem_attrs[i].bit) {
/u-boot/drivers/mtd/spi/
H A Dspi-nor-core.c128 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
131 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
132 * two data bytes where bit 1 of the second byte is one.
135 * clearing status register 2, including the QE bit. The 100b code is
138 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
139 * one data byte where bit 6 is one.
141 * - 011b: QE is bit 7 of status register 2. It is set via Write status
142 * register 2 instruction 3Eh with one data byte where bit 7 is one.
145 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
146 * two data bytes where bit
1514 sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) argument
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