Searched refs:cpu (Results 26 - 50 of 50) sorted by relevance

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/seL4-refos-master/seL4_tools/elfloader-tool/src/plat/exynos5/
H A Dplatform_init.c64 void boot_cpu(int cpu, uintptr_t entry) argument
70 cpu_cfg[cpu].core.config = CORE_LOCAL_PWR_EN;
/seL4-refos-master/tools/elfloader/src/plat/exynos5/
H A Dplatform_init.c64 void boot_cpu(int cpu, uintptr_t entry) argument
70 cpu_cfg[cpu].core.config = CORE_LOCAL_PWR_EN;
/seL4-refos-master/projects/seL4_libs/libsel4bench/arch_include/arm/armv/armv7-a/sel4bench/armv/
H A Devents.h70 #include <sel4bench/cpu/events.h>
/seL4-refos-master/libs/libplatsupport/plat_include/exynos5/platsupport/plat/
H A Dclock.h82 int exynos5_clock_sys_init(void* cpu, void* core, void* acp, void* isp, void* top,
/seL4-refos-master/projects/util_libs/libplatsupport/plat_include/exynos5/platsupport/plat/
H A Dclock.h82 int exynos5_clock_sys_init(void* cpu, void* core, void* acp, void* isp, void* top,
/seL4-refos-master/kernel/include/machine/
H A Dfpu.h24 /* Switch the current owner of the FPU state on the core specified by 'cpu'. */
25 void switchFpuOwner(user_fpu_state_t *new_owner, word_t cpu);
/seL4-refos-master/projects/util_libs/libplatsupport/src/arch/arm/
H A Dgeneric_ltimer.c45 irq->cpu.number = GENERIC_TIMER_PCNT_IRQ;
46 irq->cpu.trigger = 0;
47 irq->cpu.cpu_idx = 0;
102 irq->cpu.number != GENERIC_TIMER_PCNT_IRQ &&
103 irq->cpu.trigger != 0 &&
104 irq->cpu.cpu_idx != 0) {
/seL4-refos-master/libs/libplatsupport/src/arch/arm/
H A Dgeneric_ltimer.c45 irq->cpu.number = GENERIC_TIMER_PCNT_IRQ;
46 irq->cpu.trigger = 0;
47 irq->cpu.cpu_idx = 0;
102 irq->cpu.number != GENERIC_TIMER_PCNT_IRQ &&
103 irq->cpu.trigger != 0 &&
104 irq->cpu.cpu_idx != 0) {
/seL4-refos-master/libs/libmuslc/src/fenv/i386/
H A Dfenv.s9 # consider sse fenv as well if the cpu has XMM capability
73 # consider sse fenv as well if the cpu has XMM capability
102 # consider sse fenv as well if the cpu has XMM capability
134 # consider sse fenv as well if the cpu has XMM capability
154 # consider sse fenv as well if the cpu has XMM capability
/seL4-refos-master/libs/libmuslc/src/fenv/i386_sel4/
H A Dfenv.s9 # consider sse fenv as well if the cpu has XMM capability
73 # consider sse fenv as well if the cpu has XMM capability
102 # consider sse fenv as well if the cpu has XMM capability
134 # consider sse fenv as well if the cpu has XMM capability
154 # consider sse fenv as well if the cpu has XMM capability
/seL4-refos-master/kernel/tools/hardware/outputs/
H A Delfloader.py18 from hardware.utils import cpu, memory, rule namespace
84 {% for cpu in cpus %}
86 /* {{ cpu['path'] }} */
87 .compat = "{{ cpu['compat'] }}",
88 .enable_method = {{ '"{}"'.format(cpu['enable_method']) if cpu['enable_method'] else 'NULL' }},
89 .cpu_id = {{ "0x{:x}".format(cpu['cpuid']) }},
90 .extra_data = {{ cpu['extra'] }}
103 cpus = cpu.get_cpus(tree)
128 device.Utils.make_number(2, list(cpu_node.get_prop('cpu
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/seL4-refos-master/projects/seL4_libs/libsel4bench/arch_include/arm/armv/armv8-a/sel4bench/armv/
H A Devents.h80 #include <sel4bench/cpu/events.h>
/seL4-refos-master/projects/seL4_libs/libsel4bench/arch_include/arm/cpu/arm1136jf-s/sel4bench/cpu/
H A Dprivate.h15 #include <sel4bench/cpu/events.h>
H A Dsel4bench.h15 #include <sel4bench/cpu/private.h>
/seL4-refos-master/projects/util_libs/libplatsupport/include/platsupport/
H A Dirq.h70 } cpu; member in union:__anon11::__anon12
/seL4-refos-master/libs/libplatsupport/include/platsupport/
H A Dirq.h70 } cpu; member in union:__anon1::__anon2
/seL4-refos-master/kernel/src/arch/arm/machine/
H A Dgic_v2.c31 #error GIC_V2_CONTROLLER_PPTR must be defined for virtual memory access to the gic cpu interface
85 * reset int target to current cpu
181 * 0b01 - send the ipi to all CPU interfaces except the cpu interface.
225 #error GIC_V2_VCPUCTRL_PPTR must be defined for virtual memory access to the gic virtual cpu interface control
/seL4-refos-master/kernel/include/model/
H A Dstatedata.h27 #define MODE_NODE_STATE_ON_CORE(_state, _core) ksSMP[(_core)].cpu.mode._state
28 #define ARCH_NODE_STATE_ON_CORE(_state, _core) ksSMP[(_core)].cpu._state
/seL4-refos-master/kernel/include/arch/x86/arch/64/mode/
H A Dmachine.h260 static inline void x86_save_fsgs_base(tcb_t *thread, cpu_id_t cpu) argument
277 word_t cur_fs_base = x86_read_fs_base(cpu);
279 word_t cur_gs_base = x86_read_gs_base(cpu);
/seL4-refos-master/kernel/include/arch/arm/arch/object/
H A Dvcpu.h117 void vcpu_restore(vcpu_t *cpu);
118 void vcpu_switch(vcpu_t *cpu);
/seL4-refos-master/libs/libplatsupport/src/plat/exynos5/
H A Dclock.c305 exynos5_clock_sys_init(void* cpu, void* core, void* acp, void* isp, void* top, argument
309 if (cpu) {
310 _clk_regs[CLKREGS_CPU] = cpu;
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/exynos5/
H A Dclock.c305 exynos5_clock_sys_init(void* cpu, void* core, void* acp, void* isp, void* top, argument
309 if (cpu) {
310 _clk_regs[CLKREGS_CPU] = cpu;
/seL4-refos-master/libs/libplatsupport/src/plat/zynq7000/
H A Dclock.c642 static struct clock cpu_6or4x_clk = { CLK_OPS(CPU_6OR4X, cpu, NULL) };
643 static struct clock cpu_3or2x_clk = { CLK_OPS(CPU_3OR2X, cpu, NULL) };
644 static struct clock cpu_2x_clk = { CLK_OPS(CPU_2X, cpu, NULL) };
645 static struct clock cpu_1x_clk = { CLK_OPS(CPU_1X, cpu, NULL) };
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/zynq7000/
H A Dclock.c642 static struct clock cpu_6or4x_clk = { CLK_OPS(CPU_6OR4X, cpu, NULL) };
643 static struct clock cpu_3or2x_clk = { CLK_OPS(CPU_3OR2X, cpu, NULL) };
644 static struct clock cpu_2x_clk = { CLK_OPS(CPU_2X, cpu, NULL) };
645 static struct clock cpu_1x_clk = { CLK_OPS(CPU_1X, cpu, NULL) };
/seL4-refos-master/kernel/src/object/
H A Dtcb.c52 static inline void addToBitmap(word_t cpu, word_t dom, word_t prio) argument
60 NODE_STATE_ON_CORE(ksReadyQueuesL1Bitmap[dom], cpu) |= BIT(l1index);
65 NODE_STATE_ON_CORE(ksReadyQueuesL2Bitmap[dom][l1index_inverted], cpu) |= BIT(prio & MASK(wordRadix));
68 static inline void removeFromBitmap(word_t cpu, word_t dom, word_t prio) argument
75 NODE_STATE_ON_CORE(ksReadyQueuesL2Bitmap[dom][l1index_inverted], cpu) &= ~BIT(prio & MASK(wordRadix));
76 if (unlikely(!NODE_STATE_ON_CORE(ksReadyQueuesL2Bitmap[dom][l1index_inverted], cpu))) {
77 NODE_STATE_ON_CORE(ksReadyQueuesL1Bitmap[dom], cpu) &= ~BIT(l1index);
488 /* reschedule current cpu if tcb moves itself */

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