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96456c6a |
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06-May-2020 |
Curtis Millar <curtis.millar@data61.csiro.au> |
trivial: fix header files Signed-off-by: Curtis Millar <curtis.millar@data61.csiro.au>
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512a0200 |
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19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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3207abee |
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20-Mar-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
RFC-3: Update context for x86 to use FS and GS. TLS_BASE virtual register is replaced with FS_BASE and GS_BASE virtual registers. The FS_BASE and GS_BASE virtual registers are moved to the end of the context so they need not be considered in the kernel exit and entry implementation. Removed tracking of ES, DS, FS, and GS segment selectors on kernel entry and exit. ES and DS are clobbered on kernel entry with the RPL 3 selector for a DPL 3 linear data segment. FS is clobbered on exit with the RPL 3 selector for the DPL 3 segment with FS_BASE as the base. This is done on exit to reload the value from the GDT. GS is clobbered on exit with the RPL 3 selector for the DPL 3 segment with GS_BASE as the base. This is done on exit to reload the value from the GDT. Kernel entry and exit code is refactored, simplified, and improved in light of the above changes. x64: update verified config to use fsgsbase instr The verification platform for x64 relies on the fsgsbase instruction.
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761006e0 |
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18-Mar-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
style: consistently align pointer with name Run astyle with align-pointer=name
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3d10ef0c |
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18-Mar-2019 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
style: correct parenthesis padding Use astyle's unpad-paren to unpad all parentheses that are not included by pad-header, pad-oper, and pad-comma.
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374da850 |
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16-Jan-2018 |
Bamboo <bamboo@keg.ertos.in.nicta.com.au> |
[STYLE_FIX]
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29695d26 |
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07-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x64: SKIM window to mitigate Meltdown (CVE-2017-5754) on x86-64 Introduces a kernel option that, when enabled, reduces the kernel window in a user address space to just be Static Kernel Image and Microstate (SKIM), instead of the full kernel address space. This isolates the important kernel data from the user preventing a Meltdown style attack being able to violate secrecy. The kernel text and read only data, i.e. anything that is static from boot, is not secret and can be allowed in the SKIM window and potentially read by the user. Additionally to switch to and from the actual kernel address space a small amount of state needs to also be in the SKIM window. This is only an implementation for x86-64, although the same design is applicable to ia32
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ed37e31d |
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07-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x64: Invalid ASID with single asm block This performs a double address space switch to invalidate an ASID using a single hand written asm block instead of setCurrentCR3. The purpose of this is to ensure that the only requirements on the temporary address space that we switch to is that the kernel code is still mapped in at the same location. As we ensure our old cr3 value is in register we can ensure, unlike with calling getCurrentCR3 that no stack or other temporary memory is required.
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96842a2c |
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05-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x64: If PCIDs are not enabled forbid them in any CR3 values When PCIDs are not enabled the low 12 bits of CR3 are not all ignored as bits 3 and 4 control memory typing of the translation. To prevent setting these to 'random' values we should leave the low bits of CR3 0 when not using PCIDs. A new makeCR3 wrapper is defined that is used instead of cr3_new that, based on CONFIG_SUPPORT_PCID, either fills in the PCID or 0 as required.
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4edbbbd4 |
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03-Jan-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x64: Separate notion of current vspace root with current user vspace root This introduces functions for specifically manipulating the user vspace root, either as an abstract root or the specific CR3 value, in a way that is separated from the current vspace root. Currently they are one and the same, but this separation allows for having the kernel translation (and hence the active vspace root) be different the currently active user.
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40c61e5c |
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18-Jun-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
Fix licenses (the rest)
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0a0c2722 |
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03-May-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Remove trailing semicolons in asm statements These semicolons are not actually necessary, and cause problems for the C parser
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eccaae51 |
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20-Feb-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
s/D61/DATA61/ in license headers for consistency
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dcaff678 |
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05-Feb-2017 |
Bamboo <bamboo@keg.ertos.in.nicta.com.au> |
[STYLE_FIX]
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331e9796 |
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02-Feb-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Implement safe rdmsr function Implements a safe version of `x86_rdmsr` that can return success or failure depending on if the rdmsr caused a GP fault
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564b9839 |
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05-Dec-2016 |
Donny Yang <work@kota.moe> |
x86: Avoid writing the fs/gs base if we don't have to
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d6d8fb54 |
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14-Nov-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x64: Multicore TLB coherency
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a0cb9e67 |
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09-Nov-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x64: Support multiple kernel stacks Adds support for per-core kernel stacks through the use of thread local storage and swapgs. In addition to the main kernel stack the IRQ stack also needs to be made per core
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6f908324 |
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06-Nov-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x64: Access core local state correctly
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056dbf81 |
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02-Nov-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-634: support for TLB and cache management
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b90238d0 |
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19-Oct-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Replace #pragma once with include guards
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f062dcdc |
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11-Oct-2016 |
Bamboo <bamboo@keg.ertos.in.nicta.com.au> |
[STYLE_FIX]
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9c1d204e |
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09-Oct-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x64: Correctly invalidate PCIDs
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7f9970e5 |
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20-Dec-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x64: Add x86_64 support
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