Make kernel log buffer derived from cmake config

This removes the explicit CMake configuration for the kernel log buffer
and replaces it with a #define that is enabled for the required
configurations.

Signed-off-by: Curtis Millar <curtis@curtism.me>

KernelBenchmarksTrackUtilisation: Add more stats

For each thread also track number of times scheduled, number of kernel
entries and amount of cycles spent inside the kernel. Also add
core-wide totals for each.

Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>

KernelBenchmarksTrackUtilisation: Fix for SMP

Create per-node global definitions for utilization variables.
This enables the tracking to more cleanly work on SMP configurations.
As resetting and starting the counters via SysBenchmarkResetLog only
updates the counters of the current thread and idle thread on the
current node it was not possible to accurately record utilization
statistics across multiple nodes. Now each node can have its tracking
independently started, stopped and queried. It is possible to add
additional syscalls in the future for doing this for all nodes in a
single syscall.

Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>

replacing all ifndef with pargma once

All the kernel header files now use pargma once rather than the ifndef,
as the pre-processed C files do not change while header files
are protected with pargma once. This will also solve any naming issues
caused by ifndef.

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

Revert "Cache FPU enable state on all platforms"

This reverts commit 186180cf309b365b45c162f7a1f5931f0fc05d7c.

Cache FPU enable state on all platforms

This change broadens the caching of the FPU enable/disable bit from arm
to all platforms to ensure that on x86 time is not wasted on the
fastpath disabling or enabling an already disabled/enabled FPU.

Revert the recent changes to Faster FPU switch

These changes need to be reverted until we can properly test the changes
with all of our hardware online (currently we cannot test on x86
hardware).

This reverts commit a0aeec3b304d16909619bc847197df221c73a0c4.
This reverts commit af0fdc82c23f1e7e3f1e568f6987f5afd0d2150a.
This reverts commit a190a14ecaae688a6b40dd0a699b8f49c2c0631e.

Cache FPU enable state on all platforms

This change broadens the caching of the FPU enable/disable bit from arm
to all platforms to ensure that on x86 time is not wasted on the
fastpath disabling or enabling an already disabled/enabled FPU.

mcs: configurable scheduling context size

This allows users to define custom amounts of refills without
increasing the scheduling context size system wide.

also add libsel4 functions for refill size

mcs: add periodic scheduling

This commit adds periodic scheduling with sporadic servers.

mcs: tickless scheduler implementation

This changes the budget/remaining fields in scheduling contexts
to contain timer ticks, not number of abstract sel4ticks.

seL4_SchedControl_Configure now takes microseconds, not ticks.

This commit is plat-independant - the platform and arch specific
timer code follows in later commits.

mcs: Add a scheduling context object

This is the first part of the seL4 MCS. This commit:

* adds a scheduling context object. Threads without scheduling
context objects cannot be scheduled.
* replaces tcbTimeSlice with the scheduling context object
* adds seL4_SchedControl caps for each core
* adds seL4_SchedControl_Configure which allows users to configure
amount of ticks a scheduling context has, and set a core for the
scheduling context.
* adds seL4_SchedContext_Bind, Unbind and UnbindObject, which allows
a tcb to be bound to a scheduling context.

[SMP] Abstracted IRQ indexing to handle PPIs

irq_t is now a "virtual" interrupt type that encapsulates the
information of the core in case of a private interrupt. There is a
couple of macros that need to be defined on the interrupt controller
level to translate between virtual and hardware IRQs.

Boot code: Statically allocate idle thread

The idle thread is not managed at user-level and so it can instead be
statically allocated. This simplifies the boot code and increments
towards being easier to formally verify.

boot: implement intStateIRQNode as an array

It turns out that verifying this is easier than if intStateIRQNode is a
pointer that is statically initialised to point to another array.

Compile time abstraction for calling getCurrentCPUIndex

This defines a CURRENT_CPU_INDEX() macro that resolves to a constant 0 in the absence of
SMP, or a call to getCurrentCPUIndex in the presence of SMP. This provides a way to use
per-core data structures, without additional guards, in a way that is nearly invisible
to verification

Define SchedulerAction_ChooseNewThread as 1

1 is never a valid tcb, and ~0 on x64 results in 0x00000000FFFFFFFF,
which could be a valid tcb.

Correct L2 bitmap size calculation and put it in one place

This corrects the calculation of the L2 bitmap size to correctly handle cases where the
requested num priorities is not a clean multiple of the wordBits

SMP: Introduce ENABLE_SMP_SUPPORT

- Make it more readable and less confusing compared to the 'CONFIG_MAX_NUM_NODES > 1' check

Fix licenses (the rest)

SELFOUR-880: add seL4_DebugDumpScheduler

- when CONFIG_DEBUG is enabled, track all threads
- when CONFIG_PRINTING is enabled, provide seL4_DebugDumpScheduler which
allows the user to dump the state of the kernel scheduler.

Move arch independent functions to generic files and HAVE_FPU config

x86: move current active FPU owner to node state

x86: define number of restore since switch as node state

s/D61/DATA61/ in license headers for consistency

ARM/SMP: Prepare for ARM SMP adding stubs

Currently building ARM/SMP is broken. This commit:
1- Makes it possible to build ARM/SMP with stubs. Run-time SMP for ARM
DOES NOT WORK.
2- Can be a reference for future SMP targets to follow in order to
layout/add the minimal required files and functions needed to support SMP.
3- Builds for Sabre only. In order to support other platforms, ipi
interrupt ID should be defined in machine.h

SMP: Abstract architecture/platform independent parts of smp.h and ipi.h

This commit is a re-arrangement of SMP directory structure to make it
easier for other architectures/platforms (in general) and ARM (in
particular) to add SMP support.

* new include/smp directory to act as a centralised container of
"shared" architecture-independent SMP headers.
This makes it clearer what's needed for other architecture/platform to
support SMP.
* Each platform can define its own unique ipi.[h|c] that make sense,
since ipi implementation is SoC/platform dependent.

Remove unneeded usages of `VISIBLE`

Using `VISIBLE` where it is not needed limits the ability for the
compiler to optimize, especially when using whole program optimizations

Revert SELFOUR-242

This reverts commits
3aee0ab7b3ae5ff5294192526fb00823b49048b5
6b6b965528d16c1e4c946fb920fb95060f84424f
a1421832acd19ed5ede71640af82b982708207c2

SELFOUR-242: invert bitfield scheduler & optimise

This commit does the following:

* invert the bit field scheduler for better cache performance for high priority threads
* peeks into the bitfield scheduler to allow fastpath to be leveraged when IPC occurs from lo --> hi priority threads if correct

Remove arch/machine.h include from statedata.h

statedata.h gets included from arch/machine.h, and statedata
does not require any of the machine.h definitions.

As a result of removing this various other, previously missing,
includes need to be added

Replace #pragma once with include guards

SELFOUR-632: implement cores non-architecture dependent structres

SELFOUR-630:preliminary booting application processors
- update core detection code and Kconfig file
- update kernel stack managment so that BSP does not use boot stack before IPI APs
- move arch dependant data to a single structure
- add cache line size to Kconfig
- add cpu indexing and apic id mapping
- boot APs to halting state
- add guard for kernel stack if there is only one core

Revert "Merge pull request #358 in SEL4/sel4 from ~AZARRABI/sel4:multicore to master"

This reverts commit ce2f666bb811c5e4c779829fcb09d5a189ebcdbb, reversing
changes made to dc183f96b81f2344d7d0d910fc430f924eaae940.

Revert "[STYLE_FIX]"

This reverts commit d29f743bbcc3acff2f61b40dedb4fe0839db38b8.

[STYLE_FIX]

SELFOUR-630:preliminary booting application processors
- update core detection code and Kconfig file
- update kernel stack managment so that BSP does not use boot stack before IPI APs
- move arch dependant data to a single structure
- add cache line size to Kconfig
- add cpu indexing and apic id mapping
- boot APs to halting state
- add guard for kernel stack if there is only one core

SELFOUR-518: User-level log buffer

Remove global ksLog and use KS_LOG_PPTR instead

Benchmark - Log buffer: use global page table

Refactor duplicated code in hardware.h

One copy to rule them all.

Mark tlbLockCount as visible so it is not discarded

This variable is referenced in assembler and needs to not get discarded
by the optimizer prior to linking.

Make lockTLBEntry comply with the decompiler

lockTLBEntry, an assembly function, had tlb_lock_count as a symbol that
needed to be placed sufficiently close to be loaded and stored with
offset-from-pc addressing. When assembled, the symbol would turn up
between functions, as opposed to within a literal pool (it's a variable,
not a constant) or the .bss / data sections. The decompiler doesn't
handle that use case, and likely won't. This change turns
tlb_lock_count into a C global variable (so that it will be placed in
the .bss / data sections), and splits lockTLBEntry into two parts so the
critical section will still fit in a 64-byte aligned region, and
therefore be guaranteed to live within a single page.

unsigned int -> word_t

Rename uint32_t -> word_t in any relevant places

Using bitfields to track for which priorities there exist non-empty ready queues.

Background
seL4 organizes threads into ready queues, of which there is one for each
domain, for each priority level. The ready queue for a given
domain/priority combination can be found by indexing the array
`ksReadyQueues` with "domain*num_priorities + priority".

Current scheduler implementation
To find the non-empty ready queue with the maximum priority for the current domain,
seL4 iterates through `ksReadyQueues`, starting with the element
corresponding to the current domain and maximum possible priority, and
decrementing the priority until a non-empty queue is found. This is
problematic in cases where the only ready threads have low priorities,
as iterating through many elements of an array effectively flushes the
cache.

Changes in this patch
This patch replaces the iteration with a lookup into a table of
bitfields per domain. Using bitfields allows the kernel to determine the
highest priority level with a non-empty ready queue for the current
domain by counting the leading zeroes in bitfields. This removes the
negative cache effects of iterating through an array.

Implementation details
For each domain, a multilevel table of bitfields is maintained which
stores the priority levels within that domain for which there exist
ready threads. On a 32-bit architecture, the top level of the table is a 32-bit bitfield where if
the ith bit is set, there is at least 1 priority level in
[i*32..i*32+31] with a non-empty ready queue. The positions of bits in
this bitfield are used as indices into the second level table, which is
an array of 32-bit bitfields. The ith bit of the jth bitfield in this
array set to 1, indicates that priority level j*32+i has a non-empty
ready queue.

Release snapshot