Searched refs:sih (Results 26 - 50 of 84) sorted by relevance

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/netgear-R7000-V1.0.7.12_1.2.5/src/shared/
H A Dhndmips.c85 si_getirq(si_t *sih) argument
94 osh = si_osh(sih);
95 flag = si_flag(sih);
97 idx = si_coreidx(sih);
99 if ((regs = si_setcore(sih, MIPS74K_CORE_ID, 0)) != NULL) {
108 } else if ((regs = si_setcore(sih, MIPS33_CORE_ID, 0)) != NULL) {
127 si_setcoreidx(sih, idx);
137 si_irq(si_t *sih) argument
139 uint irq = si_getirq(sih);
141 irq = si_flag(sih)
147 si_clearirq(si_t *sih, uint irq) argument
174 si_setirq(si_t *sih, uint irq, uint coreid, uint coreunit) argument
225 si_mips_init(si_t *sih, uint shirqmap) argument
338 si_cpu_clock(si_t *sih) argument
394 si_mem_clock(si_t *sih) argument
431 do_router_coma(si_t *sih, void *dmem, int delay) argument
761 si_router_coma(si_t *sih, int reset, int delay) argument
818 mips_pmu_setclock_4706(si_t *sih, uint32 mipsclock, uint32 ddrclock, uint32 axiclock) argument
917 mips_pmu_setclock(si_t *sih, uint32 mipsclock, uint32 ddrclock, uint32 axiclock) argument
1194 si_mips_setclock(si_t *sih, uint32 mipsclock, uint32 siclock, uint32 pciclock) argument
1780 si_memc_get_ncdl(si_t *sih) argument
1828 hnd_cpu_reset(si_t *sih) argument
[all...]
H A Dhndchipc.c81 BCMATTACHFN(si_serial_init)(si_t *sih, si_serial_init_fn add) argument
90 osh = si_osh(sih);
92 cc = (chipcregs_t *)si_setcoreidx(sih, SI_CC_IDX);
96 rev = sih->ccrev;
97 cap = sih->cccaps;
101 irq = si_irq(sih);
103 if (CCPLL_ENAB(sih) && pll == PLL_TYPE1) {
112 baud_base = si_alp_clock(sih);
123 baud_base = si_clock(sih);
161 hnd_jtagm_init(si_t *sih, uin argument
203 hnd_jtagm_disable(si_t *sih, void *h) argument
234 jtag_scan(si_t *sih, void *h, uint irsz, uint32 ir0, uint32 ir1, uint drsz, uint32 dr0, uint32 *dr1, bool rti) argument
304 si_cc_register_isr(si_t *sih, cc_isr_fn isr, uint32 ccintmask, void *cbdata) argument
343 si_cc_isr(si_t *sih, chipcregs_t *regs) argument
[all...]
H A Dsflash.c53 sflash_init(si_t *sih, chipcregs_t *cc) argument
59 ASSERT(sih);
61 osh = si_osh(sih);
65 sflash.type = sih->cccaps & CC_CAP_FLASH_MASK;
245 sflash_read(si_t *sih, chipcregs_t *cc, uint offset, uint len, uchar *buf) argument
250 ASSERT(sih);
265 if (sih->ccrev == 12)
295 sflash_poll(si_t *sih, chipcregs_t *cc, uint offset) argument
299 ASSERT(sih);
301 osh = si_osh(sih);
336 sflash_write(si_t *sih, chipcregs_t *cc, uint offset, uint length, const uchar *buffer) argument
504 sflash_erase(si_t *sih, chipcregs_t *cc, uint offset) argument
541 sflash_commit(si_t *sih, chipcregs_t *cc, uint offset, uint len, const uchar *buf) argument
[all...]
H A Dbcmsrom.c84 static uint8* srom_offset(si_t *sih, void *curmap) argument
86 if (sih->ccrev <= 31)
88 if ((sih->cccaps & CC_CAP_SROM) == 0)
90 if (BUSTYPE(sih->bustype) == SI_BUS)
115 static int initvars_srom_si(si_t *sih, osl_t *osh, void *curmap, char **vars, uint *count);
117 static int initvars_tcm_pcidev(si_t *sih, osl_t *osh, void *curmap, char **vars, uint *count);
120 static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, uint *count);
121 static int initvars_cis_pci(si_t *sih, osl_t *osh, void *curmap, char **vars, uint *count);
122 static int initvars_cis_pcmcia(si_t *sih, osl_t *osh, char **vars, uint *count);
125 static int initvars_flash_si(si_t *sih, cha
1992 srom_var_init(si_t *sih, uint bustype, void *curmap, osl_t *osh, char **vars, uint *count) argument
2050 srom_read(si_t *sih, uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf, bool check_crc) argument
2144 srom_write(si_t *sih, uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf) argument
2417 srom_write_short(si_t *sih, uint bustype, void *curmap, osl_t *osh, uint byteoff, uint16 value) argument
2650 get_si_pcmcia_srom(si_t *sih, osl_t *osh, uint8 *pcmregs, uint boff, uint16 *srom, uint bsz, bool check_crc) argument
2713 set_si_pcmcia_srom(si_t *sih, osl_t *osh, uint8 *pcmregs, uint boff, uint16 *srom, uint bsz) argument
5207 srom_cc_cmd(si_t *sih, osl_t *osh, void *ccregs, uint32 cmd, uint wordoff, uint16 data) argument
5236 sprom_read_pci(osl_t *osh, si_t *sih, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc) argument
5342 otp_read_pci(osl_t *osh, si_t *sih, uint16 *buf, uint bufsz) argument
5393 srom_otp_write_region_crc(si_t *sih, uint nbytes, uint16* buf16, bool write) argument
5484 dbushost_initvars_flash(si_t *sih, osl_t *osh, char **base, uint len) argument
5495 initvars_flash(si_t *sih, osl_t *osh, char **base, uint len) argument
5583 initvars_flash_si(si_t *sih, char **vars, uint *count) argument
5916 initvars_srom_pci(si_t *sih, void *curmap, char **vars, uint *count) argument
6232 initvars_cis_pci(si_t *sih, osl_t *osh, void *curmap, char **vars, uint *count) argument
6320 initvars_cis_pcmcia(si_t *sih, osl_t *osh, char **vars, uint *count) argument
6396 srom_size(si_t *sih, osl_t *osh) argument
6453 initvars_cis_usbdriver(si_t *sih, osl_t *osh, char **vars, uint *count) argument
6483 initvars_srom_si_usbdriver(si_t *sih, osl_t *osh, char **vars, uint *varsz) argument
6617 initvars_srom_si_bl(si_t *sih, osl_t *osh, void *curmap, char **vars, uint *varsz) argument
6692 initvars_srom_si(si_t *sih, osl_t *osh, void *curmap, char **vars, uint *varsz) argument
7071 srom_load_nvram(si_t *sih, osl_t *osh, uint8 *pcis[], uint ciscnt, char **vars, uint *varsz) argument
7171 initvars_srom_si(si_t *sih, osl_t *osh, void *curmap, char **vars, uint *varsz) argument
7325 initvars_srom_si(si_t *sih, osl_t *osh, void *curmap, char **vars, uint *varsz) argument
7336 initvars_srom_si(si_t *sih, osl_t *osh, void *curmap, char **vars, uint *varsz) argument
7391 initvars_tcm_pcidev(si_t *sih, osl_t *osh, void *curmap, char **vars, uint *varsz) argument
7407 initvars_srom_si(si_t *sih, osl_t *osh, void *curmap, char **vars, uint *varsz) argument
7420 srom_var_deinit(si_t *sih) argument
[all...]
H A Dbcmotp.c77 typedef void* (*otp_init_t)(si_t *sih);
79 typedef int (*otp_read_region_t)(si_t *sih, int region, uint16 *data, uint *wlen);
82 typedef int (*otp_cis_append_region_t)(si_t *sih, int region, char *vars, int count);
83 typedef int (*otp_lock_t)(si_t *sih);
112 si_t *sih; /* Saved sb handle */ member in struct:__anon20323
378 si_t *sih; local
389 sih = oi->sih;
390 ASSERT(sih != NULL);
394 if (si_is_sprom_available(sih))
833 ipxotp_init(si_t *sih) argument
2114 _ipxotp_cis_append_region(si_t *sih, int region, char *vars, int count) argument
2278 ipxotp_cis_append_region(si_t *sih, int region, char *vars, int count) argument
2640 hndotp_init(si_t *sih) argument
3345 hndotp_cis_append_region(si_t *sih, int region, char *vars, int count) argument
3712 otp_init(si_t *sih) argument
3780 otp_read_region(si_t *sih, int region, uint16 *data, uint *wlen) argument
3812 otp_read_word(si_t *sih, uint wn, uint16 *data) argument
3857 otp_write_region(si_t *sih, int region, uint16 *data, uint wlen, uint flags) argument
3889 otp_write_word(si_t *sih, uint wn, uint16 data) argument
3925 otp_cis_append_region(si_t *sih, int region, char *vars, int count) argument
3937 otp_lock(si_t *sih) argument
[all...]
H A Dload.c247 load(si_t *sih) argument
255 if (sih->ccrev == 12)
266 bootdev = soc_boot_dev((void *)sih);
310 set_sflash_div(si_t *sih) argument
312 uint idx = si_coreidx(sih);
313 osl_t *osh = si_osh(sih);
320 cc = si_setcoreidx(sih, SI_CC_IDX);
324 if ((sih->ccrev == 38) && ((sih->chipst & (1 << 4)) != 0))
327 fltype = sih
379 si_t *sih; local
[all...]
H A Dnandcore.c84 static int nandcore_poll(si_t *sih, nandregs_t *nc);
86 hndnand_t *nandcore_init(si_t *sih);
161 ASSERT(nfl->sih);
173 osh = si_osh(nfl->sih);
201 if ((ret = nandcore_poll(nfl->sih, nc)) < 0)
271 ASSERT(nfl->sih);
283 osh = si_osh(nfl->sih);
357 ret = nandcore_poll(nfl->sih, nc);
422 ASSERT(nfl->sih);
423 osh = si_osh(nfl->sih);
520 nandcore_init(si_t *sih) argument
766 nandcore_poll(si_t *sih, nandregs_t *nc) argument
825 si_t *sih = nfl->sih; local
873 si_t *sih = nfl->sih; local
957 si_t *sih = nfl->sih; local
1060 si_t *sih = nfl->sih; local
1086 si_t *sih = nfl->sih; local
1184 si_t *sih = nfl->sih; local
1248 si_t *sih = nfl->sih; local
[all...]
H A Dsbutils.c137 sb_coreid(si_t *sih) argument
142 sii = SI_INFO(sih);
149 sb_intflag(si_t *sih) argument
156 sii = SI_INFO(sih);
159 origidx = si_coreidx(sih);
160 corereg = si_setcore(sih, CC_CORE_ID, 0);
164 sb_setcoreidx(sih, origidx);
171 sb_flag(si_t *sih) argument
176 sii = SI_INFO(sih);
183 sb_setint(si_t *sih, in argument
256 sb_corevendor(si_t *sih) argument
268 sb_corerev(si_t *sih) argument
283 sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val) argument
302 sb_core_cflags(si_t *sih, uint32 mask, uint32 val) argument
328 sb_core_sflags(si_t *sih, uint32 mask, uint32 val) argument
352 sb_iscoreup(si_t *sih) argument
375 sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) argument
482 sb_corereg_addr(si_t *sih, uint coreidx, uint regoff) argument
636 sb_scan(si_t *sih, void *regs, uint devid) argument
662 sb_setcoreidx(si_t *sih, uint coreidx) argument
775 sb_numaddrspaces(si_t *sih) argument
789 sb_addrspace(si_t *sih, uint asidx) argument
800 sb_addrspacesize(si_t *sih, uint asidx) argument
843 sb_taclear(si_t *sih, bool details) argument
951 sb_commit(si_t *sih) argument
987 sb_core_disable(si_t *sih, uint32 bits) argument
1047 sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits) argument
1120 sb_set_initiator_to(si_t *sih, uint32 to, uint idx) argument
1221 sb_dumpregs(si_t *sih, struct bcmstrbuf *b) argument
[all...]
H A Daiutils.c35 #define BCM47162_DMP() ((CHIPID(sih->chip) == BCM47162_CHIP_ID) && \
36 (CHIPREV(sih->chiprev) == 0) && \
39 #define BCM5357_DMP() (((CHIPID(sih->chip) == BCM5357_CHIP_ID) || \
40 (CHIPID(sih->chip) == BCM4749_CHIP_ID)) && \
41 (sih->chippkg == BCM5357_PKG_ID) && \
43 #define BCM4707_DMP() (BCM4707_CHIP(CHIPID(sih->chip)) && \
49 get_erom_ent(si_t *sih, uint32 **eromptr, uint32 mask, uint32 match) argument
55 ent = R_REG(si_osh(sih), *eromptr);
83 get_asd(si_t *sih, uint32 **eromptr, uint sp, uint ad, uint st, uint32 *addrl, uint32 *addrh, argument
88 asd = get_erom_ent(sih, erompt
183 remap_coreid(si_t *sih, uint coreid) argument
202 remap_corerev(si_t *sih, uint corerev) argument
227 ai_scan(si_t *sih, void *regs, uint devid) argument
470 ai_setcoreidx(si_t *sih, uint coreidx) argument
535 ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size) argument
621 ai_numaddrspaces(si_t *sih) argument
628 ai_addrspace(si_t *sih, uint asidx) argument
649 ai_addrspacesize(si_t *sih, uint asidx) argument
669 ai_flag(si_t *sih) argument
694 ai_flag_alt(si_t *sih) argument
719 ai_setint(si_t *sih, int siflag) argument
724 ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val) argument
740 ai_corevendor(si_t *sih) argument
751 ai_corerev(si_t *sih) argument
763 ai_iscoreup(si_t *sih) argument
785 ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val) argument
878 ai_corereg_addr(si_t *sih, uint coreidx, uint regoff) argument
933 ai_core_disable(si_t *sih, uint32 bits) argument
983 ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits) argument
1033 ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val) argument
1069 ai_core_cflags(si_t *sih, uint32 mask, uint32 val) argument
1106 ai_core_sflags(si_t *sih, uint32 mask, uint32 val) argument
1146 ai_dumpregs(si_t *sih, struct bcmstrbuf *b) argument
1314 ai_view(si_t *sih, bool verbose) argument
1342 ai_viewall(si_t *sih, bool verbose) argument
1384 ai_enable_backplane_timeouts(si_t *sih) argument
1400 ai_clear_backplane_to(si_t *sih) argument
[all...]
H A Dccsflash.c38 hndsflash_t *ccsflash_init(si_t *sih);
58 ccsflash_init(si_t *sih) argument
65 ASSERT(sih);
68 if (sih->ccrev == 42)
71 if ((cc = (chipcregs_t *)si_setcoreidx(sih, SI_CC_IDX)) == NULL)
77 osh = si_osh(sih);
80 ccsflash.sih = sih;
89 ccsflash.type = sih->cccaps & CC_CAP_FLASH_MASK;
271 si_t *sih local
322 si_t *sih = sfl->sih; local
365 si_t *sih = sfl->sih; local
533 si_t *sih = sfl->sih; local
571 si_t *sih = sfl->sih; local
[all...]
H A Dhndnand.c35 extern hndnand_t *nflash_init(si_t *sih);
36 extern hndnand_t *nandcore_init(si_t *sih);
40 hndnand_init(si_t *sih) argument
44 ASSERT(sih);
50 origidx = si_coreidx(sih);
54 hndnand = nflash_init(sih);
58 hndnand = nandcore_init(sih);
61 si_setcoreidx(sih, origidx);
H A Dspiflash.c57 static int spiflash_open(si_t *sih, qspiregs_t *qspi);
336 osl_t *osh = si_osh(spifl->sih);
431 si_t *sih = spifl->sih; local
438 ASSERT(sih);
439 osh = si_osh(sih);
508 si_t *sih = spifl->sih; local
516 ASSERT(sih);
517 osh = si_osh(sih);
671 si_t *sih = spifl->sih; local
701 spiflash_init(si_t *sih) argument
944 spiflash_open(si_t *sih, qspiregs_t *qspi) argument
971 si_t *sih = spifl->sih; local
1026 si_t *sih = spifl->sih; local
1115 si_t *sih = spifl->sih; local
1145 si_t *sih = spifl->sih; local
1185 si_t *sih = spifl->sih; local
[all...]
H A Dnvram_rw.c142 si_t *sih; local
144 sih = (si_t *)si;
155 si_gpioouten(sih, ((uint32) 1 << gpio), 0, GPIO_DRV_PRIORITY);
165 si_t * sih = (si_t *)si; local
167 if ((gpio = nvram_resetgpio_init((void *)sih)) < 0)
172 if (si_gpioin(sih) & ((uint32) 1 << gpio))
216 BCMINITFN(find_nvram)(si_t *sih, bool embonly, bool *isemb) argument
229 bootdev = soc_boot_dev((void *)sih);
233 nfl_info = hndnand_init(sih);
242 sfl_info = hndsflash_init(sih);
323 si_t *sih; local
376 si_t *sih; local
576 find_devinfo_nvram(si_t *sih) argument
602 si_t *sih = (si_t *)si; local
[all...]
H A Daisdram-ca9.c42 extern void si_mem_setclock(si_t *sih, uint32 ddrclock);
791 ddr_regs_init(si_t *sih, ddrcregs_t *ddr, unsigned int ddr_table[]) argument
797 osh = si_osh(sih);
804 int rewrite_mode_registers(void *sih) argument
812 osh = si_osh((si_t *)sih);
813 ddr = (ddrcregs_t *)si_setcore((si_t *)sih, NS_DDR23_CORE_ID, 0);
990 Program_Digital_Core_Power_Voltage(si_t *sih) argument
1011 osh = si_osh(sih);
1012 chipcb = (chipcommonbregs_t *)si_setcore(sih, NS_CCB_CORE_ID, 0);
1019 if (CHIPID(sih
1103 si_t *sih; local
[all...]
H A Dmin_osl.c680 si_t *sih; local
683 sih = si_kattach(SI_OSH);
685 if (sih == NULL)
689 si_mips_init(sih, 0);
692 si_arm_init(sih);
698 cpu_clock = si_cpu_clock(sih);
700 c0counts_per_ms = si_cpu_clock(sih) / (1000 * c0counts_per_cycle);
703 if ((sih->chippkg != HDLSIM_PKG_ID) && (sih->chippkg != HWSIM_PKG_ID))
704 si_serial_init(sih, serial_ad
[all...]
H A Dflashutl.c49 static si_t *sih = NULL; variable
84 sih = si_kattach(SI_OSH);
85 ASSERT(sih);
87 osh = si_osh(sih);
89 cc = (chipcregs_t *)si_setcoreidx(sih, SI_CC_IDX);
96 if (sih->ccrev == 12)
100 sflash = sflash_init(sih, cc);
525 err = sflash_commit(sih, cc, off, len, data);
542 err = sflash_commit(sih, cc, off, numbytes, NULL);
568 err = sflash_commit(sih, c
[all...]
/netgear-R7000-V1.0.7.12_1.2.5/src/include/
H A Dhndmips.h24 extern void si_mips_init(si_t *sih, uint shirq_map_base);
25 extern bool si_mips_setclock(si_t *sih, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
27 extern uint32 si_memc_get_ncdl(si_t *sih);
H A Dnicpci.h90 extern uint pcie_readreg(si_t *sih, struct sbpcieregs *pcieregs, uint addrtype, uint offset);
91 extern uint pcie_writereg(si_t *sih, struct sbpcieregs *pcieregs, uint addrtype, uint offset,
107 extern void *pcicore_init(si_t *sih, osl_t *osh, void *regs);
157 #define PCIE_MRRS_OVERRIDE(sih) \
158 ((pi->sih->boardvendor == VENDOR_APPLE) && \
159 ((pi->sih->boardtype == BCM94331X19) || \
160 (pi->sih->boardtype == BCM94331X28) || \
161 (pi->sih->boardtype == BCM94331X28B) || \
162 (pi->sih->boardtype == BCM94331X29B) || \
163 (pi->sih
[all...]
H A Dbcmnvram.h61 extern int nvram_init(void *sih);
62 extern int nvram_deinit(void *sih);
67 extern int devinfo_nvram_init(void *sih);
83 extern int nvram_reset(void *sih);
89 extern void nvram_exit(void *sih);
112 extern int BCMINITFN(nvram_resetgpio_init)(void *sih);
H A Dhndsflash.h40 si_t *sih; member in struct:hndsflash
49 hndsflash_t *hndsflash_init(si_t *sih);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/mips/brcm-boards/bcm947xx/
H A Dpcibios.c56 #define sih bcm947xx_sih macro
67 ret = hndpci_read_config(sih, bus->number, PCI_SLOT(devfn),
81 ret = hndpci_write_config(sih, bus->number, PCI_SLOT(devfn),
126 if (sih->chip == BCM4716_CHIP_ID) {
131 if (!(sih = si_kattach(SI_OSH)))
136 hndpci_init(sih);
227 hndpci_arb_park(sih, PCI_PARK_NVRAM);
286 regs = si_setcoreidx(sih, PCI_SLOT(dev->devfn));
287 coreidx = si_coreidx(sih);
288 coreid = si_coreid(sih);
[all...]
H A Dsetup.c109 #define sih bcm947xx_sih macro
137 if (CHIPID(sih->chip) == BCM4706_CHIP_ID)
138 hndpci_deinit(sih);
143 si_gpioout(sih, lp, 0, GPIO_DRV_PRIORITY);
144 si_gpioouten(sih, lp, lp, GPIO_DRV_PRIORITY);
153 si_gpioout(sih, reset, 0, GPIO_DRV_PRIORITY);
154 si_gpioouten(sih, reset, reset, GPIO_DRV_PRIORITY);
167 hnd_cpu_reset(sih);
177 si_watchdog(sih, 0);
204 serial_setup(si_t *sih) argument
[all...]
H A Dtime.c48 #define sih bcm947xx_sih macro
73 if (!(hz = si_cpu_clock(sih)))
76 bcm_chipname(sih->chip, cn, 8);
77 printk(KERN_INFO "CPU: BCM%s rev %d at %d MHz\n", cn, sih->chiprev,
138 si_watchdog_ms(sih, watchdog);
H A Dprom.c50 #define sih bcm947xx_sih macro
253 sih = si_kattach(SI_OSH);
255 idx = si_coreidx(sih);
256 if ((si_setcore(sih, DMEMC_CORE_ID, 0) != NULL) ||
257 (si_setcore(sih, DMEMS_CORE_ID, 0) != NULL)) {
262 si_coreaddrspaceX(sih, asidx, &addr, &size);
273 si_setcoreidx(sih, idx);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/mtd/maps/
H A Dbcm947xx-flash.c48 #define sih bcm947xx_sih macro
100 coreidx = si_coreidx(sih);
103 if ((cc = si_setcore(sih, CC_CORE_ID, 0))) {
119 si_setcoreidx(sih, coreidx);

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