1/* 2 * Broadcom QSPI serial flash interface 3 * 4 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: $ 19 */ 20 21#include <bcm_cfg.h> 22#include <typedefs.h> 23#include <osl.h> 24#include <bcmutils.h> 25#include <siutils.h> 26#include <hndsoc.h> 27#include <sbhndcpu.h> 28#include <bcmdevs.h> 29#include <qspi_core.h> 30#include <hndsflash.h> 31#include <chipcommonb.h> 32 33#ifndef FLASH_SPI_MAX_PAGE_SIZE 34#define FLASH_SPI_MAX_PAGE_SIZE (256) 35#endif 36 37#ifdef BCMDBG 38#define SPIFL_MSG(args) printf args 39#else 40#define SPIFL_MSG(args) 41#endif /* BCMDBG */ 42 43#define MSPI_CALC_TIMEOUT(bytes, baud) ((((bytes * 9000)/baud) * 110)/100 + 1) 44 45/* Private global state */ 46static hndsflash_t spiflash; 47 48static int bspi_enabled = 1; 49static bool firsttime = TRUE; 50 51/* Prototype */ 52static int spiflash_read(hndsflash_t *spifl, uint offset, uint len, const uchar *buf); 53static int spiflash_write(hndsflash_t *spifl, uint offset, uint len, const uchar *buf); 54static int spiflash_erase(hndsflash_t *spifl, uint offset); 55static int spiflash_poll(hndsflash_t *spifl, uint offset); 56static int spiflash_commit(hndsflash_t *spifl, uint offset, uint len, const uchar *buf); 57static int spiflash_open(si_t *sih, qspiregs_t *qspi); 58 59/* Disable Boot SPI */ 60static void 61mspi_disable_bspi(osl_t *osh, qspiregs_t *qspi) 62{ 63 int i, j; 64 unsigned int lval; 65 66 if (bspi_enabled == 0) 67 return; 68 69 lval = R_REG(osh, &qspi->bspi_mast_n_boot_ctrl); 70 if ((lval & 1) == 1) 71 return; 72 73 for (i = 0; i < 1000; i++) { 74 lval = R_REG(osh, &qspi->bspi_busy_status); 75 if ((lval & 1) == 0) { 76 W_REG(osh, &qspi->bspi_mast_n_boot_ctrl, 0x1); 77 bspi_enabled = 0; 78 for (j = 0; j < 1000; j++); 79 return; 80 } 81 } 82} 83 84/* Enable Boot SPI */ 85static void 86mspi_enable_bspi(osl_t *osh, qspiregs_t *qspi) 87{ 88 unsigned int lval; 89 90 if (bspi_enabled == 1) 91 return; 92 93 lval = R_REG(osh, &qspi->bspi_mast_n_boot_ctrl); 94 if ((lval & 1) == 0) 95 return; 96 97 W_REG(osh, &qspi->bspi_mast_n_boot_ctrl, 0x0); 98 99 bspi_enabled = 1; 100 return; 101} 102 103static int 104mspi_wait(osl_t *osh, qspiregs_t *qspi, unsigned int timeout_ms) 105{ 106 unsigned int lval; 107 unsigned int loopCnt = ((timeout_ms * 1000) / 10) + 1; 108 unsigned int count; 109 int rc = -1; 110 111 /* We must wait mspi_spcr2 spe bit clear before reading mspi_mspi_status */ 112 while (1) { 113 lval = R_REG(osh, &qspi->mspi_spcr2); 114 if ((lval & MSPI_SPCR2_spe_MASK) == 0) 115 break; 116 } 117 118 /* Check status */ 119 for (count = 0; count < loopCnt; count++) { 120 lval = R_REG(osh, &qspi->mspi_mspi_status); 121 if (lval & MSPI_MSPI_STATUS_SPIF_MASK) { 122 rc = 0; 123 break; 124 } 125 126 /* Create some delay 5 times bigger */ 127 OSL_DELAY(100); 128 } 129 130 W_REG(osh, &qspi->mspi_mspi_status, 0); 131 if (rc) { 132 SPIFL_MSG(("Wait timeout\n")); 133 } 134 135 return rc; 136} 137 138static int 139mspi_writeread(osl_t *osh, qspiregs_t *qspi, unsigned char *w_buf, 140 unsigned char write_len, unsigned char *r_buf, unsigned char read_len) 141{ 142 unsigned int lval; 143 unsigned char i, len; 144 145 len = write_len + read_len; 146 for (i = 0; i < len; i++) { 147 if (i < write_len) { 148 /* Transmit Register File MSB */ 149 W_REG(osh, &qspi->mspi_txram[i * 2], (unsigned int)w_buf[i]); 150 } 151 152 lval = SPI_CDRAM_CONT | SPI_CDRAM_PCS_DISABLE_ALL | SPI_CDRAM_PCS_DSCK; 153 lval &= ~(1 << BSPI_Pcs_eUpgSpiPcs2); 154 /* Command Register File */ 155 W_REG(osh, &qspi->mspi_cdram[i], lval); 156 } 157 158 lval = SPI_CDRAM_PCS_DISABLE_ALL | SPI_CDRAM_PCS_DSCK; 159 lval &= ~(1 << BSPI_Pcs_eUpgSpiPcs2); 160 /* Command Register File */ 161 W_REG(osh, &qspi->mspi_cdram[len - 1], lval); 162 163 /* Set queue pointers */ 164 W_REG(osh, &qspi->mspi_newqp, 0); 165 W_REG(osh, &qspi->mspi_endqp, len - 1); 166 167 /* Start SPI transfer */ 168 lval = R_REG(osh, &qspi->mspi_spcr2); 169 lval |= MSPI_SPCR2_spe_MASK; 170 W_REG(osh, &qspi->mspi_spcr2, lval); 171 172 /* Wait for SPI to finish */ 173 if (mspi_wait(osh, qspi, MSPI_CALC_TIMEOUT(len, MAX_SPI_BAUD)) != 0) 174 return 0; 175 176 W_REG(osh, &qspi->mspi_write_lock, 0); 177 178 for (i = write_len; i < len; ++i) { 179 /* Data stored in the transmit register file LSB */ 180 r_buf[i-write_len] = (unsigned char)R_REG(osh, &qspi->mspi_rxram[1 + (i * 2)]); 181 } 182 183 return 1; 184} 185 186static int 187mspi_writeread_continue(osl_t *osh, qspiregs_t *qspi, unsigned char *w_buf, 188 unsigned char write_len, unsigned char *r_buf, unsigned char read_len) 189{ 190 unsigned int lval; 191 unsigned char i, len; 192 193 len = write_len + read_len; 194 for (i = 0; i < len; i++) { 195 if (i < write_len) 196 W_REG(osh, &qspi->mspi_txram[i * 2], (unsigned int)w_buf[i]); 197 198 lval = SPI_CDRAM_CONT | SPI_CDRAM_PCS_DISABLE_ALL | SPI_CDRAM_PCS_DSCK; 199 lval &= ~(1 << BSPI_Pcs_eUpgSpiPcs2); 200 W_REG(osh, &qspi->mspi_cdram[i], lval); 201 } 202 203 /* Set queue pointers */ 204 W_REG(osh, &qspi->mspi_newqp, 0); 205 W_REG(osh, &qspi->mspi_endqp, len - 1); 206 207 W_REG(osh, &qspi->mspi_write_lock, 1); 208 209 /* Start SPI transfer */ 210 lval = R_REG(osh, &qspi->mspi_spcr2); 211 lval |= MSPI_SPCR2_cont_after_cmd_MASK | MSPI_SPCR2_spe_MASK; 212 W_REG(osh, &qspi->mspi_spcr2, lval); 213 214 /* Wait for SPI to finish */ 215 if (mspi_wait(osh, qspi, MSPI_CALC_TIMEOUT(len, MAX_SPI_BAUD)) != 0) 216 return 0; 217 218 for (i = write_len; i < len; ++i) 219 r_buf[i-write_len] = (unsigned char)R_REG(osh, &qspi->mspi_rxram[1 + (i * 2)]); 220 221 return 1; 222} 223 224/* Command codes for the flash_command routine */ 225#define FLASH_READ 0x03 /* read data from memory array */ 226#define FLASH_READ_FAST 0x0B /* read data from memory array */ 227#define FLASH_PROG 0x02 /* program data into memory array */ 228#define FLASH_WREN 0x06 /* set write enable latch */ 229#define FLASH_WRDI 0x04 /* reset write enable latch */ 230#define FLASH_RDSR 0x05 /* read status register */ 231#define FLASH_WRST 0x01 /* write status register */ 232#define FLASH_EWSR 0x50 /* enable write status */ 233#define FLASH_WORD_AAI 0xAD /* auto address increment word program */ 234#define FLASH_AAI 0xAF /* auto address increment program */ 235 236#define SST_FLASH_CERASE 0x60 /* erase all sectors in memory array */ 237#define SST_FLASH_SERASE 0x20 /* erase one sector in memroy array */ 238#define SST_FLASH_RDID 0x90 /* read manufacturer and product id */ 239 240#define ATMEL_FLASH_CERASE 0x62 /* erase all sectors in memory array */ 241#define ATMEL_FLASH_SERASE 0x52 /* erase one sector in memroy array */ 242#define ATMEL_FLASH_RDID 0x15 /* read manufacturer and product id */ 243 244#define ATMEL_FLASH_PSEC 0x36 /* protect sector */ 245#define ATMEL_FLASH_UNPSEC 0x39 /* unprotect sector */ 246#define ATMEL_FLASH_RDPREG 0x3C /* read protect sector registers */ 247 248#define AMD_FLASH_CERASE 0xC7 /* erase all sectors in memory array */ 249#define AMD_FLASH_SERASE 0xD8 /* erase one sector in memroy array */ 250#define AMD_FLASH_RDID 0xAB /* read manufacturer and product id */ 251 252#define SPAN_FLASH_CERASE 0xC7 /* erase all sectors in memory array */ 253#define SPAN_FLASH_SERASE 0xD8 /* erase one sector in memory array */ 254#define SPAN_FLASH_RDID 0x9F /* read manufacturer and product id */ 255 256/* Spansion commands for 4-byte addressing */ 257#define SPAN_FLASH_BRWR 0x17 /* bank register write */ 258#define SPAN_FLASH_4PP 0x12 /* page program with 4-byte address */ 259#define SPAN_FLASH_4P4E 0x21 /* parameter 4-kB secotor erase with 4-byte address */ 260#define SPAN_FLASH_4SE 0xDC /* sectore erase with 4-byte address */ 261 262#define ST_FLASH_RDID 0x9F /* read manufacturer and product id */ 263#define ST_FLASH_RDFSR 0x70 /* read flag status register */ 264 265/* ATMEL's manufacturer ID */ 266#define ATMELPART 0x1F 267 268/* A list of ATMEL device ID's - add others as needed */ 269#define ID_AT25F512 0x60 270#define ID_AT25F512A 0x65 271#define ID_AT25F2048 0x63 272#define ID_AT26F004 0x04 273#define ID_AT25DF041A 0x44 274 275/* AMD's device ID */ 276#define AMD_S25FL002D 0x11 277 278/* SST's manufacturer ID */ 279#define SSTPART 0xBF 280 281/* A list of SST device ID's - add others as needed */ 282#define ID_SST25VF016B 0x41 283#define ID_SST25VF020 0x43 284#define ID_SST25VF040 0x44 285#define ID_SST25VF080 0x80 286 287/* Winbond/NexFlash's manufacturer ID */ 288#define NXPART 0xEF 289 290/* A list of NexFlash device ID's - add others as needed */ 291#define ID_NX25P20 0x11 292#define ID_NX25P40 0x12 293#define ID_W25X16 0x14 294#define ID_W25X32 0x15 295#define ID_W25X64 0x16 296 297/* StFlash's manufacturer ID */ 298#define STPART 0x12 299 300/* A list of StFlash device ID's - add others as needed */ 301#define ID_M25P40 0x12 302 303/* SPANSION manufacturer ID */ 304#define SPANPART 0x01 305 306/* SPANSION device ID's */ 307#define ID_SPAN25FL002A 0x11 308#define ID_SPAN25FL004A 0x12 309#define ID_SPAN25FL008A 0x13 310#define ID_SPAN25FL016A 0x14 311#define ID_SPAN25FL032A 0x15 312#define ID_SPAN25FL064A 0x16 313#define ID_SPAN25FL128A 0x17 314 315/* EON manufacturer ID */ 316#define EONPART 0x1C 317/* NUMONYX manufacturer ID */ 318#define NUMONYXPART 0x20 319/* Macronix manufacturer ID */ 320#define MACRONIXPART 0xC2 321 322/* JEDEC device ID */ 323#define ID_M25P64 0x17 324 325/* Use READ_ID (0x90) command 326 * Manufacturer Identification - 1 byte 327 * Device Identification - 2 bytes 328 * Extended Device Identification - 2 bytes 329 */ 330#define MSPI_IDS_READLEN 5 331 332/* Enable/disable BSPI 4-byte mode read */ 333static void 334spiflash_set_4byte_mode(hndsflash_t *spifl, int enable) 335{ 336 osl_t *osh = si_osh(spifl->sih); 337 qspiregs_t *qspi = (qspiregs_t *)spifl->core; 338 unsigned char cmd[1]; 339 340 /* Use MSPI to configure flash for entering/exiting 4-byte mode */ 341 mspi_disable_bspi(osh, qspi); 342 cmd[0] = SPI_WREN_CMD; 343 mspi_writeread(osh, qspi, cmd, 1, NULL, 0); 344 if (spifl->vendor_id == SPANPART) 345 cmd[0] = enable? SPAN_FLASH_BRWR : SPI_EX4B_CMD; 346 else 347 cmd[0] = enable? SPI_EN4B_CMD : SPI_EX4B_CMD; 348 mspi_writeread(osh, qspi, cmd, 1, NULL, 0); 349 cmd[0] = SPI_WRDI_CMD; 350 mspi_writeread(osh, qspi, cmd, 1, NULL, 0); 351 352 if (enable) { 353 /* Enable 32-bit address */ 354 OR_REG(osh, &qspi->bspi_bits_per_phase, BSPI_BITS_PER_PHASE_ADDR_MARK); 355 } else { 356 /* Disable 32-bit address */ 357 AND_REG(osh, &qspi->bspi_bits_per_phase, ~BSPI_BITS_PER_PHASE_ADDR_MARK); 358 } 359 360 /* BSPI by default */ 361 mspi_enable_bspi(osh, qspi); 362} 363 364static uint16 365NTOS(unsigned char *a) 366{ 367 uint16 v; 368 v = (a[0]*256) + a[1]; 369 return v; 370} 371 372static unsigned short 373mspi_read_id(osl_t *osh, qspiregs_t *qspi) 374{ 375 unsigned char cmd[4]; 376 unsigned char data[5]; 377 378 /* Try SST flashes read product id command */ 379 cmd[0] = SST_FLASH_RDID; 380 cmd[1] = 0; 381 cmd[2] = 0; 382 cmd[3] = 0; 383 if (mspi_writeread(osh, qspi, cmd, 4, data, 2)) { 384 if (data[0] == SSTPART || data[0] == NXPART) { 385 return NTOS(data); 386 } 387 } 388 389 /* Try ATMEL flashes read product id command */ 390 cmd[0] = ATMEL_FLASH_RDID; 391 if (mspi_writeread(osh, qspi, cmd, 1, data, 2)) { 392 if (data[0] == ATMELPART) { 393 return NTOS(data); 394 } 395 } 396 397 /* Try SPANSION flashes read product id command */ 398 cmd[0] = SPAN_FLASH_RDID; 399 if (mspi_writeread(osh, qspi, cmd, 1, data, 3)) { 400 if (data[0] == ATMELPART) { 401 return NTOS(data); 402 } 403 404 if ((data[0] == NUMONYXPART) || (data[0] == SPANPART) || 405 (data[0] == EONPART) || (data[0] == MACRONIXPART)) { 406 data[1] = data[2]; 407 return NTOS(data); 408 } 409 } 410 411 /* 412 * AMD_FLASH_RDID is the same as RES command for SPAN, 413 * so it has to be the last one. 414 */ 415 cmd[0] = AMD_FLASH_RDID; 416 cmd[1] = 0; 417 cmd[2] = 0; 418 cmd[3] = 0; 419 if (mspi_writeread(osh, qspi, cmd, 4, data, 2)) { 420 if (data[0] == AMD_S25FL002D || data[0] == STPART) { 421 return NTOS(data); 422 } 423 } 424 425 return 0; 426} 427 428static int 429bspi_sector_erase(hndsflash_t *spifl, qspiregs_t *qspi, unsigned int offset) 430{ 431 si_t *sih = spifl->sih; 432 osl_t *osh; 433 int result = 0; 434 unsigned char cmd[5]; 435 unsigned char data; 436 int idx; 437 438 ASSERT(sih); 439 osh = si_osh(sih); 440 switch (spifl->type) { 441 case QSPIFLASH_ST: 442 cmd[0] = SPI_WREN_CMD; 443 if ((result = mspi_writeread(osh, qspi, cmd, 1, NULL, 0)) != 1) 444 break; 445 446 idx = 0; 447 if (spifl->vendor_id == SPANPART && (spifl->device_id & 0xff) >= 0x19) 448 cmd[idx++] = (spifl->blocksize < (64 * 1024)) ? 449 SPAN_FLASH_4P4E : SPAN_FLASH_4SE; 450 else 451 cmd[idx++] = (spifl->blocksize < (64 * 1024)) ? SPI_SSE_CMD : SPI_SE_CMD; 452 if (spifl->size > 0x1000000) { 453 cmd[idx++] = ((offset & 0xFF000000) >> 24); 454 } 455 cmd[idx++] = ((offset & 0x00FF0000) >> 16); 456 cmd[idx++] = ((offset & 0x0000FF00) >> 8); 457 cmd[idx++] = (offset & 0x000000FF); 458 if ((result = mspi_writeread(osh, qspi, cmd, idx, NULL, 0)) != 1) 459 break; 460 461 /* Check for ST Write In Progress bit */ 462 do { 463 cmd[0] = SPI_RDSR_CMD; 464 if ((result = mspi_writeread(osh, qspi, cmd, 1, &data, 1)) != 1) 465 break; 466 } while(data & 0x01); /* busy check */ 467 468 if (result != 1) 469 break; 470 471 /* disable the write */ 472 cmd[0] = SPI_WRDI_CMD; 473 result = mspi_writeread(osh, qspi, cmd, 1, NULL, 0); 474 break; 475 476 case QSPIFLASH_AT: 477 cmd[0] = SPI_AT_PAGE_ERASE; 478 offset = offset << 1; 479 cmd[1] = ((offset & 0x00FF0000) >> 16); 480 cmd[2] = ((offset & 0x0000FF00) >> 8); 481 cmd[3] = (offset & 0x000000FF); 482 if ((result = mspi_writeread(osh, qspi, cmd, 4, NULL, 0)) != 1) 483 break; 484 485 /* Check for Atmel Ready bit */ 486 do { 487 cmd[0] = SPI_AT_STATUS; 488 if ((result = mspi_writeread(osh, qspi, cmd, 1, &data, 1)) != 1) 489 break; 490 } while(data & 0x80); /* busy check */ 491 492 if (result != 1) 493 break; 494 495 /* disable the write */ 496 cmd[0] = SPI_WRDI_CMD; 497 result = mspi_writeread(osh, qspi, cmd, 1, NULL, 0); 498 break; 499 } 500 501 return result; 502} 503 504static int 505bspi2_st_page_program(hndsflash_t *spifl, qspiregs_t *qspi, unsigned int offset, 506 unsigned char *buf, int len) 507{ 508 si_t *sih = spifl->sih; 509 osl_t *osh; 510 int result = 0; 511 int i, len_total; 512 static unsigned char cmd[FLASH_SPI_MAX_PAGE_SIZE+5]; 513 unsigned char data; 514 int idx; 515 516 ASSERT(sih); 517 osh = si_osh(sih); 518 if (len >(FLASH_SPI_MAX_PAGE_SIZE+4)) /* Max bytes per transaction */ 519 goto done; 520 521 cmd[0] = SPI_WREN_CMD; 522 if ((result = mspi_writeread(osh, qspi, cmd, 1, NULL, 0)) != 1) 523 goto done; 524 525 idx = 0; 526 if (spifl->vendor_id == SPANPART && (spifl->device_id & 0xff) >= 0x19) 527 cmd[idx++] = SPAN_FLASH_4PP; 528 else 529 cmd[idx++] = SPI_PP_CMD; 530 if (spifl->size > 0x1000000) { 531 cmd[idx++] = ((offset & 0xFF000000) >> 24); 532 } 533 cmd[idx++] = ((offset & 0x00FF0000) >> 16); 534 cmd[idx++] = ((offset & 0x0000FF00) >> 8); 535 cmd[idx++] = (offset & 0x000000FF); 536 537 /* 538 * If new SPI has fix for byte orderig, define FLASH_SPI_BYTE_ORDER_FIX 539 * to 1 in qspi_core.h 540 */ 541#if defined(IL_BIGENDIAN) && !defined(FLASH_SPI_BYTE_ORDER_FIX) 542 /* 543 * mspi does not handle byte ordering for be mode. Handle it here. 544 * Let's assume len is multiple of 4 545 */ 546 for (i = 0; i < len; i = i+4) { 547 cmd[i + idx + 0] = buf[i + 3]; 548 cmd[i + idx + 1] = buf[i + 2]; 549 cmd[i + idx + 2] = buf[i + 1]; 550 cmd[i + idx + 3] = buf[i + 0]; 551 } 552#else 553 for (i = 0; i < len; ++i) 554 cmd[i + idx] = buf[i]; 555#endif 556 557 i = 0; 558 len_total = len + idx; 559 560 while (len_total > 16) { 561 if ((result = mspi_writeread_continue(osh, qspi, cmd + i, 16, NULL, 0)) != 1) 562 goto done; 563 i += 16; 564 len_total -= 16; 565 } 566 567 if (len_total <= 16 && len_total > 0) { 568 if ((result = mspi_writeread(osh, qspi, cmd+i, len_total, NULL, 0)) != 1) 569 goto done; 570 } 571 572 do { 573 cmd[0] = SPI_RDSR_CMD; 574 if ((result = mspi_writeread(osh, qspi, cmd, 1, &data, 1)) != 1) 575 goto done; 576 } while(data & 0x01 /* busy*/); 577 578 /* disable the write */ 579 cmd[0] = SPI_WRDI_CMD; 580 if ((result = mspi_writeread(osh, qspi, cmd, 1, NULL, 0)) != 1) 581 goto done; 582 583done: 584 return result; 585} 586 587static int 588bspi2_at_page_program(osl_t *osh, qspiregs_t *qspi, hndsflash_t *spifl, unsigned int offset, 589 unsigned char *buf, int len) 590{ 591 int result = 0; 592 int i, len_total; 593 static unsigned char cmd[FLASH_SPI_MAX_PAGE_SIZE+4]; 594 unsigned char data; 595 uint32 page, byte, mask; 596 597 mask = spifl->blocksize - 1; 598 page = (offset & ~mask) << 1; 599 byte = offset & mask; 600 601 /* Read main memory page into buffer 1 */ 602 if (byte || (len < spifl->blocksize)) { 603 cmd[0] = SPI_AT_BUF1_LOAD; 604 cmd[1] = ((page & 0x00FF0000) >> 16); 605 cmd[2] = ((page & 0x0000FF00) >> 8); 606 cmd[3] = (page & 0x000000FF); 607 608 if ((result = mspi_writeread(osh, qspi, cmd, 4, NULL, 0)) != 1) 609 goto done; 610 611 do { 612 cmd[0] = SPI_AT_STATUS; 613 if ((result = mspi_writeread(osh, qspi, cmd, 1, &data, 1)) != 1) 614 goto done; 615 } while(!(data & SPI_AT_READY) /* not ready */); 616 } 617 618 /* Write into buffer 1 */ 619 cmd[0] = SPI_AT_BUF1_WRITE; 620 cmd[1] = ((byte & 0x00FF0000) >> 16); 621 cmd[2] = ((byte & 0x0000FF00) >> 8); 622 cmd[3] = (byte & 0x000000FF); 623 /* 624 * If new SPI has fix for byte orderig, define FLASH_SPI_BYTE_ORDER_FIX 625 * to 1 in qspi_core.h 626 */ 627#if defined(IL_BIGENDIAN) && !defined(FLASH_SPI_BYTE_ORDER_FIX) 628 /* 629 * mspi does not handle byte ordering for be mode. Handle it here. 630 * Let's assume len is multiple of 4 631 */ 632 for (i = 0; i < len; i = i+4) { 633 cmd[i+4] = buf[i+3]; 634 cmd[i+5] = buf[i+2]; 635 cmd[i+6] = buf[i+1]; 636 cmd[i+7] = buf[i]; 637 } 638#else 639 for (i = 0; i < len; ++i) 640 cmd[i+4] = buf[i]; 641#endif 642 643 i = 0; 644 len_total = len + 4; 645 646 while (len_total > 16) { 647 if ((result = mspi_writeread_continue(osh, qspi, cmd + i, 16, NULL, 0)) != 1) 648 goto done; 649 i += 16; 650 len_total -= 16; 651 } 652 653 if (len_total <= 16 && len_total > 0) { 654 if ((result = mspi_writeread(osh, qspi, cmd+i, len_total, NULL, 0)) != 1) 655 goto done; 656 } 657 658 /* Write buffer 1 into main memory page */ 659 cmd[0] = SPI_AT_BUF1_PROGRAM; 660 cmd[1] = ((page & 0x00FF0000) >> 16); 661 cmd[2] = ((page & 0x0000FF00) >> 8); 662 cmd[3] = (page & 0x000000FF); 663 result = mspi_writeread(osh, qspi, cmd, 4, NULL, 0); 664 665done: 666 return result; 667} 668 669static int bspi_poll(hndsflash_t *spifl, qspiregs_t *qspi, unsigned int offset) 670{ 671 si_t *sih = spifl->sih; 672 osl_t *osh; 673 int result = 1; 674 unsigned char cmd[4]; 675 unsigned char data; 676 677 ASSERT(sih); 678 679 osh = si_osh(sih); 680 681 switch (spifl->device_id & 0x00ff) 682 { 683 case 0x20: 684 do { 685 cmd[0] = ST_FLASH_RDFSR; 686 if ((result = mspi_writeread(osh, qspi, cmd, 1, &data, 1)) != 1) { 687 result = 0; 688 break; 689 } 690 } while ((data & 0x80) == 0); 691 break; 692 default: 693 break; 694 } 695 696 return result; 697} 698 699/* Initialize serial flash access */ 700hndsflash_t * 701spiflash_init(si_t *sih) 702{ 703 qspiregs_t *qspi; 704 uint16 device_id; 705 const char *name = ""; 706 osl_t *osh; 707 uint8 vendor_id; 708 int force_3byte_mode = 0; 709 710 ASSERT(sih); 711 712 /* Only support chipcommon revision == 42 for now */ 713 if (sih->ccrev != 42) 714 return NULL; 715 716 if ((qspi = (qspiregs_t *)si_setcore(sih, NS_QSPI_CORE_ID, 0)) == NULL) 717 return NULL; 718 719 if (!firsttime && spiflash.size != 0) 720 return &spiflash; 721 722 osh = si_osh(sih); 723 724 bzero(&spiflash, sizeof(spiflash)); 725 spiflash.sih = sih; 726 spiflash.core = (void *)qspi; 727 spiflash.read = spiflash_read; 728 spiflash.write = spiflash_write; 729 spiflash.erase = spiflash_erase; 730 spiflash.commit = spiflash_commit; 731 732 spiflash.device_id = device_id = mspi_read_id(osh, qspi); 733 spiflash.vendor_id = vendor_id = (device_id >> 8); 734 switch (vendor_id) { 735 case SPANPART: 736 case MACRONIXPART: 737 case NUMONYXPART: 738 case NXPART: 739 /* ST compatible */ 740 if (vendor_id == SPANPART) 741 name = "ST compatible"; 742 else if (vendor_id == MACRONIXPART) 743 name = "ST compatible (Marconix)"; 744 else if (vendor_id == NXPART) 745 name = "ST compatible (Winbond/NexFlash)"; 746 else 747 name = "ST compatible (Micron)"; 748 749 spiflash.type = QSPIFLASH_ST; 750 spiflash.blocksize = 64 * 1024; 751 752 switch ((unsigned short)(device_id & 0x00ff)) { 753 case 0x11: 754 /* ST M25P20 2 Mbit Serial Flash */ 755 spiflash.numblocks = 4; 756 break; 757 case 0x12: 758 /* ST M25P40 4 Mbit Serial Flash */ 759 spiflash.numblocks = 8; 760 break; 761 case 0x13: 762 spiflash.numblocks = 16; 763 break; 764 case 0x14: 765 /* ST M25P16 16 Mbit Serial Flash */ 766 spiflash.numblocks = 32; 767 break; 768 case 0x15: 769 /* ST M25P32 32 Mbit Serial Flash */ 770 spiflash.numblocks = 64; 771 break; 772 case 0x16: 773 /* ST M25P64 64 Mbit Serial Flash */ 774 spiflash.numblocks = 128; 775 break; 776 case 0x17: 777 case 0x18: 778 /* ST M25FL128 128 Mbit Serial Flash */ 779 spiflash.numblocks = 256; 780 break; 781 case 0x19: 782 spiflash.numblocks = 512; 783 break; 784 case 0x20: 785 spiflash.numblocks = 1024; 786 /* Special poll requirement for Micron N25Q512 */ 787 spiflash.poll = spiflash_poll; 788 break; 789 } 790 break; 791 792 case SSTPART: 793 name = "SST"; 794 spiflash.type = QSPIFLASH_ST; 795 spiflash.blocksize = 4 * 1024; 796 switch ((unsigned char)(device_id & 0x00ff)) { 797 case 1: 798 /* SST25WF512 512 Kbit Serial Flash */ 799 spiflash.numblocks = 16; 800 break; 801 case 0x48: 802 /* SST25VF512 512 Kbit Serial Flash */ 803 spiflash.numblocks = 16; 804 break; 805 case 2: 806 /* SST25WF010 1 Mbit Serial Flash */ 807 spiflash.numblocks = 32; 808 break; 809 case 0x49: 810 /* SST25VF010 1 Mbit Serial Flash */ 811 spiflash.numblocks = 32; 812 break; 813 case 3: 814 /* SST25WF020 2 Mbit Serial Flash */ 815 spiflash.numblocks = 64; 816 break; 817 case 0x43: 818 /* SST25VF020 2 Mbit Serial Flash */ 819 spiflash.numblocks = 64; 820 break; 821 case 4: 822 /* SST25WF040 4 Mbit Serial Flash */ 823 spiflash.numblocks = 128; 824 break; 825 case 0x44: 826 /* SST25VF040 4 Mbit Serial Flash */ 827 spiflash.numblocks = 128; 828 break; 829 case 0x8d: 830 /* SST25VF040B 4 Mbit Serial Flash */ 831 spiflash.numblocks = 128; 832 break; 833 case 5: 834 /* SST25WF080 8 Mbit Serial Flash */ 835 spiflash.numblocks = 256; 836 break; 837 case 0x8e: 838 /* SST25VF080B 8 Mbit Serial Flash */ 839 spiflash.numblocks = 256; 840 break; 841 case 0x41: 842 /* SST25VF016 16 Mbit Serial Flash */ 843 spiflash.numblocks = 512; 844 break; 845 case 0x4a: 846 /* SST25VF032 32 Mbit Serial Flash */ 847 spiflash.numblocks = 1024; 848 break; 849 case 0x4b: 850 /* SST25VF064 64 Mbit Serial Flash */ 851 spiflash.numblocks = 2048; 852 break; 853 } 854 break; 855 856 case ATMELPART: 857 /* SFLASH_AT_STATUS not implement */ 858 name = "Atmel"; 859 spiflash.type = QSPIFLASH_AT; 860 switch ((char)(device_id & 0x00ff)) { 861 case ID_AT25F512: 862 spiflash.numblocks = 2; 863 spiflash.blocksize = 32 * 1024; 864 break; 865 866 case ID_AT25F2048: 867 spiflash.numblocks = 4; 868 spiflash.blocksize = 64 * 1024; 869 break; 870 default: 871 break; 872 } 873 break; 874 875 default: 876 spiflash.numblocks = 0; 877 SPIFL_MSG(("Unknown flash, device_id:0x%02X\n", device_id)); 878 return NULL; 879 } 880 881 /* Open device here */ 882 spiflash_open(sih, qspi); 883 884 spiflash.size = spiflash.blocksize * spiflash.numblocks; 885 886 if (BCM4707_CHIP(CHIPID(sih->chip))) { 887 uint32 chip_rev, straps_ctrl; 888 uint32 *srab_base, *dmu_base; 889 /* Get chip revision */ 890 srab_base = (uint32 *)REG_MAP(CHIPCB_SRAB_BASE, SI_CORE_SIZE); 891 W_REG(osh, (uint32 *)((uint32)srab_base + CHIPCB_SRAB_CMDSTAT_OFFSET), 0x02400001); 892 chip_rev = R_REG(osh, 893 (uint32 *)((uint32)srab_base + CHIPCB_SRAB_RDL_OFFSET)) & 0xff; 894 REG_UNMAP(srab_base); 895 if (CHIPID(sih->chip) == BCM4707_CHIP_ID && chip_rev < 2) { 896 force_3byte_mode = 1; 897 } 898 /* Check 4BYTE_MODE strap */ 899 dmu_base = (uint32 *)REG_MAP(CHIPCB_DMU_BASE, SI_CORE_SIZE); 900 straps_ctrl = R_REG(osh, 901 (uint32 *)((uint32)dmu_base + CHIPCB_CRU_STRAPS_CTRL_OFFSET)); 902 REG_UNMAP(dmu_base); 903 if (!(straps_ctrl & CHIPCB_CRU_STRAPS_4BYTE)) 904 force_3byte_mode = 1; 905 } 906 /* NOR flash size check. */ 907 if (force_3byte_mode && (spiflash.size > SI_FLASH_WINDOW)) { 908 SPIFL_MSG(("NOR flash size %dMB is bigger than %dMB, limit it to %dMB\n", 909 (spiflash.size >> 20), (SI_FLASH_WINDOW >> 20), 910 (SI_FLASH_WINDOW >> 20))); 911 spiflash.size = SI_FLASH_WINDOW; 912 } else if (spiflash.size > SI_NS_FLASH_WINDOW) { 913 SPIFL_MSG(("NOR flash size %dMB is bigger than %dMB, limit it to %dMB\n", 914 (spiflash.size >> 20), (SI_NS_FLASH_WINDOW >> 20), 915 (SI_NS_FLASH_WINDOW >> 20))); 916 spiflash.size = SI_NS_FLASH_WINDOW; 917 } 918 919 spiflash.phybase = SI_NS_NORFLASH; 920 if (spiflash.size) 921 spiflash.base = (uint32)REG_MAP(SI_NS_NORFLASH, spiflash.size); 922 923 if (firsttime) { 924 if (spiflash.size == 0) 925 printf("ERROR: Unknown flash, device_id:0x%02X\n", device_id); 926 else { 927 /* Enter 4-byte mode if size > 16MB */ 928 if (spiflash.size > 0x1000000) { 929 spiflash_set_4byte_mode(&spiflash, 1); 930 } else { 931 spiflash_set_4byte_mode(&spiflash, 0); 932 } 933 printf("Found a %s serial flash with %d %dKB blocks; total size %dMB\n", 934 name, spiflash.numblocks, spiflash.blocksize / 1024, 935 spiflash.size / (1024 * 1024)); 936 } 937 } 938 939 firsttime = FALSE; 940 return spiflash.size ? &spiflash : NULL; 941} 942 943static int 944spiflash_open(si_t *sih, qspiregs_t *qspi) 945{ 946 osl_t *osh = NULL; 947 unsigned int lval; 948 949 ASSERT(sih); 950 951 osh = si_osh(sih); 952 953 lval = SPI_SYSTEM_CLK / (2 * MAX_SPI_BAUD); 954 W_REG(osh, &qspi->mspi_spcr0_lsb, lval); 955 lval = R_REG(osh, &qspi->mspi_spcr0_msb); 956 lval &= ~(MSPI_SPCR0_MSB_CPOL_MASK | MSPI_SPCR0_MSB_CPHA_MASK | MSPI_SPCR0_MSB_BitS_MASK); 957 lval |= (MSPI_SPCR0_MSB_MSTR_MASK | (MSPI_SPCR0_MSB_CPOL_MASK | MSPI_SPCR0_MSB_CPHA_MASK | 958 (0x8 << MSPI_SPCR0_MSB_BitS_SHIFT))); 959 W_REG(osh, &qspi->mspi_spcr0_msb, lval); 960 961 /* add delay if it is 7422A0 */ 962 W_REG(osh, &qspi->mspi_spcr1_msb, 128); 963 964 return 0; 965} 966 967/* Read len bytes starting at offset into buf. Returns number of bytes read. */ 968static int 969spiflash_read(hndsflash_t *spifl, uint offset, uint len, const uchar *buf) 970{ 971 si_t *sih = spifl->sih; 972 qspiregs_t *qspi = (qspiregs_t *)spifl->core; 973 osl_t *osh; 974 uint8 *from, *to; 975 int cnt, i; 976 977 ASSERT(sih); 978 979 osh = si_osh(sih); 980 981 if (!len) 982 return 0; 983 984 if ((offset + len) > spifl->size) 985 return -22; 986 987 if ((len >= 4) && (offset & 3)) 988 cnt = 4 - (offset & 3); 989 else if ((len >= 4) && ((uintptr)buf & 3)) 990 cnt = 4 - ((uintptr)buf & 3); 991 else 992 cnt = len; 993 994 from = (uint8 *)((void *)spifl->base + offset); 995 to = (uint8 *)buf; 996 997 mspi_enable_bspi(osh, qspi); 998 if (cnt < 4) { 999 for (i = 0; i < cnt; i ++) { 1000 /* Cannot use R_REG because in bigendian that will 1001 * xor the address and we don't want that here. 1002 */ 1003 *to = *from; 1004 from ++; 1005 to ++; 1006 } 1007 return cnt; 1008 } 1009 1010 while (cnt >= 4) { 1011 *(uint32 *)to = *(uint32 *)from; 1012 from += 4; 1013 to += 4; 1014 cnt -= 4; 1015 } 1016 1017 return (len - cnt); 1018} 1019 1020/* Write len bytes starting at offset into buf. Returns number of bytes 1021 * written 1022 */ 1023static int 1024spiflash_write(hndsflash_t *spifl, uint offset, uint length, const uchar *buffer) 1025{ 1026 si_t *sih = spifl->sih; 1027 qspiregs_t *qspi = (qspiregs_t *)spifl->core; 1028 const uint8 *buf = buffer; 1029 int ret = 0; 1030 osl_t *osh; 1031 unsigned i, j, number_byte_to_write; 1032 uchar temp[FLASH_SPI_MAX_PAGE_SIZE+28]; 1033 1034 ASSERT(sih); 1035 1036 osh = si_osh(sih); 1037 1038 if (!length) 1039 return 0; 1040 1041 if ((offset + length) > spifl->size) 1042 return -22; 1043 1044 mspi_disable_bspi(osh, qspi); 1045 1046 switch (spifl->type) { 1047 case QSPIFLASH_ST: 1048 for (i = 0; i < length; i += number_byte_to_write) { 1049 if (i + FLASH_SPI_MAX_PAGE_SIZE >= length) 1050 number_byte_to_write = length - i; 1051 else 1052 number_byte_to_write = FLASH_SPI_MAX_PAGE_SIZE; 1053 1054 /* to prevent address cross the page boundary of 256 bytes. */ 1055 if (number_byte_to_write > (256 - (i&0xFF))) 1056 number_byte_to_write = 256 - (i&0xFF); 1057 1058 for (j = 0; j < number_byte_to_write; j++) { 1059 temp[j] = *buf; 1060 buf += 1; 1061 } 1062 if (!bspi2_st_page_program(spifl, qspi, offset + i, &temp[0], 1063 number_byte_to_write)) { 1064 SPIFL_MSG(("Program fail\n")); 1065 ret = -11; 1066 break; 1067 } 1068 1069 if (spifl->poll && !bspi_poll(spifl, qspi, offset + i)) { 1070 SPIFL_MSG(("Poll fail\n")); 1071 ret = -33; 1072 break; 1073 } 1074 1075 ret += number_byte_to_write; 1076 } 1077 break; 1078 1079 case QSPIFLASH_AT: 1080 for (i = 0; i < length; i += number_byte_to_write) { 1081 if (i + FLASH_SPI_MAX_PAGE_SIZE >= length) 1082 number_byte_to_write = length - i; 1083 else 1084 number_byte_to_write = FLASH_SPI_MAX_PAGE_SIZE; 1085 1086 /* to prevent address cross the page boundary of 256 bytes. */ 1087 if (number_byte_to_write > (256 - (i&0xFF))) 1088 number_byte_to_write = 256 - (i&0xFF); 1089 1090 for (j = 0; j < number_byte_to_write; j++) { 1091 temp[j] = *buf; 1092 buf += 1; 1093 } 1094 if (!bspi2_at_page_program(osh, qspi, spifl, offset + i, &temp[0], 1095 number_byte_to_write)) { 1096 SPIFL_MSG(("Program fail\n")); 1097 ret = -11; 1098 break; 1099 } 1100 ret += number_byte_to_write; 1101 } 1102 break; 1103 } 1104 1105 mspi_enable_bspi(osh, qspi); 1106 return ret; 1107} 1108 1109/* Erase a region. Returns number of bytes scheduled for erasure. 1110 * Caller should poll for completion. 1111 */ 1112static int 1113spiflash_erase(hndsflash_t *spifl, uint offset) 1114{ 1115 si_t *sih = spifl->sih; 1116 qspiregs_t *qspi = (qspiregs_t *)spifl->core; 1117 int erase_size = 0; 1118 osl_t *osh = NULL; 1119 1120 ASSERT(sih); 1121 1122 osh = si_osh(sih); 1123 1124 if (offset >= spifl->size) 1125 return -22; 1126 1127 mspi_disable_bspi(osh, qspi); 1128 1129 if (bspi_sector_erase(spifl, qspi, offset)) 1130 erase_size = spifl->blocksize; 1131 1132 mspi_enable_bspi(osh, qspi); 1133 1134 return erase_size; 1135} 1136 1137/* 1138 * Poll function called after write/erase operations. Returns 0 when poll 1139 * completes. 1140 */ 1141static int 1142spiflash_poll(hndsflash_t *spifl, uint offset) 1143{ 1144 int result = 0; 1145 si_t *sih = spifl->sih; 1146 qspiregs_t *qspi = (qspiregs_t *)spifl->core; 1147 osl_t *osh = NULL; 1148 1149 ASSERT(sih); 1150 1151 osh = si_osh(sih); 1152 1153 if (offset >= spifl->size) 1154 return -22; 1155 1156 mspi_disable_bspi(osh, qspi); 1157 1158 switch (spifl->type) { 1159 case QSPIFLASH_ST: 1160 /* Larger part such as the Micron 25Q512A (64MB) requires the flash status register 1161 * (FSR) polled after write/erase. 1162 */ 1163 if (!bspi_poll(spifl, qspi, offset)) { 1164 result = 1; /* Poll failed */ 1165 } 1166 break; 1167 1168 default: 1169 /* Nothing to do */ 1170 break; 1171 } 1172 1173 mspi_enable_bspi(osh, qspi); 1174 1175 return result; 1176} 1177 1178/* 1179 * writes the appropriate range of flash, a NULL buf simply erases 1180 * the region of flash 1181 */ 1182static int 1183spiflash_commit(hndsflash_t *spifl, uint offset, uint len, const uchar *buf) 1184{ 1185 si_t *sih = spifl->sih; 1186 uchar *block = NULL, *cur_ptr, *blk_ptr; 1187 uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder; 1188 uint blk_offset, blk_len, copied; 1189 int bytes, ret = 0; 1190 osl_t *osh; 1191 1192 ASSERT(sih); 1193 1194 osh = si_osh(sih); 1195 1196 /* Check address range */ 1197 if (len <= 0) 1198 return 0; 1199 1200 if ((offset + len) > spifl->size) 1201 return -1; 1202 1203 blocksize = spifl->blocksize; 1204 mask = blocksize - 1; 1205 1206 /* Allocate a block of mem */ 1207 if (!(block = MALLOC(osh, blocksize))) 1208 return -1; 1209 1210 while (len) { 1211 /* Align offset */ 1212 cur_offset = offset & ~mask; 1213 cur_length = blocksize; 1214 cur_ptr = block; 1215 1216 remainder = blocksize - (offset & mask); 1217 if (len < remainder) 1218 cur_retlen = len; 1219 else 1220 cur_retlen = remainder; 1221 1222 /* buf == NULL means erase only */ 1223 if (buf) { 1224 /* Copy existing data into holding block if necessary */ 1225 if ((offset & mask) || (len < blocksize)) { 1226 blk_offset = cur_offset; 1227 blk_len = cur_length; 1228 blk_ptr = cur_ptr; 1229 1230 /* Copy entire block */ 1231 while (blk_len) { 1232 copied = spiflash_read(spifl, blk_offset, blk_len, 1233 blk_ptr); 1234 blk_offset += copied; 1235 blk_len -= copied; 1236 blk_ptr += copied; 1237 } 1238 } 1239 1240 /* Copy input data into holding block */ 1241 memcpy(cur_ptr + (offset & mask), buf, cur_retlen); 1242 } 1243 1244 /* Erase block */ 1245 if ((ret = spiflash_erase(spifl, (uint)cur_offset)) < 0) 1246 goto done; 1247 1248 /* buf == NULL means erase only */ 1249 if (!buf) { 1250 offset += cur_retlen; 1251 len -= cur_retlen; 1252 continue; 1253 } 1254 1255 /* Write holding block */ 1256 while (cur_length > 0) { 1257 if ((bytes = spiflash_write(spifl, 1258 (uint)cur_offset, 1259 (uint)cur_length, 1260 (uchar *)cur_ptr)) < 0) { 1261 ret = bytes; 1262 goto done; 1263 } 1264 cur_offset += bytes; 1265 cur_length -= bytes; 1266 cur_ptr += bytes; 1267 } 1268 1269 offset += cur_retlen; 1270 len -= cur_retlen; 1271 buf += cur_retlen; 1272 } 1273 1274 ret = len; 1275done: 1276 if (block) 1277 MFREE(osh, block, blocksize); 1278 return ret; 1279} 1280