Lines Matching refs:sih
42 extern void si_mem_setclock(si_t *sih, uint32 ddrclock);
791 ddr_regs_init(si_t *sih, ddrcregs_t *ddr, unsigned int ddr_table[])
797 osh = si_osh(sih);
804 int rewrite_mode_registers(void *sih)
812 osh = si_osh((si_t *)sih);
813 ddr = (ddrcregs_t *)si_setcore((si_t *)sih, NS_DDR23_CORE_ID, 0);
990 Program_Digital_Core_Power_Voltage(si_t *sih)
1011 osh = si_osh(sih);
1012 chipcb = (chipcommonbregs_t *)si_setcore(sih, NS_CCB_CORE_ID, 0);
1019 if (CHIPID(sih->chip) == BCM4707_CHIP_ID || CHIPID(sih->chip) == BCM47094_CHIP_ID) {
1020 if (sih->chippkg != BCM4709_PKG_ID) {
1103 si_t *sih;
1122 sih = (si_t *)osl_init();
1123 osh = si_osh(sih);
1125 Program_Digital_Core_Power_Voltage(sih);
1127 regs = (void *)si_setcore(sih, NS_DDR23_CORE_ID, 0);
1129 ddrtype_ddr3 = ((si_core_sflags(sih, 0, 0) & DDR_TYPE_MASK) == DDR_STAT_DDR3);
1132 chipcb = (chipcommonbregs_t *)si_setcore(sih, NS_CCB_CORE_ID, 0);
1153 ddr = (ddrcregs_t *)si_setcore(sih, NS_DDR23_CORE_ID, 0);
1168 si_mem_setclock(sih, ddrclock);
1173 si_mem_setclock(sih, ddrclock);
1177 bootdev = soc_boot_dev((void *)sih);
1227 si_watchdog(sih, 1);
1314 si_watchdog(sih, 1);
1320 ddr_regs_init(sih, ddr, ddr3_init_tab_1600);
1322 ddr_regs_init(sih, ddr, ddr2_init_tab_400);
1434 status = do_shmoo((void *)sih, DDR_PHY_CONTROL_REGS_REVISION, 0,
1438 hnd_cpu_reset(sih);