Searched refs:pll (Results 101 - 120 of 120) sorted by relevance

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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-davinci/
H A Dda850.c971 struct pll_data *pll = clk->pll_data; local
979 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/media/dvb/dvb-usb/
H A Ddib0700_devices.c1104 .pll = &dib807x_bw_config_12_mhz,
1121 .pll = &dib807x_bw_config_12_mhz,
1413 .pll = &dib8090_pll_config_12mhz,
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/telephony/
H A Dixj.h449 unsigned int pll:1; /* 1 = div 10, 0 = div 5 */ member in struct:__anon16118
H A Dixj.c1853 j->sic2.bits.pll = 0; /* 1 = div 10, 0 = div 5 */
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/gpu/drm/radeon/
H A Dradeon_mode.h137 /* pll flags */
153 /* pll algo */
167 /* pll in/out limits */
189 /* pll id */
191 /* pll algo */
494 extern void radeon_compute_pll(struct radeon_pll *pll,
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-omap2/
H A Dsram242x.S165 str r3, [r4] @ set new state (pll/x, x=1 or 2)
233 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
H A Dsram243x.S165 str r3, [r4] @ set new state (pll/x, x=1 or 2)
233 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c64xx/
H A Dclock.c28 #include <mach/pll.h>
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s5p6440/
H A Dclock.c32 #include <plat/pll.h>
/netgear-R7000-V1.0.7.12_1.2.5/src/shared/
H A Dhndpmu.c341 static const char BCMATTACHDATA(rstr_pllD)[] = "pll%d";
3121 /* setup pll and query clock speed */
3292 PMU_MSG(("Done pll\n"));
3339 /* setup pll and query clock speed */
3913 /** returns chip specific default pll fvco frequency in [khz] units */
4270 /* Now toggle pllctlupdate so the pll sees the new values */
4417 /* Bootloader need to change pll if it is not default 37.4M */
4972 /* Flush deferred pll control registers writes */
5060 /* Flush deferred pll control registers writes */
5190 /* Flush ('update') the deferred pll contro
6371 uint pll; local
6447 uint pll; local
[all...]
H A Dboot.S107 # correct pll clk freq to real speed in the 5350 case.
H A Dsiutils.c3659 /** turn primary xtal and/or pll off/on */
3710 /* turn pll on */
3795 case CLK_FAST: /* FORCEHT, fast (pll) clock */
7354 uint32 rev, cap, pll, div, baud_base = 0x00; local
7358 pll = cap & CC_CAP_PLL_MASK;
7360 if (CCPLL_ENAB(sih) && pll == PLL_TYPE1) {
7362 baud_base = si_clock_rate(pll, R_REG(osh, &cc->clockcontrol_n),
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/nvidia/
H A Dnvidia.c443 state->vpll = state->pll;
444 state->vpll2 = state->pll;
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/aty/
H A Dradeon_monitor.c662 rinfo->panel_info.ref_divider = rinfo->pll.ref_div;
H A Dradeon_pm.c1644 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
1907 /* Set LVDS registers but keep interface & pll down */
2187 OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s5pc100/
H A Dclock.c27 #include <plat/pll.h>
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s5pv210/
H A Dclock.c29 #include <plat/pll.h>
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/gpu/drm/nouveau/
H A Dnouveau_bios.c644 struct nouveau_pll_vals pll; local
652 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
656 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
657 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
3980 /* don't let script change pll->head binding */
4665 /* don't let script change pll->head binding */
4717 * pll) and load the hard coded limits instead.
4799 else /* limit match is a pll type */
4857 /* pll decodin
[all...]
H A Dnouveau_drv.h480 uint32_t pll; member in struct:nv04_mode_state
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/wireless/ath/ath9k/
H A Dhw.c689 u32 pll = ath9k_hw_compute_pll_control(ah, chan); local
691 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);

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