1/* 2 * Copyright (c) 2008-2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include <linux/io.h> 18#include <linux/slab.h> 19#include <asm/unaligned.h> 20 21#include "hw.h" 22#include "hw-ops.h" 23#include "rc.h" 24#include "ar9003_mac.h" 25 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 27 28MODULE_AUTHOR("Atheros Communications"); 29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); 31MODULE_LICENSE("Dual BSD/GPL"); 32 33static int __init ath9k_init(void) 34{ 35 return 0; 36} 37module_init(ath9k_init); 38 39static void __exit ath9k_exit(void) 40{ 41 return; 42} 43module_exit(ath9k_exit); 44 45/* Private hardware callbacks */ 46 47static void ath9k_hw_init_cal_settings(struct ath_hw *ah) 48{ 49 ath9k_hw_private_ops(ah)->init_cal_settings(ah); 50} 51 52static void ath9k_hw_init_mode_regs(struct ath_hw *ah) 53{ 54 ath9k_hw_private_ops(ah)->init_mode_regs(ah); 55} 56 57static bool ath9k_hw_macversion_supported(struct ath_hw *ah) 58{ 59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 60 61 return priv_ops->macversion_supported(ah->hw_version.macVersion); 62} 63 64static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, 65 struct ath9k_channel *chan) 66{ 67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); 68} 69 70static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) 71{ 72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) 73 return; 74 75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); 76} 77 78static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) 79{ 80 /* You will not have this callback if using the old ANI */ 81 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) 82 return; 83 84 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); 85} 86 87/********************/ 88/* Helper Functions */ 89/********************/ 90 91static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) 92{ 93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 94 95 if (!ah->curchan) /* should really check for CCK instead */ 96 return usecs *ATH9K_CLOCK_RATE_CCK; 97 if (conf->channel->band == IEEE80211_BAND_2GHZ) 98 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; 99 100 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) 101 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; 102 else 103 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM; 104} 105 106static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) 107{ 108 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 109 110 if (conf_is_ht40(conf)) 111 return ath9k_hw_mac_clks(ah, usecs) * 2; 112 else 113 return ath9k_hw_mac_clks(ah, usecs); 114} 115 116bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) 117{ 118 int i; 119 120 BUG_ON(timeout < AH_TIME_QUANTUM); 121 122 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { 123 if ((REG_READ(ah, reg) & mask) == val) 124 return true; 125 126 udelay(AH_TIME_QUANTUM); 127 } 128 129 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, 130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 131 timeout, reg, REG_READ(ah, reg), mask, val); 132 133 return false; 134} 135EXPORT_SYMBOL(ath9k_hw_wait); 136 137u32 ath9k_hw_reverse_bits(u32 val, u32 n) 138{ 139 u32 retval; 140 int i; 141 142 for (i = 0, retval = 0; i < n; i++) { 143 retval = (retval << 1) | (val & 1); 144 val >>= 1; 145 } 146 return retval; 147} 148 149bool ath9k_get_channel_edges(struct ath_hw *ah, 150 u16 flags, u16 *low, 151 u16 *high) 152{ 153 struct ath9k_hw_capabilities *pCap = &ah->caps; 154 155 if (flags & CHANNEL_5GHZ) { 156 *low = pCap->low_5ghz_chan; 157 *high = pCap->high_5ghz_chan; 158 return true; 159 } 160 if ((flags & CHANNEL_2GHZ)) { 161 *low = pCap->low_2ghz_chan; 162 *high = pCap->high_2ghz_chan; 163 return true; 164 } 165 return false; 166} 167 168u16 ath9k_hw_computetxtime(struct ath_hw *ah, 169 u8 phy, int kbps, 170 u32 frameLen, u16 rateix, 171 bool shortPreamble) 172{ 173 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; 174 175 if (kbps == 0) 176 return 0; 177 178 switch (phy) { 179 case WLAN_RC_PHY_CCK: 180 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; 181 if (shortPreamble) 182 phyTime >>= 1; 183 numBits = frameLen << 3; 184 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); 185 break; 186 case WLAN_RC_PHY_OFDM: 187 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { 188 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; 189 numBits = OFDM_PLCP_BITS + (frameLen << 3); 190 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 191 txTime = OFDM_SIFS_TIME_QUARTER 192 + OFDM_PREAMBLE_TIME_QUARTER 193 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); 194 } else if (ah->curchan && 195 IS_CHAN_HALF_RATE(ah->curchan)) { 196 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; 197 numBits = OFDM_PLCP_BITS + (frameLen << 3); 198 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 199 txTime = OFDM_SIFS_TIME_HALF + 200 OFDM_PREAMBLE_TIME_HALF 201 + (numSymbols * OFDM_SYMBOL_TIME_HALF); 202 } else { 203 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; 204 numBits = OFDM_PLCP_BITS + (frameLen << 3); 205 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); 206 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME 207 + (numSymbols * OFDM_SYMBOL_TIME); 208 } 209 break; 210 default: 211 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 212 "Unknown phy %u (rate ix %u)\n", phy, rateix); 213 txTime = 0; 214 break; 215 } 216 217 return txTime; 218} 219EXPORT_SYMBOL(ath9k_hw_computetxtime); 220 221void ath9k_hw_get_channel_centers(struct ath_hw *ah, 222 struct ath9k_channel *chan, 223 struct chan_centers *centers) 224{ 225 int8_t extoff; 226 227 if (!IS_CHAN_HT40(chan)) { 228 centers->ctl_center = centers->ext_center = 229 centers->synth_center = chan->channel; 230 return; 231 } 232 233 if ((chan->chanmode == CHANNEL_A_HT40PLUS) || 234 (chan->chanmode == CHANNEL_G_HT40PLUS)) { 235 centers->synth_center = 236 chan->channel + HT40_CHANNEL_CENTER_SHIFT; 237 extoff = 1; 238 } else { 239 centers->synth_center = 240 chan->channel - HT40_CHANNEL_CENTER_SHIFT; 241 extoff = -1; 242 } 243 244 centers->ctl_center = 245 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); 246 /* 25 MHz spacing is supported by hw but not on upper layers */ 247 centers->ext_center = 248 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); 249} 250 251/******************/ 252/* Chip Revisions */ 253/******************/ 254 255static void ath9k_hw_read_revisions(struct ath_hw *ah) 256{ 257 u32 val; 258 259 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; 260 261 if (val == 0xFF) { 262 val = REG_READ(ah, AR_SREV); 263 ah->hw_version.macVersion = 264 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 265 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); 266 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; 267 } else { 268 if (!AR_SREV_9100(ah)) 269 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); 270 271 ah->hw_version.macRev = val & AR_SREV_REVISION; 272 273 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) 274 ah->is_pciexpress = true; 275 } 276} 277 278/************************************/ 279/* HW Attach, Detach, Init Routines */ 280/************************************/ 281 282static void ath9k_hw_disablepcie(struct ath_hw *ah) 283{ 284 if (AR_SREV_9100(ah)) 285 return; 286 287 ENABLE_REGWRITE_BUFFER(ah); 288 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 292 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 293 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 294 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 295 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 296 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 298 299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 300 301 REGWRITE_BUFFER_FLUSH(ah); 302 DISABLE_REGWRITE_BUFFER(ah); 303} 304 305/* This should work for all families including legacy */ 306static bool ath9k_hw_chip_test(struct ath_hw *ah) 307{ 308 struct ath_common *common = ath9k_hw_common(ah); 309 u32 regAddr[2] = { AR_STA_ID0 }; 310 u32 regHold[2]; 311 u32 patternData[4] = { 0x55555555, 312 0xaaaaaaaa, 313 0x66666666, 314 0x99999999 }; 315 int i, j, loop_max; 316 317 if (!AR_SREV_9300_20_OR_LATER(ah)) { 318 loop_max = 2; 319 regAddr[1] = AR_PHY_BASE + (8 << 2); 320 } else 321 loop_max = 1; 322 323 for (i = 0; i < loop_max; i++) { 324 u32 addr = regAddr[i]; 325 u32 wrData, rdData; 326 327 regHold[i] = REG_READ(ah, addr); 328 for (j = 0; j < 0x100; j++) { 329 wrData = (j << 16) | j; 330 REG_WRITE(ah, addr, wrData); 331 rdData = REG_READ(ah, addr); 332 if (rdData != wrData) { 333 ath_print(common, ATH_DBG_FATAL, 334 "address test failed " 335 "addr: 0x%08x - wr:0x%08x != " 336 "rd:0x%08x\n", 337 addr, wrData, rdData); 338 return false; 339 } 340 } 341 for (j = 0; j < 4; j++) { 342 wrData = patternData[j]; 343 REG_WRITE(ah, addr, wrData); 344 rdData = REG_READ(ah, addr); 345 if (wrData != rdData) { 346 ath_print(common, ATH_DBG_FATAL, 347 "address test failed " 348 "addr: 0x%08x - wr:0x%08x != " 349 "rd:0x%08x\n", 350 addr, wrData, rdData); 351 return false; 352 } 353 } 354 REG_WRITE(ah, regAddr[i], regHold[i]); 355 } 356 udelay(100); 357 358 return true; 359} 360 361static void ath9k_hw_init_config(struct ath_hw *ah) 362{ 363 int i; 364 365 ah->config.dma_beacon_response_time = 2; 366 ah->config.sw_beacon_response_time = 10; 367 ah->config.additional_swba_backoff = 0; 368 ah->config.ack_6mb = 0x0; 369 ah->config.cwm_ignore_extcca = 0; 370 ah->config.pcie_powersave_enable = 0; 371 ah->config.pcie_clock_req = 0; 372 ah->config.pcie_waen = 0; 373 ah->config.analog_shiftreg = 1; 374 ah->config.ofdm_trig_low = 200; 375 ah->config.ofdm_trig_high = 500; 376 ah->config.cck_trig_high = 200; 377 ah->config.cck_trig_low = 100; 378 ah->config.enable_ani = true; 379 380 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { 381 ah->config.spurchans[i][0] = AR_NO_SPUR; 382 ah->config.spurchans[i][1] = AR_NO_SPUR; 383 } 384 385 if (ah->hw_version.devid != AR2427_DEVID_PCIE) 386 ah->config.ht_enable = 1; 387 else 388 ah->config.ht_enable = 0; 389 390 /* PAPRD needs some more work to be enabled */ 391 ah->config.paprd_disable = 1; 392 393 ah->config.rx_intr_mitigation = true; 394 ah->config.pcieSerDesWrite = true; 395 396 /* 397 * We need this for PCI devices only (Cardbus, PCI, miniPCI) 398 * _and_ if on non-uniprocessor systems (Multiprocessor/HT). 399 * This means we use it for all AR5416 devices, and the few 400 * minor PCI AR9280 devices out there. 401 * 402 * Serialization is required because these devices do not handle 403 * well the case of two concurrent reads/writes due to the latency 404 * involved. During one read/write another read/write can be issued 405 * on another CPU while the previous read/write may still be working 406 * on our hardware, if we hit this case the hardware poops in a loop. 407 * We prevent this by serializing reads and writes. 408 * 409 * This issue is not present on PCI-Express devices or pre-AR5416 410 * devices (legacy, 802.11abg). 411 */ 412 if (num_possible_cpus() > 1) 413 ah->config.serialize_regmode = SER_REG_MODE_AUTO; 414} 415 416static void ath9k_hw_init_defaults(struct ath_hw *ah) 417{ 418 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 419 420 regulatory->country_code = CTRY_DEFAULT; 421 regulatory->power_limit = MAX_RATE_POWER; 422 regulatory->tp_scale = ATH9K_TP_SCALE_MAX; 423 424 ah->hw_version.magic = AR5416_MAGIC; 425 ah->hw_version.subvendorid = 0; 426 427 ah->ah_flags = 0; 428 if (!AR_SREV_9100(ah)) 429 ah->ah_flags = AH_USE_EEPROM; 430 431 ah->atim_window = 0; 432 ah->sta_id1_defaults = 433 AR_STA_ID1_CRPT_MIC_ENABLE | 434 AR_STA_ID1_MCAST_KSRCH; 435 ah->beacon_interval = 100; 436 ah->enable_32kHz_clock = DONT_USE_32KHZ; 437 ah->slottime = (u32) -1; 438 ah->globaltxtimeout = (u32) -1; 439 ah->power_mode = ATH9K_PM_UNDEFINED; 440} 441 442static int ath9k_hw_init_macaddr(struct ath_hw *ah) 443{ 444 struct ath_common *common = ath9k_hw_common(ah); 445 u32 sum; 446 int i; 447 u16 eeval; 448 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; 449 450 sum = 0; 451 for (i = 0; i < 3; i++) { 452 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); 453 sum += eeval; 454 common->macaddr[2 * i] = eeval >> 8; 455 common->macaddr[2 * i + 1] = eeval & 0xff; 456 } 457 if (sum == 0 || sum == 0xffff * 3) 458 return -EADDRNOTAVAIL; 459 460 return 0; 461} 462 463static int ath9k_hw_post_init(struct ath_hw *ah) 464{ 465 int ecode; 466 467 if (!AR_SREV_9271(ah)) { 468 if (!ath9k_hw_chip_test(ah)) 469 return -ENODEV; 470 } 471 472 if (!AR_SREV_9300_20_OR_LATER(ah)) { 473 ecode = ar9002_hw_rf_claim(ah); 474 if (ecode != 0) 475 return ecode; 476 } 477 478 ecode = ath9k_hw_eeprom_init(ah); 479 if (ecode != 0) 480 return ecode; 481 482 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, 483 "Eeprom VER: %d, REV: %d\n", 484 ah->eep_ops->get_eeprom_ver(ah), 485 ah->eep_ops->get_eeprom_rev(ah)); 486 487 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 488 if (ecode) { 489 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 490 "Failed allocating banks for " 491 "external radio\n"); 492 ath9k_hw_rf_free_ext_banks(ah); 493 return ecode; 494 } 495 496 if (!AR_SREV_9100(ah)) { 497 ath9k_hw_ani_setup(ah); 498 ath9k_hw_ani_init(ah); 499 } 500 501 return 0; 502} 503 504static void ath9k_hw_attach_ops(struct ath_hw *ah) 505{ 506 if (AR_SREV_9300_20_OR_LATER(ah)) 507 ar9003_hw_attach_ops(ah); 508 else 509 ar9002_hw_attach_ops(ah); 510} 511 512/* Called for all hardware families */ 513static int __ath9k_hw_init(struct ath_hw *ah) 514{ 515 struct ath_common *common = ath9k_hw_common(ah); 516 int r = 0; 517 518 if (ah->hw_version.devid == AR5416_AR9100_DEVID) 519 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 520 521 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 522 ath_print(common, ATH_DBG_FATAL, 523 "Couldn't reset chip\n"); 524 return -EIO; 525 } 526 527 ath9k_hw_init_defaults(ah); 528 ath9k_hw_init_config(ah); 529 530 ath9k_hw_attach_ops(ah); 531 532 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 533 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 534 return -EIO; 535 } 536 537 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { 538 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || 539 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && 540 !ah->is_pciexpress)) { 541 ah->config.serialize_regmode = 542 SER_REG_MODE_ON; 543 } else { 544 ah->config.serialize_regmode = 545 SER_REG_MODE_OFF; 546 } 547 } 548 549 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", 550 ah->config.serialize_regmode); 551 552 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 553 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; 554 else 555 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; 556 557 if (!ath9k_hw_macversion_supported(ah)) { 558 ath_print(common, ATH_DBG_FATAL, 559 "Mac Chip Rev 0x%02x.%x is not supported by " 560 "this driver\n", ah->hw_version.macVersion, 561 ah->hw_version.macRev); 562 return -EOPNOTSUPP; 563 } 564 565 if (AR_SREV_9271(ah) || AR_SREV_9100(ah)) 566 ah->is_pciexpress = false; 567 568 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 569 ath9k_hw_init_cal_settings(ah); 570 571 ah->ani_function = ATH9K_ANI_ALL; 572 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 573 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 574 if (!AR_SREV_9300_20_OR_LATER(ah)) 575 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; 576 577 ath9k_hw_init_mode_regs(ah); 578 579 /* 580 * Read back AR_WA into a permanent copy and set bits 14 and 17. 581 * We need to do this to avoid RMW of this register. We cannot 582 * read the reg when chip is asleep. 583 */ 584 ah->WARegVal = REG_READ(ah, AR_WA); 585 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | 586 AR_WA_ASPM_TIMER_BASED_DISABLE); 587 588 if (ah->is_pciexpress) 589 ath9k_hw_configpcipowersave(ah, 0, 0); 590 else 591 ath9k_hw_disablepcie(ah); 592 593 if (!AR_SREV_9300_20_OR_LATER(ah)) 594 ar9002_hw_cck_chan14_spread(ah); 595 596 r = ath9k_hw_post_init(ah); 597 if (r) 598 return r; 599 600 ath9k_hw_init_mode_gain_regs(ah); 601 r = ath9k_hw_fill_cap_info(ah); 602 if (r) 603 return r; 604 605 r = ath9k_hw_init_macaddr(ah); 606 if (r) { 607 ath_print(common, ATH_DBG_FATAL, 608 "Failed to initialize MAC address\n"); 609 return r; 610 } 611 612 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 613 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); 614 else 615 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 616 617 ah->bb_watchdog_timeout_ms = 25; 618 619 common->state = ATH_HW_INITIALIZED; 620 621 return 0; 622} 623 624int ath9k_hw_init(struct ath_hw *ah) 625{ 626 int ret; 627 struct ath_common *common = ath9k_hw_common(ah); 628 629 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ 630 switch (ah->hw_version.devid) { 631 case AR5416_DEVID_PCI: 632 case AR5416_DEVID_PCIE: 633 case AR5416_AR9100_DEVID: 634 case AR9160_DEVID_PCI: 635 case AR9280_DEVID_PCI: 636 case AR9280_DEVID_PCIE: 637 case AR9285_DEVID_PCIE: 638 case AR9287_DEVID_PCI: 639 case AR9287_DEVID_PCIE: 640 case AR2427_DEVID_PCIE: 641 case AR9300_DEVID_PCIE: 642 break; 643 default: 644 if (common->bus_ops->ath_bus_type == ATH_USB) 645 break; 646 ath_print(common, ATH_DBG_FATAL, 647 "Hardware device ID 0x%04x not supported\n", 648 ah->hw_version.devid); 649 return -EOPNOTSUPP; 650 } 651 652 ret = __ath9k_hw_init(ah); 653 if (ret) { 654 ath_print(common, ATH_DBG_FATAL, 655 "Unable to initialize hardware; " 656 "initialization status: %d\n", ret); 657 return ret; 658 } 659 660 return 0; 661} 662EXPORT_SYMBOL(ath9k_hw_init); 663 664static void ath9k_hw_init_qos(struct ath_hw *ah) 665{ 666 ENABLE_REGWRITE_BUFFER(ah); 667 668 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 669 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); 670 671 REG_WRITE(ah, AR_QOS_NO_ACK, 672 SM(2, AR_QOS_NO_ACK_TWO_BIT) | 673 SM(5, AR_QOS_NO_ACK_BIT_OFF) | 674 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); 675 676 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 677 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 678 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 679 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 680 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 681 682 REGWRITE_BUFFER_FLUSH(ah); 683 DISABLE_REGWRITE_BUFFER(ah); 684} 685 686static void ath9k_hw_init_pll(struct ath_hw *ah, 687 struct ath9k_channel *chan) 688{ 689 u32 pll = ath9k_hw_compute_pll_control(ah, chan); 690 691 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 692 693 /* Switch the core clock for ar9271 to 117Mhz */ 694 if (AR_SREV_9271(ah)) { 695 udelay(500); 696 REG_WRITE(ah, 0x50040, 0x304); 697 } 698 699 udelay(RTC_PLL_SETTLE_DELAY); 700 701 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 702} 703 704static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 705 enum nl80211_iftype opmode) 706{ 707 u32 imr_reg = AR_IMR_TXERR | 708 AR_IMR_TXURN | 709 AR_IMR_RXERR | 710 AR_IMR_RXORN | 711 AR_IMR_BCNMISC; 712 713 if (AR_SREV_9300_20_OR_LATER(ah)) { 714 imr_reg |= AR_IMR_RXOK_HP; 715 if (ah->config.rx_intr_mitigation) 716 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 717 else 718 imr_reg |= AR_IMR_RXOK_LP; 719 720 } else { 721 if (ah->config.rx_intr_mitigation) 722 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; 723 else 724 imr_reg |= AR_IMR_RXOK; 725 } 726 727 if (ah->config.tx_intr_mitigation) 728 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; 729 else 730 imr_reg |= AR_IMR_TXOK; 731 732 if (opmode == NL80211_IFTYPE_AP) 733 imr_reg |= AR_IMR_MIB; 734 735 ENABLE_REGWRITE_BUFFER(ah); 736 737 REG_WRITE(ah, AR_IMR, imr_reg); 738 ah->imrs2_reg |= AR_IMR_S2_GTT; 739 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 740 741 if (!AR_SREV_9100(ah)) { 742 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); 743 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); 744 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); 745 } 746 747 REGWRITE_BUFFER_FLUSH(ah); 748 DISABLE_REGWRITE_BUFFER(ah); 749 750 if (AR_SREV_9300_20_OR_LATER(ah)) { 751 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); 752 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); 753 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); 754 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); 755 } 756} 757 758static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 759{ 760 u32 val = ath9k_hw_mac_to_clks(ah, us); 761 val = min(val, (u32) 0xFFFF); 762 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); 763} 764 765static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 766{ 767 u32 val = ath9k_hw_mac_to_clks(ah, us); 768 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); 769 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); 770} 771 772static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 773{ 774 u32 val = ath9k_hw_mac_to_clks(ah, us); 775 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); 776 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); 777} 778 779static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 780{ 781 if (tu > 0xFFFF) { 782 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, 783 "bad global tx timeout %u\n", tu); 784 ah->globaltxtimeout = (u32) -1; 785 return false; 786 } else { 787 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); 788 ah->globaltxtimeout = tu; 789 return true; 790 } 791} 792 793void ath9k_hw_init_global_settings(struct ath_hw *ah) 794{ 795 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 796 int acktimeout; 797 int slottime; 798 int sifstime; 799 800 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 801 ah->misc_mode); 802 803 if (ah->misc_mode != 0) 804 REG_WRITE(ah, AR_PCU_MISC, 805 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); 806 807 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) 808 sifstime = 16; 809 else 810 sifstime = 10; 811 812 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 813 slottime = ah->slottime + 3 * ah->coverage_class; 814 acktimeout = slottime + sifstime; 815 816 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 817 acktimeout += 64 - sifstime - ah->slottime; 818 819 ath9k_hw_setslottime(ah, slottime); 820 ath9k_hw_set_ack_timeout(ah, acktimeout); 821 ath9k_hw_set_cts_timeout(ah, acktimeout); 822 if (ah->globaltxtimeout != (u32) -1) 823 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 824} 825EXPORT_SYMBOL(ath9k_hw_init_global_settings); 826 827void ath9k_hw_deinit(struct ath_hw *ah) 828{ 829 struct ath_common *common = ath9k_hw_common(ah); 830 831 if (common->state < ATH_HW_INITIALIZED) 832 goto free_hw; 833 834 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 835 836free_hw: 837 ath9k_hw_rf_free_ext_banks(ah); 838} 839EXPORT_SYMBOL(ath9k_hw_deinit); 840 841/*******/ 842/* INI */ 843/*******/ 844 845u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) 846{ 847 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 848 849 if (IS_CHAN_B(chan)) 850 ctl |= CTL_11B; 851 else if (IS_CHAN_G(chan)) 852 ctl |= CTL_11G; 853 else 854 ctl |= CTL_11A; 855 856 return ctl; 857} 858 859/****************************************/ 860/* Reset and Channel Switching Routines */ 861/****************************************/ 862 863static inline void ath9k_hw_set_dma(struct ath_hw *ah) 864{ 865 struct ath_common *common = ath9k_hw_common(ah); 866 u32 regval; 867 868 ENABLE_REGWRITE_BUFFER(ah); 869 870 /* 871 * set AHB_MODE not to do cacheline prefetches 872 */ 873 if (!AR_SREV_9300_20_OR_LATER(ah)) { 874 regval = REG_READ(ah, AR_AHB_MODE); 875 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); 876 } 877 878 /* 879 * let mac dma reads be in 128 byte chunks 880 */ 881 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; 882 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); 883 884 REGWRITE_BUFFER_FLUSH(ah); 885 DISABLE_REGWRITE_BUFFER(ah); 886 887 /* 888 * Restore TX Trigger Level to its pre-reset value. 889 * The initial value depends on whether aggregation is enabled, and is 890 * adjusted whenever underruns are detected. 891 */ 892 if (!AR_SREV_9300_20_OR_LATER(ah)) 893 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); 894 895 ENABLE_REGWRITE_BUFFER(ah); 896 897 /* 898 * let mac dma writes be in 128 byte chunks 899 */ 900 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; 901 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); 902 903 /* 904 * Setup receive FIFO threshold to hold off TX activities 905 */ 906 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 907 908 if (AR_SREV_9300_20_OR_LATER(ah)) { 909 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); 910 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); 911 912 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 913 ah->caps.rx_status_len); 914 } 915 916 /* 917 * reduce the number of usable entries in PCU TXBUF to avoid 918 * wrap around issues. 919 */ 920 if (AR_SREV_9285(ah)) { 921 /* For AR9285 the number of Fifos are reduced to half. 922 * So set the usable tx buf size also to half to 923 * avoid data/delimiter underruns 924 */ 925 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 926 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); 927 } else if (!AR_SREV_9271(ah)) { 928 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 929 AR_PCU_TXBUF_CTRL_USABLE_SIZE); 930 } 931 932 REGWRITE_BUFFER_FLUSH(ah); 933 DISABLE_REGWRITE_BUFFER(ah); 934 935 if (AR_SREV_9300_20_OR_LATER(ah)) 936 ath9k_hw_reset_txstatus_ring(ah); 937} 938 939static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) 940{ 941 u32 val; 942 943 val = REG_READ(ah, AR_STA_ID1); 944 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); 945 switch (opmode) { 946 case NL80211_IFTYPE_AP: 947 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP 948 | AR_STA_ID1_KSRCH_MODE); 949 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 950 break; 951 case NL80211_IFTYPE_ADHOC: 952 case NL80211_IFTYPE_MESH_POINT: 953 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC 954 | AR_STA_ID1_KSRCH_MODE); 955 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); 956 break; 957 case NL80211_IFTYPE_STATION: 958 case NL80211_IFTYPE_MONITOR: 959 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); 960 break; 961 } 962} 963 964void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, 965 u32 *coef_mantissa, u32 *coef_exponent) 966{ 967 u32 coef_exp, coef_man; 968 969 for (coef_exp = 31; coef_exp > 0; coef_exp--) 970 if ((coef_scaled >> coef_exp) & 0x1) 971 break; 972 973 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 974 975 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 976 977 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 978 *coef_exponent = coef_exp - 16; 979} 980 981static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 982{ 983 u32 rst_flags; 984 u32 tmpReg; 985 986 if (AR_SREV_9100(ah)) { 987 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); 988 val &= ~AR_RTC_DERIVED_CLK_PERIOD; 989 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); 990 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); 991 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); 992 } 993 994 ENABLE_REGWRITE_BUFFER(ah); 995 996 if (AR_SREV_9300_20_OR_LATER(ah)) { 997 REG_WRITE(ah, AR_WA, ah->WARegVal); 998 udelay(10); 999 } 1000 1001 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1002 AR_RTC_FORCE_WAKE_ON_INT); 1003 1004 if (AR_SREV_9100(ah)) { 1005 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | 1006 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; 1007 } else { 1008 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); 1009 if (tmpReg & 1010 (AR_INTR_SYNC_LOCAL_TIMEOUT | 1011 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1012 u32 val; 1013 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1014 1015 val = AR_RC_HOSTIF; 1016 if (!AR_SREV_9300_20_OR_LATER(ah)) 1017 val |= AR_RC_AHB; 1018 REG_WRITE(ah, AR_RC, val); 1019 1020 } else if (!AR_SREV_9300_20_OR_LATER(ah)) 1021 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1022 1023 rst_flags = AR_RTC_RC_MAC_WARM; 1024 if (type == ATH9K_RESET_COLD) 1025 rst_flags |= AR_RTC_RC_MAC_COLD; 1026 } 1027 1028 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1029 1030 REGWRITE_BUFFER_FLUSH(ah); 1031 DISABLE_REGWRITE_BUFFER(ah); 1032 1033 udelay(50); 1034 1035 REG_WRITE(ah, AR_RTC_RC, 0); 1036 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1037 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1038 "RTC stuck in MAC reset\n"); 1039 return false; 1040 } 1041 1042 if (!AR_SREV_9100(ah)) 1043 REG_WRITE(ah, AR_RC, 0); 1044 1045 if (AR_SREV_9100(ah)) 1046 udelay(50); 1047 1048 return true; 1049} 1050 1051static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) 1052{ 1053 ENABLE_REGWRITE_BUFFER(ah); 1054 1055 if (AR_SREV_9300_20_OR_LATER(ah)) { 1056 REG_WRITE(ah, AR_WA, ah->WARegVal); 1057 udelay(10); 1058 } 1059 1060 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1061 AR_RTC_FORCE_WAKE_ON_INT); 1062 1063 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1064 REG_WRITE(ah, AR_RC, AR_RC_AHB); 1065 1066 REG_WRITE(ah, AR_RTC_RESET, 0); 1067 udelay(2); 1068 1069 REGWRITE_BUFFER_FLUSH(ah); 1070 DISABLE_REGWRITE_BUFFER(ah); 1071 1072 if (!AR_SREV_9300_20_OR_LATER(ah)) 1073 udelay(2); 1074 1075 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1076 REG_WRITE(ah, AR_RC, 0); 1077 1078 REG_WRITE(ah, AR_RTC_RESET, 1); 1079 1080 if (!ath9k_hw_wait(ah, 1081 AR_RTC_STATUS, 1082 AR_RTC_STATUS_M, 1083 AR_RTC_STATUS_ON, 1084 AH_WAIT_TIMEOUT)) { 1085 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 1086 "RTC not waking up\n"); 1087 return false; 1088 } 1089 1090 ath9k_hw_read_revisions(ah); 1091 1092 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); 1093} 1094 1095static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) 1096{ 1097 if (AR_SREV_9300_20_OR_LATER(ah)) { 1098 REG_WRITE(ah, AR_WA, ah->WARegVal); 1099 udelay(10); 1100 } 1101 1102 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1103 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1104 1105 switch (type) { 1106 case ATH9K_RESET_POWER_ON: 1107 return ath9k_hw_set_reset_power_on(ah); 1108 case ATH9K_RESET_WARM: 1109 case ATH9K_RESET_COLD: 1110 return ath9k_hw_set_reset(ah, type); 1111 default: 1112 return false; 1113 } 1114} 1115 1116static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1117 struct ath9k_channel *chan) 1118{ 1119 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { 1120 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) 1121 return false; 1122 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 1123 return false; 1124 1125 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1126 return false; 1127 1128 ah->chip_fullsleep = false; 1129 ath9k_hw_init_pll(ah, chan); 1130 ath9k_hw_set_rfmode(ah, chan); 1131 1132 return true; 1133} 1134 1135static bool ath9k_hw_channel_change(struct ath_hw *ah, 1136 struct ath9k_channel *chan) 1137{ 1138 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1139 struct ath_common *common = ath9k_hw_common(ah); 1140 struct ieee80211_channel *channel = chan->chan; 1141 u32 qnum; 1142 int r; 1143 1144 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1145 if (ath9k_hw_numtxpending(ah, qnum)) { 1146 ath_print(common, ATH_DBG_QUEUE, 1147 "Transmit frames pending on " 1148 "queue %d\n", qnum); 1149 return false; 1150 } 1151 } 1152 1153 if (!ath9k_hw_rfbus_req(ah)) { 1154 ath_print(common, ATH_DBG_FATAL, 1155 "Could not kill baseband RX\n"); 1156 return false; 1157 } 1158 1159 ath9k_hw_set_channel_regs(ah, chan); 1160 1161 r = ath9k_hw_rf_set_freq(ah, chan); 1162 if (r) { 1163 ath_print(common, ATH_DBG_FATAL, 1164 "Failed to set channel\n"); 1165 return false; 1166 } 1167 1168 ah->eep_ops->set_txpower(ah, chan, 1169 ath9k_regd_get_ctl(regulatory, chan), 1170 channel->max_antenna_gain * 2, 1171 channel->max_power * 2, 1172 min((u32) MAX_RATE_POWER, 1173 (u32) regulatory->power_limit)); 1174 1175 ath9k_hw_rfbus_done(ah); 1176 1177 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1178 ath9k_hw_set_delta_slope(ah, chan); 1179 1180 ath9k_hw_spur_mitigate_freq(ah, chan); 1181 1182 return true; 1183} 1184 1185bool ath9k_hw_check_alive(struct ath_hw *ah) 1186{ 1187 int count = 50; 1188 u32 reg; 1189 1190 if (AR_SREV_9285_10_OR_LATER(ah)) 1191 return true; 1192 1193 do { 1194 reg = REG_READ(ah, AR_OBS_BUS_1); 1195 1196 if ((reg & 0x7E7FFFEF) == 0x00702400) 1197 continue; 1198 1199 switch (reg & 0x7E000B00) { 1200 case 0x1E000000: 1201 case 0x52000B00: 1202 case 0x18000B00: 1203 continue; 1204 default: 1205 return true; 1206 } 1207 } while (count-- > 0); 1208 1209 return false; 1210} 1211EXPORT_SYMBOL(ath9k_hw_check_alive); 1212 1213int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1214 struct ath9k_hw_cal_data *caldata, bool bChannelChange) 1215{ 1216 struct ath_common *common = ath9k_hw_common(ah); 1217 u32 saveLedState; 1218 struct ath9k_channel *curchan = ah->curchan; 1219 u32 saveDefAntenna; 1220 u32 macStaId1; 1221 u64 tsf = 0; 1222 int i, r; 1223 1224 ah->txchainmask = common->tx_chainmask; 1225 ah->rxchainmask = common->rx_chainmask; 1226 1227 if (!ah->chip_fullsleep) { 1228 ath9k_hw_abortpcurecv(ah); 1229 if (!ath9k_hw_stopdmarecv(ah)) { 1230 ath_print(common, ATH_DBG_XMIT, 1231 "Failed to stop receive dma\n"); 1232 bChannelChange = false; 1233 } 1234 } 1235 1236 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 1237 return -EIO; 1238 1239 if (curchan && !ah->chip_fullsleep && ah->caldata) 1240 ath9k_hw_getnf(ah, curchan); 1241 1242 ah->caldata = caldata; 1243 if (caldata && 1244 (chan->channel != caldata->channel || 1245 (chan->channelFlags & ~CHANNEL_CW_INT) != 1246 (caldata->channelFlags & ~CHANNEL_CW_INT))) { 1247 /* Operating channel changed, reset channel calibration data */ 1248 memset(caldata, 0, sizeof(*caldata)); 1249 ath9k_init_nfcal_hist_buffer(ah, chan); 1250 } 1251 1252 if (bChannelChange && 1253 (ah->chip_fullsleep != true) && 1254 (ah->curchan != NULL) && 1255 (chan->channel != ah->curchan->channel) && 1256 ((chan->channelFlags & CHANNEL_ALL) == 1257 (ah->curchan->channelFlags & CHANNEL_ALL)) && 1258 !AR_SREV_9280(ah)) { 1259 1260 if (ath9k_hw_channel_change(ah, chan)) { 1261 ath9k_hw_loadnf(ah, ah->curchan); 1262 ath9k_hw_start_nfcal(ah, true); 1263 return 0; 1264 } 1265 } 1266 1267 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); 1268 if (saveDefAntenna == 0) 1269 saveDefAntenna = 1; 1270 1271 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; 1272 1273 /* For chips on which RTC reset is done, save TSF before it gets cleared */ 1274 if (AR_SREV_9100(ah) || 1275 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) 1276 tsf = ath9k_hw_gettsf64(ah); 1277 1278 saveLedState = REG_READ(ah, AR_CFG_LED) & 1279 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | 1280 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); 1281 1282 ath9k_hw_mark_phy_inactive(ah); 1283 1284 /* Only required on the first reset */ 1285 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1286 REG_WRITE(ah, 1287 AR9271_RESET_POWER_DOWN_CONTROL, 1288 AR9271_RADIO_RF_RST); 1289 udelay(50); 1290 } 1291 1292 if (!ath9k_hw_chip_reset(ah, chan)) { 1293 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); 1294 return -EINVAL; 1295 } 1296 1297 /* Only required on the first reset */ 1298 if (AR_SREV_9271(ah) && ah->htc_reset_init) { 1299 ah->htc_reset_init = false; 1300 REG_WRITE(ah, 1301 AR9271_RESET_POWER_DOWN_CONTROL, 1302 AR9271_GATE_MAC_CTL); 1303 udelay(50); 1304 } 1305 1306 /* Restore TSF */ 1307 if (tsf) 1308 ath9k_hw_settsf64(ah, tsf); 1309 1310 if (AR_SREV_9280_10_OR_LATER(ah)) 1311 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1312 1313 if (!AR_SREV_9300_20_OR_LATER(ah)) 1314 ar9002_hw_enable_async_fifo(ah); 1315 1316 r = ath9k_hw_process_ini(ah, chan); 1317 if (r) 1318 return r; 1319 1320 /* 1321 * Some AR91xx SoC devices frequently fail to accept TSF writes 1322 * right after the chip reset. When that happens, write a new 1323 * value after the initvals have been applied, with an offset 1324 * based on measured time difference 1325 */ 1326 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { 1327 tsf += 1500; 1328 ath9k_hw_settsf64(ah, tsf); 1329 } 1330 1331 /* Setup MFP options for CCMP */ 1332 if (AR_SREV_9280_20_OR_LATER(ah)) { 1333 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt 1334 * frames when constructing CCMP AAD. */ 1335 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, 1336 0xc7ff); 1337 ah->sw_mgmt_crypto = false; 1338 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 1339 /* Disable hardware crypto for management frames */ 1340 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, 1341 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); 1342 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, 1343 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); 1344 ah->sw_mgmt_crypto = true; 1345 } else 1346 ah->sw_mgmt_crypto = true; 1347 1348 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1349 ath9k_hw_set_delta_slope(ah, chan); 1350 1351 ath9k_hw_spur_mitigate_freq(ah, chan); 1352 ah->eep_ops->set_board_values(ah, chan); 1353 1354 ath9k_hw_set_operating_mode(ah, ah->opmode); 1355 1356 ENABLE_REGWRITE_BUFFER(ah); 1357 1358 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1359 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) 1360 | macStaId1 1361 | AR_STA_ID1_RTS_USE_DEF 1362 | (ah->config. 1363 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) 1364 | ah->sta_id1_defaults); 1365 ath_hw_setbssidmask(common); 1366 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 1367 ath9k_hw_write_associd(ah); 1368 REG_WRITE(ah, AR_ISR, ~0); 1369 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1370 1371 REGWRITE_BUFFER_FLUSH(ah); 1372 DISABLE_REGWRITE_BUFFER(ah); 1373 1374 r = ath9k_hw_rf_set_freq(ah, chan); 1375 if (r) 1376 return r; 1377 1378 ENABLE_REGWRITE_BUFFER(ah); 1379 1380 for (i = 0; i < AR_NUM_DCU; i++) 1381 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 1382 1383 REGWRITE_BUFFER_FLUSH(ah); 1384 DISABLE_REGWRITE_BUFFER(ah); 1385 1386 ah->intr_txqs = 0; 1387 for (i = 0; i < ah->caps.total_queues; i++) 1388 ath9k_hw_resettxqueue(ah, i); 1389 1390 ath9k_hw_init_interrupt_masks(ah, ah->opmode); 1391 ath9k_hw_ani_cache_ini_regs(ah); 1392 ath9k_hw_init_qos(ah); 1393 1394 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) 1395 ath9k_enable_rfkill(ah); 1396 1397 ath9k_hw_init_global_settings(ah); 1398 1399 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1400 ar9002_hw_update_async_fifo(ah); 1401 ar9002_hw_enable_wep_aggregation(ah); 1402 } 1403 1404 REG_WRITE(ah, AR_STA_ID1, 1405 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 1406 1407 ath9k_hw_set_dma(ah); 1408 1409 REG_WRITE(ah, AR_OBS, 8); 1410 1411 if (ah->config.rx_intr_mitigation) { 1412 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 1413 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 1414 } 1415 1416 if (ah->config.tx_intr_mitigation) { 1417 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); 1418 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); 1419 } 1420 1421 ath9k_hw_init_bb(ah, chan); 1422 1423 if (!ath9k_hw_init_cal(ah, chan)) 1424 return -EIO; 1425 1426 ENABLE_REGWRITE_BUFFER(ah); 1427 1428 ath9k_hw_restore_chainmask(ah); 1429 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1430 1431 REGWRITE_BUFFER_FLUSH(ah); 1432 DISABLE_REGWRITE_BUFFER(ah); 1433 1434 /* 1435 * For big endian systems turn on swapping for descriptors 1436 */ 1437 if (AR_SREV_9100(ah)) { 1438 u32 mask; 1439 mask = REG_READ(ah, AR_CFG); 1440 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 1441 ath_print(common, ATH_DBG_RESET, 1442 "CFG Byte Swap Set 0x%x\n", mask); 1443 } else { 1444 mask = 1445 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 1446 REG_WRITE(ah, AR_CFG, mask); 1447 ath_print(common, ATH_DBG_RESET, 1448 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 1449 } 1450 } else { 1451 if (common->bus_ops->ath_bus_type == ATH_USB) { 1452 /* Configure AR9271 target WLAN */ 1453 if (AR_SREV_9271(ah)) 1454 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); 1455 else 1456 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1457 } 1458#ifdef __BIG_ENDIAN 1459 else 1460 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1461#endif 1462 } 1463 1464 if (ah->btcoex_hw.enabled) 1465 ath9k_hw_btcoex_enable(ah); 1466 1467 if (AR_SREV_9300_20_OR_LATER(ah)) 1468 ar9003_hw_bb_watchdog_config(ah); 1469 1470 return 0; 1471} 1472EXPORT_SYMBOL(ath9k_hw_reset); 1473 1474/************************/ 1475/* Key Cache Management */ 1476/************************/ 1477 1478bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) 1479{ 1480 u32 keyType; 1481 1482 if (entry >= ah->caps.keycache_size) { 1483 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1484 "keychache entry %u out of range\n", entry); 1485 return false; 1486 } 1487 1488 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 1489 1490 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 1491 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 1492 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 1493 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); 1494 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); 1495 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 1496 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); 1497 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); 1498 1499 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 1500 u16 micentry = entry + 64; 1501 1502 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); 1503 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 1504 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); 1505 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 1506 1507 } 1508 1509 return true; 1510} 1511EXPORT_SYMBOL(ath9k_hw_keyreset); 1512 1513static bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) 1514{ 1515 u32 macHi, macLo; 1516 u32 unicast_flag = AR_KEYTABLE_VALID; 1517 1518 if (entry >= ah->caps.keycache_size) { 1519 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1520 "keychache entry %u out of range\n", entry); 1521 return false; 1522 } 1523 1524 if (mac != NULL) { 1525 /* 1526 * AR_KEYTABLE_VALID indicates that the address is a unicast 1527 * address, which must match the transmitter address for 1528 * decrypting frames. 1529 * Not setting this bit allows the hardware to use the key 1530 * for multicast frame decryption. 1531 */ 1532 if (mac[0] & 0x01) 1533 unicast_flag = 0; 1534 1535 macHi = (mac[5] << 8) | mac[4]; 1536 macLo = (mac[3] << 24) | 1537 (mac[2] << 16) | 1538 (mac[1] << 8) | 1539 mac[0]; 1540 macLo >>= 1; 1541 macLo |= (macHi & 1) << 31; 1542 macHi >>= 1; 1543 } else { 1544 macLo = macHi = 0; 1545 } 1546 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); 1547 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag); 1548 1549 return true; 1550} 1551 1552bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, 1553 const struct ath9k_keyval *k, 1554 const u8 *mac) 1555{ 1556 const struct ath9k_hw_capabilities *pCap = &ah->caps; 1557 struct ath_common *common = ath9k_hw_common(ah); 1558 u32 key0, key1, key2, key3, key4; 1559 u32 keyType; 1560 1561 if (entry >= pCap->keycache_size) { 1562 ath_print(common, ATH_DBG_FATAL, 1563 "keycache entry %u out of range\n", entry); 1564 return false; 1565 } 1566 1567 switch (k->kv_type) { 1568 case ATH9K_CIPHER_AES_OCB: 1569 keyType = AR_KEYTABLE_TYPE_AES; 1570 break; 1571 case ATH9K_CIPHER_AES_CCM: 1572 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 1573 ath_print(common, ATH_DBG_ANY, 1574 "AES-CCM not supported by mac rev 0x%x\n", 1575 ah->hw_version.macRev); 1576 return false; 1577 } 1578 keyType = AR_KEYTABLE_TYPE_CCM; 1579 break; 1580 case ATH9K_CIPHER_TKIP: 1581 keyType = AR_KEYTABLE_TYPE_TKIP; 1582 if (ATH9K_IS_MIC_ENABLED(ah) 1583 && entry + 64 >= pCap->keycache_size) { 1584 ath_print(common, ATH_DBG_ANY, 1585 "entry %u inappropriate for TKIP\n", entry); 1586 return false; 1587 } 1588 break; 1589 case ATH9K_CIPHER_WEP: 1590 if (k->kv_len < WLAN_KEY_LEN_WEP40) { 1591 ath_print(common, ATH_DBG_ANY, 1592 "WEP key length %u too small\n", k->kv_len); 1593 return false; 1594 } 1595 if (k->kv_len <= WLAN_KEY_LEN_WEP40) 1596 keyType = AR_KEYTABLE_TYPE_40; 1597 else if (k->kv_len <= WLAN_KEY_LEN_WEP104) 1598 keyType = AR_KEYTABLE_TYPE_104; 1599 else 1600 keyType = AR_KEYTABLE_TYPE_128; 1601 break; 1602 case ATH9K_CIPHER_CLR: 1603 keyType = AR_KEYTABLE_TYPE_CLR; 1604 break; 1605 default: 1606 ath_print(common, ATH_DBG_FATAL, 1607 "cipher %u not supported\n", k->kv_type); 1608 return false; 1609 } 1610 1611 key0 = get_unaligned_le32(k->kv_val + 0); 1612 key1 = get_unaligned_le16(k->kv_val + 4); 1613 key2 = get_unaligned_le32(k->kv_val + 6); 1614 key3 = get_unaligned_le16(k->kv_val + 10); 1615 key4 = get_unaligned_le32(k->kv_val + 12); 1616 if (k->kv_len <= WLAN_KEY_LEN_WEP104) 1617 key4 &= 0xff; 1618 1619 /* 1620 * Note: Key cache registers access special memory area that requires 1621 * two 32-bit writes to actually update the values in the internal 1622 * memory. Consequently, the exact order and pairs used here must be 1623 * maintained. 1624 */ 1625 1626 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { 1627 u16 micentry = entry + 64; 1628 1629 /* 1630 * Write inverted key[47:0] first to avoid Michael MIC errors 1631 * on frames that could be sent or received at the same time. 1632 * The correct key will be written in the end once everything 1633 * else is ready. 1634 */ 1635 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); 1636 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); 1637 1638 /* Write key[95:48] */ 1639 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 1640 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 1641 1642 /* Write key[127:96] and key type */ 1643 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 1644 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 1645 1646 /* Write MAC address for the entry */ 1647 (void) ath9k_hw_keysetmac(ah, entry, mac); 1648 1649 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { 1650 /* 1651 * TKIP uses two key cache entries: 1652 * Michael MIC TX/RX keys in the same key cache entry 1653 * (idx = main index + 64): 1654 * key0 [31:0] = RX key [31:0] 1655 * key1 [15:0] = TX key [31:16] 1656 * key1 [31:16] = reserved 1657 * key2 [31:0] = RX key [63:32] 1658 * key3 [15:0] = TX key [15:0] 1659 * key3 [31:16] = reserved 1660 * key4 [31:0] = TX key [63:32] 1661 */ 1662 u32 mic0, mic1, mic2, mic3, mic4; 1663 1664 mic0 = get_unaligned_le32(k->kv_mic + 0); 1665 mic2 = get_unaligned_le32(k->kv_mic + 4); 1666 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; 1667 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; 1668 mic4 = get_unaligned_le32(k->kv_txmic + 4); 1669 1670 /* Write RX[31:0] and TX[31:16] */ 1671 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 1672 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); 1673 1674 /* Write RX[63:32] and TX[15:0] */ 1675 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 1676 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); 1677 1678 /* Write TX[63:32] and keyType(reserved) */ 1679 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); 1680 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 1681 AR_KEYTABLE_TYPE_CLR); 1682 1683 } else { 1684 /* 1685 * TKIP uses four key cache entries (two for group 1686 * keys): 1687 * Michael MIC TX/RX keys are in different key cache 1688 * entries (idx = main index + 64 for TX and 1689 * main index + 32 + 96 for RX): 1690 * key0 [31:0] = TX/RX MIC key [31:0] 1691 * key1 [31:0] = reserved 1692 * key2 [31:0] = TX/RX MIC key [63:32] 1693 * key3 [31:0] = reserved 1694 * key4 [31:0] = reserved 1695 * 1696 * Upper layer code will call this function separately 1697 * for TX and RX keys when these registers offsets are 1698 * used. 1699 */ 1700 u32 mic0, mic2; 1701 1702 mic0 = get_unaligned_le32(k->kv_mic + 0); 1703 mic2 = get_unaligned_le32(k->kv_mic + 4); 1704 1705 /* Write MIC key[31:0] */ 1706 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); 1707 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); 1708 1709 /* Write MIC key[63:32] */ 1710 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); 1711 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); 1712 1713 /* Write TX[63:32] and keyType(reserved) */ 1714 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); 1715 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), 1716 AR_KEYTABLE_TYPE_CLR); 1717 } 1718 1719 /* MAC address registers are reserved for the MIC entry */ 1720 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); 1721 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); 1722 1723 /* 1724 * Write the correct (un-inverted) key[47:0] last to enable 1725 * TKIP now that all other registers are set with correct 1726 * values. 1727 */ 1728 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 1729 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 1730 } else { 1731 /* Write key[47:0] */ 1732 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); 1733 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); 1734 1735 /* Write key[95:48] */ 1736 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); 1737 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); 1738 1739 /* Write key[127:96] and key type */ 1740 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); 1741 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); 1742 1743 /* Write MAC address for the entry */ 1744 (void) ath9k_hw_keysetmac(ah, entry, mac); 1745 } 1746 1747 return true; 1748} 1749EXPORT_SYMBOL(ath9k_hw_set_keycache_entry); 1750 1751/******************************/ 1752/* Power Management (Chipset) */ 1753/******************************/ 1754 1755/* 1756 * Notify Power Mgt is disabled in self-generated frames. 1757 * If requested, force chip to sleep. 1758 */ 1759static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) 1760{ 1761 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1762 if (setChip) { 1763 /* 1764 * Clear the RTC force wake bit to allow the 1765 * mac to go to sleep. 1766 */ 1767 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1768 AR_RTC_FORCE_WAKE_EN); 1769 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) 1770 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 1771 1772 /* Shutdown chip. Active low */ 1773 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) 1774 REG_CLR_BIT(ah, (AR_RTC_RESET), 1775 AR_RTC_RESET_EN); 1776 } 1777 1778 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ 1779 if (AR_SREV_9300_20_OR_LATER(ah)) 1780 REG_WRITE(ah, AR_WA, 1781 ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1782} 1783 1784/* 1785 * Notify Power Management is enabled in self-generating 1786 * frames. If request, set power mode of chip to 1787 * auto/normal. Duration in units of 128us (1/8 TU). 1788 */ 1789static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) 1790{ 1791 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1792 if (setChip) { 1793 struct ath9k_hw_capabilities *pCap = &ah->caps; 1794 1795 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { 1796 /* Set WakeOnInterrupt bit; clear ForceWake bit */ 1797 REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1798 AR_RTC_FORCE_WAKE_ON_INT); 1799 } else { 1800 /* 1801 * Clear the RTC force wake bit to allow the 1802 * mac to go to sleep. 1803 */ 1804 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, 1805 AR_RTC_FORCE_WAKE_EN); 1806 } 1807 } 1808 1809 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ 1810 if (AR_SREV_9300_20_OR_LATER(ah)) 1811 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); 1812} 1813 1814static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) 1815{ 1816 u32 val; 1817 int i; 1818 1819 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ 1820 if (AR_SREV_9300_20_OR_LATER(ah)) { 1821 REG_WRITE(ah, AR_WA, ah->WARegVal); 1822 udelay(10); 1823 } 1824 1825 if (setChip) { 1826 if ((REG_READ(ah, AR_RTC_STATUS) & 1827 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { 1828 if (ath9k_hw_set_reset_reg(ah, 1829 ATH9K_RESET_POWER_ON) != true) { 1830 return false; 1831 } 1832 if (!AR_SREV_9300_20_OR_LATER(ah)) 1833 ath9k_hw_init_pll(ah, NULL); 1834 } 1835 if (AR_SREV_9100(ah)) 1836 REG_SET_BIT(ah, AR_RTC_RESET, 1837 AR_RTC_RESET_EN); 1838 1839 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1840 AR_RTC_FORCE_WAKE_EN); 1841 udelay(50); 1842 1843 for (i = POWER_UP_TIME / 50; i > 0; i--) { 1844 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; 1845 if (val == AR_RTC_STATUS_ON) 1846 break; 1847 udelay(50); 1848 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, 1849 AR_RTC_FORCE_WAKE_EN); 1850 } 1851 if (i == 0) { 1852 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 1853 "Failed to wakeup in %uus\n", 1854 POWER_UP_TIME / 20); 1855 return false; 1856 } 1857 } 1858 1859 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); 1860 1861 return true; 1862} 1863 1864bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) 1865{ 1866 struct ath_common *common = ath9k_hw_common(ah); 1867 int status = true, setChip = true; 1868 static const char *modes[] = { 1869 "AWAKE", 1870 "FULL-SLEEP", 1871 "NETWORK SLEEP", 1872 "UNDEFINED" 1873 }; 1874 1875 if (ah->power_mode == mode) 1876 return status; 1877 1878 ath_print(common, ATH_DBG_RESET, "%s -> %s\n", 1879 modes[ah->power_mode], modes[mode]); 1880 1881 switch (mode) { 1882 case ATH9K_PM_AWAKE: 1883 status = ath9k_hw_set_power_awake(ah, setChip); 1884 break; 1885 case ATH9K_PM_FULL_SLEEP: 1886 ath9k_set_power_sleep(ah, setChip); 1887 ah->chip_fullsleep = true; 1888 break; 1889 case ATH9K_PM_NETWORK_SLEEP: 1890 ath9k_set_power_network_sleep(ah, setChip); 1891 break; 1892 default: 1893 ath_print(common, ATH_DBG_FATAL, 1894 "Unknown power mode %u\n", mode); 1895 return false; 1896 } 1897 ah->power_mode = mode; 1898 1899 return status; 1900} 1901EXPORT_SYMBOL(ath9k_hw_setpower); 1902 1903/*******************/ 1904/* Beacon Handling */ 1905/*******************/ 1906 1907void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) 1908{ 1909 int flags = 0; 1910 1911 ah->beacon_interval = beacon_period; 1912 1913 ENABLE_REGWRITE_BUFFER(ah); 1914 1915 switch (ah->opmode) { 1916 case NL80211_IFTYPE_STATION: 1917 case NL80211_IFTYPE_MONITOR: 1918 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 1919 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); 1920 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); 1921 flags |= AR_TBTT_TIMER_EN; 1922 break; 1923 case NL80211_IFTYPE_ADHOC: 1924 case NL80211_IFTYPE_MESH_POINT: 1925 REG_SET_BIT(ah, AR_TXCFG, 1926 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); 1927 REG_WRITE(ah, AR_NEXT_NDP_TIMER, 1928 TU_TO_USEC(next_beacon + 1929 (ah->atim_window ? ah-> 1930 atim_window : 1))); 1931 flags |= AR_NDP_TIMER_EN; 1932 case NL80211_IFTYPE_AP: 1933 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); 1934 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 1935 TU_TO_USEC(next_beacon - 1936 ah->config. 1937 dma_beacon_response_time)); 1938 REG_WRITE(ah, AR_NEXT_SWBA, 1939 TU_TO_USEC(next_beacon - 1940 ah->config. 1941 sw_beacon_response_time)); 1942 flags |= 1943 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 1944 break; 1945 default: 1946 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, 1947 "%s: unsupported opmode: %d\n", 1948 __func__, ah->opmode); 1949 return; 1950 break; 1951 } 1952 1953 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1954 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); 1955 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); 1956 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); 1957 1958 REGWRITE_BUFFER_FLUSH(ah); 1959 DISABLE_REGWRITE_BUFFER(ah); 1960 1961 beacon_period &= ~ATH9K_BEACON_ENA; 1962 if (beacon_period & ATH9K_BEACON_RESET_TSF) { 1963 ath9k_hw_reset_tsf(ah); 1964 } 1965 1966 REG_SET_BIT(ah, AR_TIMER_MODE, flags); 1967} 1968EXPORT_SYMBOL(ath9k_hw_beaconinit); 1969 1970void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, 1971 const struct ath9k_beacon_state *bs) 1972{ 1973 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; 1974 struct ath9k_hw_capabilities *pCap = &ah->caps; 1975 struct ath_common *common = ath9k_hw_common(ah); 1976 1977 ENABLE_REGWRITE_BUFFER(ah); 1978 1979 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1980 1981 REG_WRITE(ah, AR_BEACON_PERIOD, 1982 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1983 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1984 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1985 1986 REGWRITE_BUFFER_FLUSH(ah); 1987 DISABLE_REGWRITE_BUFFER(ah); 1988 1989 REG_RMW_FIELD(ah, AR_RSSI_THR, 1990 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1991 1992 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; 1993 1994 if (bs->bs_sleepduration > beaconintval) 1995 beaconintval = bs->bs_sleepduration; 1996 1997 dtimperiod = bs->bs_dtimperiod; 1998 if (bs->bs_sleepduration > dtimperiod) 1999 dtimperiod = bs->bs_sleepduration; 2000 2001 if (beaconintval == dtimperiod) 2002 nextTbtt = bs->bs_nextdtim; 2003 else 2004 nextTbtt = bs->bs_nexttbtt; 2005 2006 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 2007 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 2008 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 2009 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 2010 2011 ENABLE_REGWRITE_BUFFER(ah); 2012 2013 REG_WRITE(ah, AR_NEXT_DTIM, 2014 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 2015 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); 2016 2017 REG_WRITE(ah, AR_SLEEP1, 2018 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) 2019 | AR_SLEEP1_ASSUME_DTIM); 2020 2021 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) 2022 beacontimeout = (BEACON_TIMEOUT_VAL << 3); 2023 else 2024 beacontimeout = MIN_BEACON_TIMEOUT_VAL; 2025 2026 REG_WRITE(ah, AR_SLEEP2, 2027 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); 2028 2029 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); 2030 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); 2031 2032 REGWRITE_BUFFER_FLUSH(ah); 2033 DISABLE_REGWRITE_BUFFER(ah); 2034 2035 REG_SET_BIT(ah, AR_TIMER_MODE, 2036 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | 2037 AR_DTIM_TIMER_EN); 2038 2039 /* TSF Out of Range Threshold */ 2040 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); 2041} 2042EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); 2043 2044/*******************/ 2045/* HW Capabilities */ 2046/*******************/ 2047 2048int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2049{ 2050 struct ath9k_hw_capabilities *pCap = &ah->caps; 2051 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2052 struct ath_common *common = ath9k_hw_common(ah); 2053 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 2054 2055 u16 capField = 0, eeval; 2056 2057 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); 2058 regulatory->current_rd = eeval; 2059 2060 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); 2061 if (AR_SREV_9285_10_OR_LATER(ah)) 2062 eeval |= AR9285_RDEXT_DEFAULT; 2063 regulatory->current_rd_ext = eeval; 2064 2065 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); 2066 2067 if (ah->opmode != NL80211_IFTYPE_AP && 2068 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { 2069 if (regulatory->current_rd == 0x64 || 2070 regulatory->current_rd == 0x65) 2071 regulatory->current_rd += 5; 2072 else if (regulatory->current_rd == 0x41) 2073 regulatory->current_rd = 0x43; 2074 ath_print(common, ATH_DBG_REGULATORY, 2075 "regdomain mapped to 0x%x\n", regulatory->current_rd); 2076 } 2077 2078 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); 2079 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { 2080 ath_print(common, ATH_DBG_FATAL, 2081 "no band has been marked as supported in EEPROM.\n"); 2082 return -EINVAL; 2083 } 2084 2085 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); 2086 2087 if (eeval & AR5416_OPFLAGS_11A) { 2088 set_bit(ATH9K_MODE_11A, pCap->wireless_modes); 2089 if (ah->config.ht_enable) { 2090 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) 2091 set_bit(ATH9K_MODE_11NA_HT20, 2092 pCap->wireless_modes); 2093 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { 2094 set_bit(ATH9K_MODE_11NA_HT40PLUS, 2095 pCap->wireless_modes); 2096 set_bit(ATH9K_MODE_11NA_HT40MINUS, 2097 pCap->wireless_modes); 2098 } 2099 } 2100 } 2101 2102 if (eeval & AR5416_OPFLAGS_11G) { 2103 set_bit(ATH9K_MODE_11G, pCap->wireless_modes); 2104 if (ah->config.ht_enable) { 2105 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) 2106 set_bit(ATH9K_MODE_11NG_HT20, 2107 pCap->wireless_modes); 2108 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { 2109 set_bit(ATH9K_MODE_11NG_HT40PLUS, 2110 pCap->wireless_modes); 2111 set_bit(ATH9K_MODE_11NG_HT40MINUS, 2112 pCap->wireless_modes); 2113 } 2114 } 2115 } 2116 2117 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2118 /* 2119 * For AR9271 we will temporarilly uses the rx chainmax as read from 2120 * the EEPROM. 2121 */ 2122 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && 2123 !(eeval & AR5416_OPFLAGS_11A) && 2124 !(AR_SREV_9271(ah))) 2125 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ 2126 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; 2127 else 2128 /* Use rx_chainmask from EEPROM. */ 2129 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2130 2131 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) 2132 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2133 2134 pCap->low_2ghz_chan = 2312; 2135 pCap->high_2ghz_chan = 2732; 2136 2137 pCap->low_5ghz_chan = 4920; 2138 pCap->high_5ghz_chan = 6100; 2139 2140 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; 2141 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; 2142 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; 2143 2144 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; 2145 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; 2146 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; 2147 2148 if (ah->config.ht_enable) 2149 pCap->hw_caps |= ATH9K_HW_CAP_HT; 2150 else 2151 pCap->hw_caps &= ~ATH9K_HW_CAP_HT; 2152 2153 pCap->hw_caps |= ATH9K_HW_CAP_GTT; 2154 pCap->hw_caps |= ATH9K_HW_CAP_VEOL; 2155 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; 2156 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; 2157 2158 if (capField & AR_EEPROM_EEPCAP_MAXQCU) 2159 pCap->total_queues = 2160 MS(capField, AR_EEPROM_EEPCAP_MAXQCU); 2161 else 2162 pCap->total_queues = ATH9K_NUM_TX_QUEUES; 2163 2164 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) 2165 pCap->keycache_size = 2166 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); 2167 else 2168 pCap->keycache_size = AR_KEYTABLE_SIZE; 2169 2170 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; 2171 2172 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) 2173 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; 2174 else 2175 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; 2176 2177 if (AR_SREV_9271(ah)) 2178 pCap->num_gpio_pins = AR9271_NUM_GPIO; 2179 else if (AR_DEVID_7010(ah)) 2180 pCap->num_gpio_pins = AR7010_NUM_GPIO; 2181 else if (AR_SREV_9285_10_OR_LATER(ah)) 2182 pCap->num_gpio_pins = AR9285_NUM_GPIO; 2183 else if (AR_SREV_9280_10_OR_LATER(ah)) 2184 pCap->num_gpio_pins = AR928X_NUM_GPIO; 2185 else 2186 pCap->num_gpio_pins = AR_NUM_GPIO; 2187 2188 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { 2189 pCap->hw_caps |= ATH9K_HW_CAP_CST; 2190 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; 2191 } else { 2192 pCap->rts_aggr_limit = (8 * 1024); 2193 } 2194 2195 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; 2196 2197#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 2198 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); 2199 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { 2200 ah->rfkill_gpio = 2201 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); 2202 ah->rfkill_polarity = 2203 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); 2204 2205 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; 2206 } 2207#endif 2208 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) 2209 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; 2210 else 2211 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; 2212 2213 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) 2214 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; 2215 else 2216 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; 2217 2218 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { 2219 pCap->reg_cap = 2220 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2221 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | 2222 AR_EEPROM_EEREGCAP_EN_KK_U2 | 2223 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; 2224 } else { 2225 pCap->reg_cap = 2226 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | 2227 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; 2228 } 2229 2230 /* Advertise midband for AR5416 with FCC midband set in eeprom */ 2231 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && 2232 AR_SREV_5416(ah)) 2233 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; 2234 2235 pCap->num_antcfg_5ghz = 2236 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); 2237 pCap->num_antcfg_2ghz = 2238 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); 2239 2240 if (AR_SREV_9280_10_OR_LATER(ah) && 2241 ath9k_hw_btcoex_supported(ah)) { 2242 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; 2243 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; 2244 2245 if (AR_SREV_9285(ah)) { 2246 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; 2247 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; 2248 } else { 2249 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; 2250 } 2251 } else { 2252 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; 2253 } 2254 2255 if (AR_SREV_9300_20_OR_LATER(ah)) { 2256 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC | 2257 ATH9K_HW_CAP_FASTCLOCK; 2258 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2259 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; 2260 pCap->rx_status_len = sizeof(struct ar9003_rxs); 2261 pCap->tx_desc_len = sizeof(struct ar9003_txc); 2262 pCap->txs_len = sizeof(struct ar9003_txs); 2263 if (!ah->config.paprd_disable && 2264 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) 2265 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2266 } else { 2267 pCap->tx_desc_len = sizeof(struct ath_desc); 2268 if (AR_SREV_9280_20(ah) && 2269 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <= 2270 AR5416_EEP_MINOR_VER_16) || 2271 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G))) 2272 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2273 } 2274 2275 if (AR_SREV_9300_20_OR_LATER(ah)) 2276 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; 2277 2278 if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah)) 2279 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; 2280 2281 return 0; 2282} 2283 2284/****************************/ 2285/* GPIO / RFKILL / Antennae */ 2286/****************************/ 2287 2288static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, 2289 u32 gpio, u32 type) 2290{ 2291 int addr; 2292 u32 gpio_shift, tmp; 2293 2294 if (gpio > 11) 2295 addr = AR_GPIO_OUTPUT_MUX3; 2296 else if (gpio > 5) 2297 addr = AR_GPIO_OUTPUT_MUX2; 2298 else 2299 addr = AR_GPIO_OUTPUT_MUX1; 2300 2301 gpio_shift = (gpio % 6) * 5; 2302 2303 if (AR_SREV_9280_20_OR_LATER(ah) 2304 || (addr != AR_GPIO_OUTPUT_MUX1)) { 2305 REG_RMW(ah, addr, (type << gpio_shift), 2306 (0x1f << gpio_shift)); 2307 } else { 2308 tmp = REG_READ(ah, addr); 2309 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); 2310 tmp &= ~(0x1f << gpio_shift); 2311 tmp |= (type << gpio_shift); 2312 REG_WRITE(ah, addr, tmp); 2313 } 2314} 2315 2316void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) 2317{ 2318 u32 gpio_shift; 2319 2320 BUG_ON(gpio >= ah->caps.num_gpio_pins); 2321 2322 if (AR_DEVID_7010(ah)) { 2323 gpio_shift = gpio; 2324 REG_RMW(ah, AR7010_GPIO_OE, 2325 (AR7010_GPIO_OE_AS_INPUT << gpio_shift), 2326 (AR7010_GPIO_OE_MASK << gpio_shift)); 2327 return; 2328 } 2329 2330 gpio_shift = gpio << 1; 2331 REG_RMW(ah, 2332 AR_GPIO_OE_OUT, 2333 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), 2334 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2335} 2336EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); 2337 2338u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 2339{ 2340#define MS_REG_READ(x, y) \ 2341 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) 2342 2343 if (gpio >= ah->caps.num_gpio_pins) 2344 return 0xffffffff; 2345 2346 if (AR_DEVID_7010(ah)) { 2347 u32 val; 2348 val = REG_READ(ah, AR7010_GPIO_IN); 2349 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; 2350 } else if (AR_SREV_9300_20_OR_LATER(ah)) 2351 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & 2352 AR_GPIO_BIT(gpio)) != 0; 2353 else if (AR_SREV_9271(ah)) 2354 return MS_REG_READ(AR9271, gpio) != 0; 2355 else if (AR_SREV_9287_10_OR_LATER(ah)) 2356 return MS_REG_READ(AR9287, gpio) != 0; 2357 else if (AR_SREV_9285_10_OR_LATER(ah)) 2358 return MS_REG_READ(AR9285, gpio) != 0; 2359 else if (AR_SREV_9280_10_OR_LATER(ah)) 2360 return MS_REG_READ(AR928X, gpio) != 0; 2361 else 2362 return MS_REG_READ(AR, gpio) != 0; 2363} 2364EXPORT_SYMBOL(ath9k_hw_gpio_get); 2365 2366void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, 2367 u32 ah_signal_type) 2368{ 2369 u32 gpio_shift; 2370 2371 if (AR_DEVID_7010(ah)) { 2372 gpio_shift = gpio; 2373 REG_RMW(ah, AR7010_GPIO_OE, 2374 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), 2375 (AR7010_GPIO_OE_MASK << gpio_shift)); 2376 return; 2377 } 2378 2379 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); 2380 gpio_shift = 2 * gpio; 2381 REG_RMW(ah, 2382 AR_GPIO_OE_OUT, 2383 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), 2384 (AR_GPIO_OE_OUT_DRV << gpio_shift)); 2385} 2386EXPORT_SYMBOL(ath9k_hw_cfg_output); 2387 2388void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) 2389{ 2390 if (AR_DEVID_7010(ah)) { 2391 val = val ? 0 : 1; 2392 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), 2393 AR_GPIO_BIT(gpio)); 2394 return; 2395 } 2396 2397 if (AR_SREV_9271(ah)) 2398 val = ~val; 2399 2400 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), 2401 AR_GPIO_BIT(gpio)); 2402} 2403EXPORT_SYMBOL(ath9k_hw_set_gpio); 2404 2405u32 ath9k_hw_getdefantenna(struct ath_hw *ah) 2406{ 2407 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; 2408} 2409EXPORT_SYMBOL(ath9k_hw_getdefantenna); 2410 2411void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) 2412{ 2413 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 2414} 2415EXPORT_SYMBOL(ath9k_hw_setantenna); 2416 2417/*********************/ 2418/* General Operation */ 2419/*********************/ 2420 2421u32 ath9k_hw_getrxfilter(struct ath_hw *ah) 2422{ 2423 u32 bits = REG_READ(ah, AR_RX_FILTER); 2424 u32 phybits = REG_READ(ah, AR_PHY_ERR); 2425 2426 if (phybits & AR_PHY_ERR_RADAR) 2427 bits |= ATH9K_RX_FILTER_PHYRADAR; 2428 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) 2429 bits |= ATH9K_RX_FILTER_PHYERR; 2430 2431 return bits; 2432} 2433EXPORT_SYMBOL(ath9k_hw_getrxfilter); 2434 2435void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) 2436{ 2437 u32 phybits; 2438 2439 ENABLE_REGWRITE_BUFFER(ah); 2440 2441 REG_WRITE(ah, AR_RX_FILTER, bits); 2442 2443 phybits = 0; 2444 if (bits & ATH9K_RX_FILTER_PHYRADAR) 2445 phybits |= AR_PHY_ERR_RADAR; 2446 if (bits & ATH9K_RX_FILTER_PHYERR) 2447 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; 2448 REG_WRITE(ah, AR_PHY_ERR, phybits); 2449 2450 if (phybits) 2451 REG_WRITE(ah, AR_RXCFG, 2452 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); 2453 else 2454 REG_WRITE(ah, AR_RXCFG, 2455 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); 2456 2457 REGWRITE_BUFFER_FLUSH(ah); 2458 DISABLE_REGWRITE_BUFFER(ah); 2459} 2460EXPORT_SYMBOL(ath9k_hw_setrxfilter); 2461 2462bool ath9k_hw_phy_disable(struct ath_hw *ah) 2463{ 2464 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) 2465 return false; 2466 2467 ath9k_hw_init_pll(ah, NULL); 2468 return true; 2469} 2470EXPORT_SYMBOL(ath9k_hw_phy_disable); 2471 2472bool ath9k_hw_disable(struct ath_hw *ah) 2473{ 2474 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) 2475 return false; 2476 2477 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) 2478 return false; 2479 2480 ath9k_hw_init_pll(ah, NULL); 2481 return true; 2482} 2483EXPORT_SYMBOL(ath9k_hw_disable); 2484 2485void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) 2486{ 2487 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2488 struct ath9k_channel *chan = ah->curchan; 2489 struct ieee80211_channel *channel = chan->chan; 2490 2491 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); 2492 2493 ah->eep_ops->set_txpower(ah, chan, 2494 ath9k_regd_get_ctl(regulatory, chan), 2495 channel->max_antenna_gain * 2, 2496 channel->max_power * 2, 2497 min((u32) MAX_RATE_POWER, 2498 (u32) regulatory->power_limit)); 2499} 2500EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); 2501 2502void ath9k_hw_setopmode(struct ath_hw *ah) 2503{ 2504 ath9k_hw_set_operating_mode(ah, ah->opmode); 2505} 2506EXPORT_SYMBOL(ath9k_hw_setopmode); 2507 2508void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) 2509{ 2510 REG_WRITE(ah, AR_MCAST_FIL0, filter0); 2511 REG_WRITE(ah, AR_MCAST_FIL1, filter1); 2512} 2513EXPORT_SYMBOL(ath9k_hw_setmcastfilter); 2514 2515void ath9k_hw_write_associd(struct ath_hw *ah) 2516{ 2517 struct ath_common *common = ath9k_hw_common(ah); 2518 2519 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); 2520 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | 2521 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); 2522} 2523EXPORT_SYMBOL(ath9k_hw_write_associd); 2524 2525#define ATH9K_MAX_TSF_READ 10 2526 2527u64 ath9k_hw_gettsf64(struct ath_hw *ah) 2528{ 2529 u32 tsf_lower, tsf_upper1, tsf_upper2; 2530 int i; 2531 2532 tsf_upper1 = REG_READ(ah, AR_TSF_U32); 2533 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { 2534 tsf_lower = REG_READ(ah, AR_TSF_L32); 2535 tsf_upper2 = REG_READ(ah, AR_TSF_U32); 2536 if (tsf_upper2 == tsf_upper1) 2537 break; 2538 tsf_upper1 = tsf_upper2; 2539 } 2540 2541 WARN_ON( i == ATH9K_MAX_TSF_READ ); 2542 2543 return (((u64)tsf_upper1 << 32) | tsf_lower); 2544} 2545EXPORT_SYMBOL(ath9k_hw_gettsf64); 2546 2547void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) 2548{ 2549 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); 2550 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); 2551} 2552EXPORT_SYMBOL(ath9k_hw_settsf64); 2553 2554void ath9k_hw_reset_tsf(struct ath_hw *ah) 2555{ 2556 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 2557 AH_TSF_WRITE_TIMEOUT)) 2558 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, 2559 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 2560 2561 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 2562} 2563EXPORT_SYMBOL(ath9k_hw_reset_tsf); 2564 2565void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) 2566{ 2567 if (setting) 2568 ah->misc_mode |= AR_PCU_TX_ADD_TSF; 2569 else 2570 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; 2571} 2572EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); 2573 2574void ath9k_hw_set11nmac2040(struct ath_hw *ah) 2575{ 2576 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 2577 u32 macmode; 2578 2579 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) 2580 macmode = AR_2040_JOINED_RX_CLEAR; 2581 else 2582 macmode = 0; 2583 2584 REG_WRITE(ah, AR_2040_MODE, macmode); 2585} 2586 2587/* HW Generic timers configuration */ 2588 2589static const struct ath_gen_timer_configuration gen_tmr_configuration[] = 2590{ 2591 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2592 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2593 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2594 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2595 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2596 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2597 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2598 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 2599 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, 2600 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, 2601 AR_NDP2_TIMER_MODE, 0x0002}, 2602 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, 2603 AR_NDP2_TIMER_MODE, 0x0004}, 2604 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, 2605 AR_NDP2_TIMER_MODE, 0x0008}, 2606 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, 2607 AR_NDP2_TIMER_MODE, 0x0010}, 2608 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, 2609 AR_NDP2_TIMER_MODE, 0x0020}, 2610 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, 2611 AR_NDP2_TIMER_MODE, 0x0040}, 2612 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, 2613 AR_NDP2_TIMER_MODE, 0x0080} 2614}; 2615 2616/* HW generic timer primitives */ 2617 2618/* compute and clear index of rightmost 1 */ 2619static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) 2620{ 2621 u32 b; 2622 2623 b = *mask; 2624 b &= (0-b); 2625 *mask &= ~b; 2626 b *= debruijn32; 2627 b >>= 27; 2628 2629 return timer_table->gen_timer_index[b]; 2630} 2631 2632u32 ath9k_hw_gettsf32(struct ath_hw *ah) 2633{ 2634 return REG_READ(ah, AR_TSF_L32); 2635} 2636EXPORT_SYMBOL(ath9k_hw_gettsf32); 2637 2638struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, 2639 void (*trigger)(void *), 2640 void (*overflow)(void *), 2641 void *arg, 2642 u8 timer_index) 2643{ 2644 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2645 struct ath_gen_timer *timer; 2646 2647 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); 2648 2649 if (timer == NULL) { 2650 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 2651 "Failed to allocate memory" 2652 "for hw timer[%d]\n", timer_index); 2653 return NULL; 2654 } 2655 2656 /* allocate a hardware generic timer slot */ 2657 timer_table->timers[timer_index] = timer; 2658 timer->index = timer_index; 2659 timer->trigger = trigger; 2660 timer->overflow = overflow; 2661 timer->arg = arg; 2662 2663 return timer; 2664} 2665EXPORT_SYMBOL(ath_gen_timer_alloc); 2666 2667void ath9k_hw_gen_timer_start(struct ath_hw *ah, 2668 struct ath_gen_timer *timer, 2669 u32 timer_next, 2670 u32 timer_period) 2671{ 2672 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2673 u32 tsf; 2674 2675 BUG_ON(!timer_period); 2676 2677 set_bit(timer->index, &timer_table->timer_mask.timer_bits); 2678 2679 tsf = ath9k_hw_gettsf32(ah); 2680 2681 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, 2682 "curent tsf %x period %x" 2683 "timer_next %x\n", tsf, timer_period, timer_next); 2684 2685 /* 2686 * Pull timer_next forward if the current TSF already passed it 2687 * because of software latency 2688 */ 2689 if (timer_next < tsf) 2690 timer_next = tsf + timer_period; 2691 2692 /* 2693 * Program generic timer registers 2694 */ 2695 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, 2696 timer_next); 2697 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, 2698 timer_period); 2699 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2700 gen_tmr_configuration[timer->index].mode_mask); 2701 2702 /* Enable both trigger and thresh interrupt masks */ 2703 REG_SET_BIT(ah, AR_IMR_S5, 2704 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2705 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2706} 2707EXPORT_SYMBOL(ath9k_hw_gen_timer_start); 2708 2709void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) 2710{ 2711 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2712 2713 if ((timer->index < AR_FIRST_NDP_TIMER) || 2714 (timer->index >= ATH_MAX_GEN_TIMER)) { 2715 return; 2716 } 2717 2718 /* Clear generic timer enable bits. */ 2719 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, 2720 gen_tmr_configuration[timer->index].mode_mask); 2721 2722 /* Disable both trigger and thresh interrupt masks */ 2723 REG_CLR_BIT(ah, AR_IMR_S5, 2724 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | 2725 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); 2726 2727 clear_bit(timer->index, &timer_table->timer_mask.timer_bits); 2728} 2729EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); 2730 2731void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) 2732{ 2733 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2734 2735 /* free the hardware generic timer slot */ 2736 timer_table->timers[timer->index] = NULL; 2737 kfree(timer); 2738} 2739EXPORT_SYMBOL(ath_gen_timer_free); 2740 2741/* 2742 * Generic Timer Interrupts handling 2743 */ 2744void ath_gen_timer_isr(struct ath_hw *ah) 2745{ 2746 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; 2747 struct ath_gen_timer *timer; 2748 struct ath_common *common = ath9k_hw_common(ah); 2749 u32 trigger_mask, thresh_mask, index; 2750 2751 /* get hardware generic timer interrupt status */ 2752 trigger_mask = ah->intr_gen_timer_trigger; 2753 thresh_mask = ah->intr_gen_timer_thresh; 2754 trigger_mask &= timer_table->timer_mask.val; 2755 thresh_mask &= timer_table->timer_mask.val; 2756 2757 trigger_mask &= ~thresh_mask; 2758 2759 while (thresh_mask) { 2760 index = rightmost_index(timer_table, &thresh_mask); 2761 timer = timer_table->timers[index]; 2762 BUG_ON(!timer); 2763 ath_print(common, ATH_DBG_HWTIMER, 2764 "TSF overflow for Gen timer %d\n", index); 2765 timer->overflow(timer->arg); 2766 } 2767 2768 while (trigger_mask) { 2769 index = rightmost_index(timer_table, &trigger_mask); 2770 timer = timer_table->timers[index]; 2771 BUG_ON(!timer); 2772 ath_print(common, ATH_DBG_HWTIMER, 2773 "Gen timer[%d] trigger\n", index); 2774 timer->trigger(timer->arg); 2775 } 2776} 2777EXPORT_SYMBOL(ath_gen_timer_isr); 2778 2779/********/ 2780/* HTC */ 2781/********/ 2782 2783void ath9k_hw_htc_resetinit(struct ath_hw *ah) 2784{ 2785 ah->htc_reset_init = true; 2786} 2787EXPORT_SYMBOL(ath9k_hw_htc_resetinit); 2788 2789static struct { 2790 u32 version; 2791 const char * name; 2792} ath_mac_bb_names[] = { 2793 /* Devices with external radios */ 2794 { AR_SREV_VERSION_5416_PCI, "5416" }, 2795 { AR_SREV_VERSION_5416_PCIE, "5418" }, 2796 { AR_SREV_VERSION_9100, "9100" }, 2797 { AR_SREV_VERSION_9160, "9160" }, 2798 /* Single-chip solutions */ 2799 { AR_SREV_VERSION_9280, "9280" }, 2800 { AR_SREV_VERSION_9285, "9285" }, 2801 { AR_SREV_VERSION_9287, "9287" }, 2802 { AR_SREV_VERSION_9271, "9271" }, 2803 { AR_SREV_VERSION_9300, "9300" }, 2804}; 2805 2806/* For devices with external radios */ 2807static struct { 2808 u16 version; 2809 const char * name; 2810} ath_rf_names[] = { 2811 { 0, "5133" }, 2812 { AR_RAD5133_SREV_MAJOR, "5133" }, 2813 { AR_RAD5122_SREV_MAJOR, "5122" }, 2814 { AR_RAD2133_SREV_MAJOR, "2133" }, 2815 { AR_RAD2122_SREV_MAJOR, "2122" } 2816}; 2817 2818/* 2819 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 2820 */ 2821static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) 2822{ 2823 int i; 2824 2825 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { 2826 if (ath_mac_bb_names[i].version == mac_bb_version) { 2827 return ath_mac_bb_names[i].name; 2828 } 2829 } 2830 2831 return "????"; 2832} 2833 2834/* 2835 * Return the RF name. "????" is returned if the RF is unknown. 2836 * Used for devices with external radios. 2837 */ 2838static const char *ath9k_hw_rf_name(u16 rf_version) 2839{ 2840 int i; 2841 2842 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { 2843 if (ath_rf_names[i].version == rf_version) { 2844 return ath_rf_names[i].name; 2845 } 2846 } 2847 2848 return "????"; 2849} 2850 2851void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) 2852{ 2853 int used; 2854 2855 /* chipsets >= AR9280 are single-chip */ 2856 if (AR_SREV_9280_10_OR_LATER(ah)) { 2857 used = snprintf(hw_name, len, 2858 "Atheros AR%s Rev:%x", 2859 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2860 ah->hw_version.macRev); 2861 } 2862 else { 2863 used = snprintf(hw_name, len, 2864 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", 2865 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), 2866 ah->hw_version.macRev, 2867 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & 2868 AR_RADIO_SREV_MAJOR)), 2869 ah->hw_version.phyRev); 2870 } 2871 2872 hw_name[used] = '\0'; 2873} 2874EXPORT_SYMBOL(ath9k_hw_name); 2875