1/* 2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver 3 * 4 * Copyright 2004 Antonino Daplas <adaplas@pol.net> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file COPYING in the main directory of this archive 8 * for more details. 9 * 10 */ 11 12#include <linux/module.h> 13#include <linux/kernel.h> 14#include <linux/errno.h> 15#include <linux/string.h> 16#include <linux/mm.h> 17#include <linux/slab.h> 18#include <linux/delay.h> 19#include <linux/fb.h> 20#include <linux/init.h> 21#include <linux/pci.h> 22#include <linux/console.h> 23#include <linux/backlight.h> 24#ifdef CONFIG_MTRR 25#include <asm/mtrr.h> 26#endif 27#ifdef CONFIG_PPC_OF 28#include <asm/prom.h> 29#include <asm/pci-bridge.h> 30#endif 31#ifdef CONFIG_BOOTX_TEXT 32#include <asm/btext.h> 33#endif 34 35#include "nv_local.h" 36#include "nv_type.h" 37#include "nv_proto.h" 38#include "nv_dma.h" 39 40#ifdef CONFIG_FB_NVIDIA_DEBUG 41#define NVTRACE printk 42#else 43#define NVTRACE if (0) printk 44#endif 45 46#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__) 47#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__) 48 49#ifdef CONFIG_FB_NVIDIA_DEBUG 50#define assert(expr) \ 51 if (!(expr)) { \ 52 printk( "Assertion failed! %s,%s,%s,line=%d\n",\ 53 #expr,__FILE__,__func__,__LINE__); \ 54 BUG(); \ 55 } 56#else 57#define assert(expr) 58#endif 59 60#define PFX "nvidiafb: " 61 62/* HW cursor parameters */ 63#define MAX_CURS 32 64 65static struct pci_device_id nvidiafb_pci_tbl[] = { 66 {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 67 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0}, 68 { 0, } 69}; 70MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl); 71 72/* command line data, set in nvidiafb_setup() */ 73static int flatpanel __devinitdata = -1; /* Autodetect later */ 74static int fpdither __devinitdata = -1; 75static int forceCRTC __devinitdata = -1; 76static int hwcur __devinitdata = 0; 77static int noaccel __devinitdata = 0; 78static int noscale __devinitdata = 0; 79static int paneltweak __devinitdata = 0; 80static int vram __devinitdata = 0; 81static int bpp __devinitdata = 8; 82static int reverse_i2c __devinitdata; 83#ifdef CONFIG_MTRR 84static int nomtrr __devinitdata = 0; 85#endif 86#ifdef CONFIG_PMAC_BACKLIGHT 87static int backlight __devinitdata = 1; 88#else 89static int backlight __devinitdata = 0; 90#endif 91 92static char *mode_option __devinitdata = NULL; 93 94static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = { 95 .type = FB_TYPE_PACKED_PIXELS, 96 .xpanstep = 8, 97 .ypanstep = 1, 98}; 99 100static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = { 101 .xres = 640, 102 .yres = 480, 103 .xres_virtual = 640, 104 .yres_virtual = 480, 105 .bits_per_pixel = 8, 106 .red = {0, 8, 0}, 107 .green = {0, 8, 0}, 108 .blue = {0, 8, 0}, 109 .transp = {0, 0, 0}, 110 .activate = FB_ACTIVATE_NOW, 111 .height = -1, 112 .width = -1, 113 .pixclock = 39721, 114 .left_margin = 40, 115 .right_margin = 24, 116 .upper_margin = 32, 117 .lower_margin = 11, 118 .hsync_len = 96, 119 .vsync_len = 2, 120 .vmode = FB_VMODE_NONINTERLACED 121}; 122 123static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8, 124 u16 bg, u16 fg, u32 w, u32 h) 125{ 126 u32 *data = (u32 *) data8; 127 int i, j, k = 0; 128 u32 b, tmp; 129 130 w = (w + 1) & ~1; 131 132 for (i = 0; i < h; i++) { 133 b = *data++; 134 reverse_order(&b); 135 136 for (j = 0; j < w / 2; j++) { 137 tmp = 0; 138#if defined(__BIG_ENDIAN) 139 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; 140 b <<= 1; 141 tmp |= (b & (1 << 31)) ? fg : bg; 142 b <<= 1; 143#else 144 tmp = (b & 1) ? fg : bg; 145 b >>= 1; 146 tmp |= (b & 1) ? fg << 16 : bg << 16; 147 b >>= 1; 148#endif 149 NV_WR32(&par->CURSOR[k++], 0, tmp); 150 } 151 k += (MAX_CURS - w) / 2; 152 } 153} 154 155static void nvidia_write_clut(struct nvidia_par *par, 156 u8 regnum, u8 red, u8 green, u8 blue) 157{ 158 NVWriteDacMask(par, 0xff); 159 NVWriteDacWriteAddr(par, regnum); 160 NVWriteDacData(par, red); 161 NVWriteDacData(par, green); 162 NVWriteDacData(par, blue); 163} 164 165static void nvidia_read_clut(struct nvidia_par *par, 166 u8 regnum, u8 * red, u8 * green, u8 * blue) 167{ 168 NVWriteDacMask(par, 0xff); 169 NVWriteDacReadAddr(par, regnum); 170 *red = NVReadDacData(par); 171 *green = NVReadDacData(par); 172 *blue = NVReadDacData(par); 173} 174 175static int nvidia_panel_tweak(struct nvidia_par *par, 176 struct _riva_hw_state *state) 177{ 178 int tweak = 0; 179 180 if (par->paneltweak) { 181 tweak = par->paneltweak; 182 } else { 183 /* begin flat panel hacks */ 184 /* This is unfortunate, but some chips need this register 185 tweaked or else you get artifacts where adjacent pixels are 186 swapped. There are no hard rules for what to set here so all 187 we can do is experiment and apply hacks. */ 188 189 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) { 190 tweak = -1; 191 } 192 193 if((par->Chipset & 0xfff0) == 0x0310) { 194 tweak = 1; 195 } 196 /* end flat panel hacks */ 197 } 198 199 return tweak; 200} 201 202static void nvidia_screen_off(struct nvidia_par *par, int on) 203{ 204 unsigned char tmp; 205 206 if (on) { 207 /* 208 * Turn off screen and disable sequencer. 209 */ 210 tmp = NVReadSeq(par, 0x01); 211 212 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */ 213 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */ 214 } else { 215 /* 216 * Reenable sequencer, then turn on screen. 217 */ 218 219 tmp = NVReadSeq(par, 0x01); 220 221 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */ 222 NVWriteSeq(par, 0x00, 0x03); /* End Reset */ 223 } 224} 225 226static void nvidia_save_vga(struct nvidia_par *par, 227 struct _riva_hw_state *state) 228{ 229 int i; 230 231 NVTRACE_ENTER(); 232 NVLockUnlock(par, 0); 233 234 NVUnloadStateExt(par, state); 235 236 state->misc_output = NVReadMiscOut(par); 237 238 for (i = 0; i < NUM_CRT_REGS; i++) 239 state->crtc[i] = NVReadCrtc(par, i); 240 241 for (i = 0; i < NUM_ATC_REGS; i++) 242 state->attr[i] = NVReadAttr(par, i); 243 244 for (i = 0; i < NUM_GRC_REGS; i++) 245 state->gra[i] = NVReadGr(par, i); 246 247 for (i = 0; i < NUM_SEQ_REGS; i++) 248 state->seq[i] = NVReadSeq(par, i); 249 NVTRACE_LEAVE(); 250} 251 252#undef DUMP_REG 253 254static void nvidia_write_regs(struct nvidia_par *par, 255 struct _riva_hw_state *state) 256{ 257 int i; 258 259 NVTRACE_ENTER(); 260 261 NVLoadStateExt(par, state); 262 263 NVWriteMiscOut(par, state->misc_output); 264 265 for (i = 1; i < NUM_SEQ_REGS; i++) { 266#ifdef DUMP_REG 267 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]); 268#endif 269 NVWriteSeq(par, i, state->seq[i]); 270 } 271 272 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */ 273 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80); 274 275 for (i = 0; i < NUM_CRT_REGS; i++) { 276 switch (i) { 277 case 0x19: 278 case 0x20 ... 0x40: 279 break; 280 default: 281#ifdef DUMP_REG 282 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]); 283#endif 284 NVWriteCrtc(par, i, state->crtc[i]); 285 } 286 } 287 288 for (i = 0; i < NUM_GRC_REGS; i++) { 289#ifdef DUMP_REG 290 printk(" GRA[%02x] = %08x\n", i, state->gra[i]); 291#endif 292 NVWriteGr(par, i, state->gra[i]); 293 } 294 295 for (i = 0; i < NUM_ATC_REGS; i++) { 296#ifdef DUMP_REG 297 printk("ATTR[%02x] = %08x\n", i, state->attr[i]); 298#endif 299 NVWriteAttr(par, i, state->attr[i]); 300 } 301 302 NVTRACE_LEAVE(); 303} 304 305static int nvidia_calc_regs(struct fb_info *info) 306{ 307 struct nvidia_par *par = info->par; 308 struct _riva_hw_state *state = &par->ModeReg; 309 int i, depth = fb_get_color_depth(&info->var, &info->fix); 310 int h_display = info->var.xres / 8 - 1; 311 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1; 312 int h_end = (info->var.xres + info->var.right_margin + 313 info->var.hsync_len) / 8 - 1; 314 int h_total = (info->var.xres + info->var.right_margin + 315 info->var.hsync_len + info->var.left_margin) / 8 - 5; 316 int h_blank_s = h_display; 317 int h_blank_e = h_total + 4; 318 int v_display = info->var.yres - 1; 319 int v_start = info->var.yres + info->var.lower_margin - 1; 320 int v_end = (info->var.yres + info->var.lower_margin + 321 info->var.vsync_len) - 1; 322 int v_total = (info->var.yres + info->var.lower_margin + 323 info->var.vsync_len + info->var.upper_margin) - 2; 324 int v_blank_s = v_display; 325 int v_blank_e = v_total + 1; 326 327 /* 328 * Set all CRTC values. 329 */ 330 331 if (info->var.vmode & FB_VMODE_INTERLACED) 332 v_total |= 1; 333 334 if (par->FlatPanel == 1) { 335 v_start = v_total - 3; 336 v_end = v_total - 2; 337 v_blank_s = v_start; 338 h_start = h_total - 5; 339 h_end = h_total - 2; 340 h_blank_e = h_total + 4; 341 } 342 343 state->crtc[0x0] = Set8Bits(h_total); 344 state->crtc[0x1] = Set8Bits(h_display); 345 state->crtc[0x2] = Set8Bits(h_blank_s); 346 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0) 347 | SetBit(7); 348 state->crtc[0x4] = Set8Bits(h_start); 349 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7) 350 | SetBitField(h_end, 4: 0, 4:0); 351 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0); 352 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0) 353 | SetBitField(v_display, 8: 8, 1:1) 354 | SetBitField(v_start, 8: 8, 2:2) 355 | SetBitField(v_blank_s, 8: 8, 3:3) 356 | SetBit(4) 357 | SetBitField(v_total, 9: 9, 5:5) 358 | SetBitField(v_display, 9: 9, 6:6) 359 | SetBitField(v_start, 9: 9, 7:7); 360 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5) 361 | SetBit(6) 362 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00); 363 state->crtc[0x10] = Set8Bits(v_start); 364 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5); 365 state->crtc[0x12] = Set8Bits(v_display); 366 state->crtc[0x13] = ((info->var.xres_virtual / 8) * 367 (info->var.bits_per_pixel / 8)); 368 state->crtc[0x15] = Set8Bits(v_blank_s); 369 state->crtc[0x16] = Set8Bits(v_blank_e); 370 371 state->attr[0x10] = 0x01; 372 373 if (par->Television) 374 state->attr[0x11] = 0x00; 375 376 state->screen = SetBitField(h_blank_e, 6: 6, 4:4) 377 | SetBitField(v_blank_s, 10: 10, 3:3) 378 | SetBitField(v_start, 10: 10, 2:2) 379 | SetBitField(v_display, 10: 10, 1:1) 380 | SetBitField(v_total, 10: 10, 0:0); 381 382 state->horiz = SetBitField(h_total, 8: 8, 0:0) 383 | SetBitField(h_display, 8: 8, 1:1) 384 | SetBitField(h_blank_s, 8: 8, 2:2) 385 | SetBitField(h_start, 8: 8, 3:3); 386 387 state->extra = SetBitField(v_total, 11: 11, 0:0) 388 | SetBitField(v_display, 11: 11, 2:2) 389 | SetBitField(v_start, 11: 11, 4:4) 390 | SetBitField(v_blank_s, 11: 11, 6:6); 391 392 if (info->var.vmode & FB_VMODE_INTERLACED) { 393 h_total = (h_total >> 1) & ~1; 394 state->interlace = Set8Bits(h_total); 395 state->horiz |= SetBitField(h_total, 8: 8, 4:4); 396 } else { 397 state->interlace = 0xff; /* interlace off */ 398 } 399 400 /* 401 * Calculate the extended registers. 402 */ 403 404 if (depth < 24) 405 i = depth; 406 else 407 i = 32; 408 409 if (par->Architecture >= NV_ARCH_10) 410 par->CURSOR = (volatile u32 __iomem *)(info->screen_base + 411 par->CursorStart); 412 413 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 414 state->misc_output &= ~0x40; 415 else 416 state->misc_output |= 0x40; 417 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 418 state->misc_output &= ~0x80; 419 else 420 state->misc_output |= 0x80; 421 422 NVCalcStateExt(par, state, i, info->var.xres_virtual, 423 info->var.xres, info->var.yres_virtual, 424 1000000000 / info->var.pixclock, info->var.vmode); 425 426 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff; 427 if (par->FlatPanel == 1) { 428 state->pixel |= (1 << 7); 429 430 if (!par->fpScaler || (par->fpWidth <= info->var.xres) 431 || (par->fpHeight <= info->var.yres)) { 432 state->scale |= (1 << 8); 433 } 434 435 if (!par->crtcSync_read) { 436 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828); 437 par->crtcSync_read = 1; 438 } 439 440 par->PanelTweak = nvidia_panel_tweak(par, state); 441 } 442 443 state->vpll = state->pll; 444 state->vpll2 = state->pll; 445 state->vpllB = state->pllB; 446 state->vpll2B = state->pllB; 447 448 VGA_WR08(par->PCIO, 0x03D4, 0x1C); 449 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5); 450 451 if (par->CRTCnumber) { 452 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000; 453 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000; 454 state->crtcOwner = 3; 455 state->pllsel |= 0x20000800; 456 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508); 457 if (par->twoStagePLL) 458 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578); 459 } else if (par->twoHeads) { 460 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000; 461 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000; 462 state->crtcOwner = 0; 463 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); 464 if (par->twoStagePLL) 465 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); 466 } 467 468 state->cursorConfig = 0x00000100; 469 470 if (info->var.vmode & FB_VMODE_DOUBLE) 471 state->cursorConfig |= (1 << 4); 472 473 if (par->alphaCursor) { 474 if ((par->Chipset & 0x0ff0) != 0x0110) 475 state->cursorConfig |= 0x04011000; 476 else 477 state->cursorConfig |= 0x14011000; 478 state->general |= (1 << 29); 479 } else 480 state->cursorConfig |= 0x02000000; 481 482 if (par->twoHeads) { 483 if ((par->Chipset & 0x0ff0) == 0x0110) { 484 state->dither = NV_RD32(par->PRAMDAC, 0x0528) & 485 ~0x00010000; 486 if (par->FPDither) 487 state->dither |= 0x00010000; 488 } else { 489 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1; 490 if (par->FPDither) 491 state->dither |= 1; 492 } 493 } 494 495 state->timingH = 0; 496 state->timingV = 0; 497 state->displayV = info->var.xres; 498 499 return 0; 500} 501 502static void nvidia_init_vga(struct fb_info *info) 503{ 504 struct nvidia_par *par = info->par; 505 struct _riva_hw_state *state = &par->ModeReg; 506 int i; 507 508 for (i = 0; i < 0x10; i++) 509 state->attr[i] = i; 510 state->attr[0x10] = 0x41; 511 state->attr[0x11] = 0xff; 512 state->attr[0x12] = 0x0f; 513 state->attr[0x13] = 0x00; 514 state->attr[0x14] = 0x00; 515 516 memset(state->crtc, 0x00, NUM_CRT_REGS); 517 state->crtc[0x0a] = 0x20; 518 state->crtc[0x17] = 0xe3; 519 state->crtc[0x18] = 0xff; 520 state->crtc[0x28] = 0x40; 521 522 memset(state->gra, 0x00, NUM_GRC_REGS); 523 state->gra[0x05] = 0x40; 524 state->gra[0x06] = 0x05; 525 state->gra[0x07] = 0x0f; 526 state->gra[0x08] = 0xff; 527 528 state->seq[0x00] = 0x03; 529 state->seq[0x01] = 0x01; 530 state->seq[0x02] = 0x0f; 531 state->seq[0x03] = 0x00; 532 state->seq[0x04] = 0x0e; 533 534 state->misc_output = 0xeb; 535} 536 537static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor) 538{ 539 struct nvidia_par *par = info->par; 540 u8 data[MAX_CURS * MAX_CURS / 8]; 541 int i, set = cursor->set; 542 u16 fg, bg; 543 544 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) 545 return -ENXIO; 546 547 NVShowHideCursor(par, 0); 548 549 if (par->cursor_reset) { 550 set = FB_CUR_SETALL; 551 par->cursor_reset = 0; 552 } 553 554 if (set & FB_CUR_SETSIZE) 555 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2); 556 557 if (set & FB_CUR_SETPOS) { 558 u32 xx, yy, temp; 559 560 yy = cursor->image.dy - info->var.yoffset; 561 xx = cursor->image.dx - info->var.xoffset; 562 temp = xx & 0xFFFF; 563 temp |= yy << 16; 564 565 NV_WR32(par->PRAMDAC, 0x0000300, temp); 566 } 567 568 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { 569 u32 bg_idx = cursor->image.bg_color; 570 u32 fg_idx = cursor->image.fg_color; 571 u32 s_pitch = (cursor->image.width + 7) >> 3; 572 u32 d_pitch = MAX_CURS / 8; 573 u8 *dat = (u8 *) cursor->image.data; 574 u8 *msk = (u8 *) cursor->mask; 575 u8 *src; 576 577 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC); 578 579 if (src) { 580 switch (cursor->rop) { 581 case ROP_XOR: 582 for (i = 0; i < s_pitch * cursor->image.height; i++) 583 src[i] = dat[i] ^ msk[i]; 584 break; 585 case ROP_COPY: 586 default: 587 for (i = 0; i < s_pitch * cursor->image.height; i++) 588 src[i] = dat[i] & msk[i]; 589 break; 590 } 591 592 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, 593 cursor->image.height); 594 595 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | 596 ((info->cmap.green[bg_idx] & 0xf8) << 2) | 597 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15; 598 599 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | 600 ((info->cmap.green[fg_idx] & 0xf8) << 2) | 601 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15; 602 603 NVLockUnlock(par, 0); 604 605 nvidiafb_load_cursor_image(par, data, bg, fg, 606 cursor->image.width, 607 cursor->image.height); 608 kfree(src); 609 } 610 } 611 612 if (cursor->enable) 613 NVShowHideCursor(par, 1); 614 615 return 0; 616} 617 618static int nvidiafb_set_par(struct fb_info *info) 619{ 620 struct nvidia_par *par = info->par; 621 622 NVTRACE_ENTER(); 623 624 NVLockUnlock(par, 1); 625 if (!par->FlatPanel || !par->twoHeads) 626 par->FPDither = 0; 627 628 if (par->FPDither < 0) { 629 if ((par->Chipset & 0x0ff0) == 0x0110) 630 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528) 631 & 0x00010000); 632 else 633 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1); 634 printk(KERN_INFO PFX "Flat panel dithering %s\n", 635 par->FPDither ? "enabled" : "disabled"); 636 } 637 638 info->fix.visual = (info->var.bits_per_pixel == 8) ? 639 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 640 641 nvidia_init_vga(info); 642 nvidia_calc_regs(info); 643 644 NVLockUnlock(par, 0); 645 if (par->twoHeads) { 646 VGA_WR08(par->PCIO, 0x03D4, 0x44); 647 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner); 648 NVLockUnlock(par, 0); 649 } 650 651 nvidia_screen_off(par, 1); 652 653 nvidia_write_regs(par, &par->ModeReg); 654 NVSetStartAddress(par, 0); 655 656#if defined(__BIG_ENDIAN) 657 /* turn on LFB swapping */ 658 { 659 unsigned char tmp; 660 661 VGA_WR08(par->PCIO, 0x3d4, 0x46); 662 tmp = VGA_RD08(par->PCIO, 0x3d5); 663 tmp |= (1 << 7); 664 VGA_WR08(par->PCIO, 0x3d5, tmp); 665 } 666#endif 667 668 info->fix.line_length = (info->var.xres_virtual * 669 info->var.bits_per_pixel) >> 3; 670 if (info->var.accel_flags) { 671 info->fbops->fb_imageblit = nvidiafb_imageblit; 672 info->fbops->fb_fillrect = nvidiafb_fillrect; 673 info->fbops->fb_copyarea = nvidiafb_copyarea; 674 info->fbops->fb_sync = nvidiafb_sync; 675 info->pixmap.scan_align = 4; 676 info->flags &= ~FBINFO_HWACCEL_DISABLED; 677 info->flags |= FBINFO_READS_FAST; 678 NVResetGraphics(info); 679 } else { 680 info->fbops->fb_imageblit = cfb_imageblit; 681 info->fbops->fb_fillrect = cfb_fillrect; 682 info->fbops->fb_copyarea = cfb_copyarea; 683 info->fbops->fb_sync = NULL; 684 info->pixmap.scan_align = 1; 685 info->flags |= FBINFO_HWACCEL_DISABLED; 686 info->flags &= ~FBINFO_READS_FAST; 687 } 688 689 par->cursor_reset = 1; 690 691 nvidia_screen_off(par, 0); 692 693#ifdef CONFIG_BOOTX_TEXT 694 /* Update debug text engine */ 695 btext_update_display(info->fix.smem_start, 696 info->var.xres, info->var.yres, 697 info->var.bits_per_pixel, info->fix.line_length); 698#endif 699 700 NVLockUnlock(par, 0); 701 NVTRACE_LEAVE(); 702 return 0; 703} 704 705static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green, 706 unsigned blue, unsigned transp, 707 struct fb_info *info) 708{ 709 struct nvidia_par *par = info->par; 710 int i; 711 712 NVTRACE_ENTER(); 713 if (regno >= (1 << info->var.green.length)) 714 return -EINVAL; 715 716 if (info->var.grayscale) { 717 /* gray = 0.30*R + 0.59*G + 0.11*B */ 718 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; 719 } 720 721 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 722 ((u32 *) info->pseudo_palette)[regno] = 723 (regno << info->var.red.offset) | 724 (regno << info->var.green.offset) | 725 (regno << info->var.blue.offset); 726 } 727 728 switch (info->var.bits_per_pixel) { 729 case 8: 730 /* "transparent" stuff is completely ignored. */ 731 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); 732 break; 733 case 16: 734 if (info->var.green.length == 5) { 735 for (i = 0; i < 8; i++) { 736 nvidia_write_clut(par, regno * 8 + i, red >> 8, 737 green >> 8, blue >> 8); 738 } 739 } else { 740 u8 r, g, b; 741 742 if (regno < 32) { 743 for (i = 0; i < 8; i++) { 744 nvidia_write_clut(par, regno * 8 + i, 745 red >> 8, green >> 8, 746 blue >> 8); 747 } 748 } 749 750 nvidia_read_clut(par, regno * 4, &r, &g, &b); 751 752 for (i = 0; i < 4; i++) 753 nvidia_write_clut(par, regno * 4 + i, r, 754 green >> 8, b); 755 } 756 break; 757 case 32: 758 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); 759 break; 760 default: 761 /* do nothing */ 762 break; 763 } 764 765 NVTRACE_LEAVE(); 766 return 0; 767} 768 769static int nvidiafb_check_var(struct fb_var_screeninfo *var, 770 struct fb_info *info) 771{ 772 struct nvidia_par *par = info->par; 773 int memlen, vramlen, mode_valid = 0; 774 int pitch, err = 0; 775 776 NVTRACE_ENTER(); 777 778 var->transp.offset = 0; 779 var->transp.length = 0; 780 781 var->xres &= ~7; 782 783 if (var->bits_per_pixel <= 8) 784 var->bits_per_pixel = 8; 785 else if (var->bits_per_pixel <= 16) 786 var->bits_per_pixel = 16; 787 else 788 var->bits_per_pixel = 32; 789 790 switch (var->bits_per_pixel) { 791 case 8: 792 var->red.offset = 0; 793 var->red.length = 8; 794 var->green.offset = 0; 795 var->green.length = 8; 796 var->blue.offset = 0; 797 var->blue.length = 8; 798 var->transp.offset = 0; 799 var->transp.length = 0; 800 break; 801 case 16: 802 var->green.length = (var->green.length < 6) ? 5 : 6; 803 var->red.length = 5; 804 var->blue.length = 5; 805 var->transp.length = 6 - var->green.length; 806 var->blue.offset = 0; 807 var->green.offset = 5; 808 var->red.offset = 5 + var->green.length; 809 var->transp.offset = (5 + var->red.offset) & 15; 810 break; 811 case 32: /* RGBA 8888 */ 812 var->red.offset = 16; 813 var->red.length = 8; 814 var->green.offset = 8; 815 var->green.length = 8; 816 var->blue.offset = 0; 817 var->blue.length = 8; 818 var->transp.length = 8; 819 var->transp.offset = 24; 820 break; 821 } 822 823 var->red.msb_right = 0; 824 var->green.msb_right = 0; 825 var->blue.msb_right = 0; 826 var->transp.msb_right = 0; 827 828 if (!info->monspecs.hfmax || !info->monspecs.vfmax || 829 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) 830 mode_valid = 1; 831 832 /* calculate modeline if supported by monitor */ 833 if (!mode_valid && info->monspecs.gtf) { 834 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) 835 mode_valid = 1; 836 } 837 838 if (!mode_valid) { 839 const struct fb_videomode *mode; 840 841 mode = fb_find_best_mode(var, &info->modelist); 842 if (mode) { 843 fb_videomode_to_var(var, mode); 844 mode_valid = 1; 845 } 846 } 847 848 if (!mode_valid && info->monspecs.modedb_len) 849 return -EINVAL; 850 851 /* 852 * If we're on a flat panel, check if the mode is outside of the 853 * panel dimensions. If so, cap it and try for the next best mode 854 * before bailing out. 855 */ 856 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres || 857 par->fpHeight < var->yres)) { 858 const struct fb_videomode *mode; 859 860 var->xres = par->fpWidth; 861 var->yres = par->fpHeight; 862 863 mode = fb_find_best_mode(var, &info->modelist); 864 if (!mode) { 865 printk(KERN_ERR PFX "mode out of range of flat " 866 "panel dimensions\n"); 867 return -EINVAL; 868 } 869 870 fb_videomode_to_var(var, mode); 871 } 872 873 if (var->yres_virtual < var->yres) 874 var->yres_virtual = var->yres; 875 876 if (var->xres_virtual < var->xres) 877 var->xres_virtual = var->xres; 878 879 var->xres_virtual = (var->xres_virtual + 63) & ~63; 880 881 vramlen = info->screen_size; 882 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8; 883 memlen = pitch * var->yres_virtual; 884 885 if (memlen > vramlen) { 886 var->yres_virtual = vramlen / pitch; 887 888 if (var->yres_virtual < var->yres) { 889 var->yres_virtual = var->yres; 890 var->xres_virtual = vramlen / var->yres_virtual; 891 var->xres_virtual /= var->bits_per_pixel / 8; 892 var->xres_virtual &= ~63; 893 pitch = (var->xres_virtual * 894 var->bits_per_pixel + 7) / 8; 895 memlen = pitch * var->yres; 896 897 if (var->xres_virtual < var->xres) { 898 printk("nvidiafb: required video memory, " 899 "%d bytes, for %dx%d-%d (virtual) " 900 "is out of range\n", 901 memlen, var->xres_virtual, 902 var->yres_virtual, var->bits_per_pixel); 903 err = -ENOMEM; 904 } 905 } 906 } 907 908 if (var->accel_flags) { 909 if (var->yres_virtual > 0x7fff) 910 var->yres_virtual = 0x7fff; 911 if (var->xres_virtual > 0x7fff) 912 var->xres_virtual = 0x7fff; 913 } 914 915 var->xres_virtual &= ~63; 916 917 NVTRACE_LEAVE(); 918 919 return err; 920} 921 922static int nvidiafb_pan_display(struct fb_var_screeninfo *var, 923 struct fb_info *info) 924{ 925 struct nvidia_par *par = info->par; 926 u32 total; 927 928 total = var->yoffset * info->fix.line_length + var->xoffset; 929 930 NVSetStartAddress(par, total); 931 932 return 0; 933} 934 935static int nvidiafb_blank(int blank, struct fb_info *info) 936{ 937 struct nvidia_par *par = info->par; 938 unsigned char tmp, vesa; 939 940 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */ 941 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */ 942 943 NVTRACE_ENTER(); 944 945 if (blank) 946 tmp |= 0x20; 947 948 switch (blank) { 949 case FB_BLANK_UNBLANK: 950 case FB_BLANK_NORMAL: 951 break; 952 case FB_BLANK_VSYNC_SUSPEND: 953 vesa |= 0x80; 954 break; 955 case FB_BLANK_HSYNC_SUSPEND: 956 vesa |= 0x40; 957 break; 958 case FB_BLANK_POWERDOWN: 959 vesa |= 0xc0; 960 break; 961 } 962 963 NVWriteSeq(par, 0x01, tmp); 964 NVWriteCrtc(par, 0x1a, vesa); 965 966 NVTRACE_LEAVE(); 967 968 return 0; 969} 970 971/* 972 * Because the VGA registers are not mapped linearly in its MMIO space, 973 * restrict VGA register saving and restore to x86 only, where legacy VGA IO 974 * access is legal. Consequently, we must also check if the device is the 975 * primary display. 976 */ 977#ifdef CONFIG_X86 978static void save_vga_x86(struct nvidia_par *par) 979{ 980 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; 981 982 if (res && res->flags & IORESOURCE_ROM_SHADOW) { 983 memset(&par->vgastate, 0, sizeof(par->vgastate)); 984 par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | 985 VGA_SAVE_CMAP; 986 save_vga(&par->vgastate); 987 } 988} 989 990static void restore_vga_x86(struct nvidia_par *par) 991{ 992 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; 993 994 if (res && res->flags & IORESOURCE_ROM_SHADOW) 995 restore_vga(&par->vgastate); 996} 997#else 998#define save_vga_x86(x) do {} while (0) 999#define restore_vga_x86(x) do {} while (0) 1000#endif /* X86 */ 1001 1002static int nvidiafb_open(struct fb_info *info, int user) 1003{ 1004 struct nvidia_par *par = info->par; 1005 1006 if (!par->open_count) { 1007 save_vga_x86(par); 1008 nvidia_save_vga(par, &par->initial_state); 1009 } 1010 1011 par->open_count++; 1012 return 0; 1013} 1014 1015static int nvidiafb_release(struct fb_info *info, int user) 1016{ 1017 struct nvidia_par *par = info->par; 1018 int err = 0; 1019 1020 if (!par->open_count) { 1021 err = -EINVAL; 1022 goto done; 1023 } 1024 1025 if (par->open_count == 1) { 1026 nvidia_write_regs(par, &par->initial_state); 1027 restore_vga_x86(par); 1028 } 1029 1030 par->open_count--; 1031done: 1032 return err; 1033} 1034 1035static struct fb_ops nvidia_fb_ops = { 1036 .owner = THIS_MODULE, 1037 .fb_open = nvidiafb_open, 1038 .fb_release = nvidiafb_release, 1039 .fb_check_var = nvidiafb_check_var, 1040 .fb_set_par = nvidiafb_set_par, 1041 .fb_setcolreg = nvidiafb_setcolreg, 1042 .fb_pan_display = nvidiafb_pan_display, 1043 .fb_blank = nvidiafb_blank, 1044 .fb_fillrect = nvidiafb_fillrect, 1045 .fb_copyarea = nvidiafb_copyarea, 1046 .fb_imageblit = nvidiafb_imageblit, 1047 .fb_cursor = nvidiafb_cursor, 1048 .fb_sync = nvidiafb_sync, 1049}; 1050 1051#ifdef CONFIG_PM 1052static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t mesg) 1053{ 1054 struct fb_info *info = pci_get_drvdata(dev); 1055 struct nvidia_par *par = info->par; 1056 1057 if (mesg.event == PM_EVENT_PRETHAW) 1058 mesg.event = PM_EVENT_FREEZE; 1059 acquire_console_sem(); 1060 par->pm_state = mesg.event; 1061 1062 if (mesg.event & PM_EVENT_SLEEP) { 1063 fb_set_suspend(info, 1); 1064 nvidiafb_blank(FB_BLANK_POWERDOWN, info); 1065 nvidia_write_regs(par, &par->SavedReg); 1066 pci_save_state(dev); 1067 pci_disable_device(dev); 1068 pci_set_power_state(dev, pci_choose_state(dev, mesg)); 1069 } 1070 dev->dev.power.power_state = mesg; 1071 1072 release_console_sem(); 1073 return 0; 1074} 1075 1076static int nvidiafb_resume(struct pci_dev *dev) 1077{ 1078 struct fb_info *info = pci_get_drvdata(dev); 1079 struct nvidia_par *par = info->par; 1080 1081 acquire_console_sem(); 1082 pci_set_power_state(dev, PCI_D0); 1083 1084 if (par->pm_state != PM_EVENT_FREEZE) { 1085 pci_restore_state(dev); 1086 1087 if (pci_enable_device(dev)) 1088 goto fail; 1089 1090 pci_set_master(dev); 1091 } 1092 1093 par->pm_state = PM_EVENT_ON; 1094 nvidiafb_set_par(info); 1095 fb_set_suspend (info, 0); 1096 nvidiafb_blank(FB_BLANK_UNBLANK, info); 1097 1098fail: 1099 release_console_sem(); 1100 return 0; 1101} 1102#else 1103#define nvidiafb_suspend NULL 1104#define nvidiafb_resume NULL 1105#endif 1106 1107static int __devinit nvidia_set_fbinfo(struct fb_info *info) 1108{ 1109 struct fb_monspecs *specs = &info->monspecs; 1110 struct fb_videomode modedb; 1111 struct nvidia_par *par = info->par; 1112 int lpitch; 1113 1114 NVTRACE_ENTER(); 1115 info->flags = FBINFO_DEFAULT 1116 | FBINFO_HWACCEL_IMAGEBLIT 1117 | FBINFO_HWACCEL_FILLRECT 1118 | FBINFO_HWACCEL_COPYAREA 1119 | FBINFO_HWACCEL_YPAN; 1120 1121 fb_videomode_to_modelist(info->monspecs.modedb, 1122 info->monspecs.modedb_len, &info->modelist); 1123 fb_var_to_videomode(&modedb, &nvidiafb_default_var); 1124 1125 switch (bpp) { 1126 case 0 ... 8: 1127 bpp = 8; 1128 break; 1129 case 9 ... 16: 1130 bpp = 16; 1131 break; 1132 default: 1133 bpp = 32; 1134 break; 1135 } 1136 1137 if (specs->modedb != NULL) { 1138 const struct fb_videomode *mode; 1139 1140 mode = fb_find_best_display(specs, &info->modelist); 1141 fb_videomode_to_var(&nvidiafb_default_var, mode); 1142 nvidiafb_default_var.bits_per_pixel = bpp; 1143 } else if (par->fpWidth && par->fpHeight) { 1144 char buf[16]; 1145 1146 memset(buf, 0, 16); 1147 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight); 1148 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb, 1149 specs->modedb_len, &modedb, bpp); 1150 } 1151 1152 if (mode_option) 1153 fb_find_mode(&nvidiafb_default_var, info, mode_option, 1154 specs->modedb, specs->modedb_len, &modedb, bpp); 1155 1156 info->var = nvidiafb_default_var; 1157 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1158 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1159 info->pseudo_palette = par->pseudo_palette; 1160 fb_alloc_cmap(&info->cmap, 256, 0); 1161 fb_destroy_modedb(info->monspecs.modedb); 1162 info->monspecs.modedb = NULL; 1163 1164 /* maximize virtual vertical length */ 1165 lpitch = info->var.xres_virtual * 1166 ((info->var.bits_per_pixel + 7) >> 3); 1167 info->var.yres_virtual = info->screen_size / lpitch; 1168 1169 info->pixmap.scan_align = 4; 1170 info->pixmap.buf_align = 4; 1171 info->pixmap.access_align = 32; 1172 info->pixmap.size = 8 * 1024; 1173 info->pixmap.flags = FB_PIXMAP_SYSTEM; 1174 1175 if (!hwcur) 1176 info->fbops->fb_cursor = NULL; 1177 1178 info->var.accel_flags = (!noaccel); 1179 1180 switch (par->Architecture) { 1181 case NV_ARCH_04: 1182 info->fix.accel = FB_ACCEL_NV4; 1183 break; 1184 case NV_ARCH_10: 1185 info->fix.accel = FB_ACCEL_NV_10; 1186 break; 1187 case NV_ARCH_20: 1188 info->fix.accel = FB_ACCEL_NV_20; 1189 break; 1190 case NV_ARCH_30: 1191 info->fix.accel = FB_ACCEL_NV_30; 1192 break; 1193 case NV_ARCH_40: 1194 info->fix.accel = FB_ACCEL_NV_40; 1195 break; 1196 } 1197 1198 NVTRACE_LEAVE(); 1199 1200 return nvidiafb_check_var(&info->var, info); 1201} 1202 1203static u32 __devinit nvidia_get_chipset(struct fb_info *info) 1204{ 1205 struct nvidia_par *par = info->par; 1206 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device; 1207 1208 printk(KERN_INFO PFX "Device ID: %x \n", id); 1209 1210 if ((id & 0xfff0) == 0x00f0 || 1211 (id & 0xfff0) == 0x02e0) { 1212 /* pci-e */ 1213 id = NV_RD32(par->REGS, 0x1800); 1214 1215 if ((id & 0x0000ffff) == 0x000010DE) 1216 id = 0x10DE0000 | (id >> 16); 1217 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */ 1218 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) | 1219 ((id >> 8) & 0x000000ff); 1220 printk(KERN_INFO PFX "Subsystem ID: %x \n", id); 1221 } 1222 1223 return id; 1224} 1225 1226static u32 __devinit nvidia_get_arch(struct fb_info *info) 1227{ 1228 struct nvidia_par *par = info->par; 1229 u32 arch = 0; 1230 1231 switch (par->Chipset & 0x0ff0) { 1232 case 0x0100: /* GeForce 256 */ 1233 case 0x0110: /* GeForce2 MX */ 1234 case 0x0150: /* GeForce2 */ 1235 case 0x0170: /* GeForce4 MX */ 1236 case 0x0180: /* GeForce4 MX (8x AGP) */ 1237 case 0x01A0: /* nForce */ 1238 case 0x01F0: /* nForce2 */ 1239 arch = NV_ARCH_10; 1240 break; 1241 case 0x0200: /* GeForce3 */ 1242 case 0x0250: /* GeForce4 Ti */ 1243 case 0x0280: /* GeForce4 Ti (8x AGP) */ 1244 arch = NV_ARCH_20; 1245 break; 1246 case 0x0300: /* GeForceFX 5800 */ 1247 case 0x0310: /* GeForceFX 5600 */ 1248 case 0x0320: /* GeForceFX 5200 */ 1249 case 0x0330: /* GeForceFX 5900 */ 1250 case 0x0340: /* GeForceFX 5700 */ 1251 arch = NV_ARCH_30; 1252 break; 1253 case 0x0040: /* GeForce 6800 */ 1254 case 0x00C0: /* GeForce 6800 */ 1255 case 0x0120: /* GeForce 6800 */ 1256 case 0x0140: /* GeForce 6600 */ 1257 case 0x0160: /* GeForce 6200 */ 1258 case 0x01D0: /* GeForce 7200, 7300, 7400 */ 1259 case 0x0090: /* GeForce 7800 */ 1260 case 0x0210: /* GeForce 6800 */ 1261 case 0x0220: /* GeForce 6200 */ 1262 case 0x0240: /* GeForce 6100 */ 1263 case 0x0290: /* GeForce 7900 */ 1264 case 0x0390: /* GeForce 7600 */ 1265 case 0x03D0: 1266 arch = NV_ARCH_40; 1267 break; 1268 case 0x0020: /* TNT, TNT2 */ 1269 arch = NV_ARCH_04; 1270 break; 1271 default: /* unknown architecture */ 1272 break; 1273 } 1274 1275 return arch; 1276} 1277 1278static int __devinit nvidiafb_probe(struct pci_dev *pd, 1279 const struct pci_device_id *ent) 1280{ 1281 struct nvidia_par *par; 1282 struct fb_info *info; 1283 unsigned short cmd; 1284 1285 1286 NVTRACE_ENTER(); 1287 assert(pd != NULL); 1288 1289 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev); 1290 1291 if (!info) 1292 goto err_out; 1293 1294 par = info->par; 1295 par->pci_dev = pd; 1296 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); 1297 1298 if (info->pixmap.addr == NULL) 1299 goto err_out_kfree; 1300 1301 if (pci_enable_device(pd)) { 1302 printk(KERN_ERR PFX "cannot enable PCI device\n"); 1303 goto err_out_enable; 1304 } 1305 1306 if (pci_request_regions(pd, "nvidiafb")) { 1307 printk(KERN_ERR PFX "cannot request PCI regions\n"); 1308 goto err_out_enable; 1309 } 1310 1311 par->FlatPanel = flatpanel; 1312 if (flatpanel == 1) 1313 printk(KERN_INFO PFX "flatpanel support enabled\n"); 1314 par->FPDither = fpdither; 1315 1316 par->CRTCnumber = forceCRTC; 1317 par->FpScale = (!noscale); 1318 par->paneltweak = paneltweak; 1319 par->reverse_i2c = reverse_i2c; 1320 1321 /* enable IO and mem if not already done */ 1322 pci_read_config_word(pd, PCI_COMMAND, &cmd); 1323 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1324 pci_write_config_word(pd, PCI_COMMAND, cmd); 1325 1326 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0); 1327 nvidiafb_fix.smem_start = pci_resource_start(pd, 1); 1328 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0); 1329 1330 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); 1331 1332 if (!par->REGS) { 1333 printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); 1334 goto err_out_free_base0; 1335 } 1336 1337 par->Chipset = nvidia_get_chipset(info); 1338 par->Architecture = nvidia_get_arch(info); 1339 1340 if (par->Architecture == 0) { 1341 printk(KERN_ERR PFX "unknown NV_ARCH\n"); 1342 goto err_out_arch; 1343 } 1344 1345 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); 1346 1347 if (NVCommonSetup(info)) 1348 goto err_out_arch; 1349 1350 par->FbAddress = nvidiafb_fix.smem_start; 1351 par->FbMapSize = par->RamAmountKBytes * 1024; 1352 if (vram && vram * 1024 * 1024 < par->FbMapSize) 1353 par->FbMapSize = vram * 1024 * 1024; 1354 1355 /* Limit amount of vram to 64 MB */ 1356 if (par->FbMapSize > 64 * 1024 * 1024) 1357 par->FbMapSize = 64 * 1024 * 1024; 1358 1359 if(par->Architecture >= NV_ARCH_40) 1360 par->FbUsableSize = par->FbMapSize - (560 * 1024); 1361 else 1362 par->FbUsableSize = par->FbMapSize - (128 * 1024); 1363 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 : 1364 16 * 1024; 1365 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize; 1366 par->CursorStart = par->FbUsableSize + (32 * 1024); 1367 1368 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize); 1369 info->screen_size = par->FbUsableSize; 1370 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024; 1371 1372 if (!info->screen_base) { 1373 printk(KERN_ERR PFX "cannot ioremap FB base\n"); 1374 goto err_out_free_base1; 1375 } 1376 1377 par->FbStart = info->screen_base; 1378 1379#ifdef CONFIG_MTRR 1380 if (!nomtrr) { 1381 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start, 1382 par->RamAmountKBytes * 1024, 1383 MTRR_TYPE_WRCOMB, 1); 1384 if (par->mtrr.vram < 0) { 1385 printk(KERN_ERR PFX "unable to setup MTRR\n"); 1386 } else { 1387 par->mtrr.vram_valid = 1; 1388 /* let there be speed */ 1389 printk(KERN_INFO PFX "MTRR set to ON\n"); 1390 } 1391 } 1392#endif /* CONFIG_MTRR */ 1393 1394 info->fbops = &nvidia_fb_ops; 1395 info->fix = nvidiafb_fix; 1396 1397 if (nvidia_set_fbinfo(info) < 0) { 1398 printk(KERN_ERR PFX "error setting initial video mode\n"); 1399 goto err_out_iounmap_fb; 1400 } 1401 1402 nvidia_save_vga(par, &par->SavedReg); 1403 1404 pci_set_drvdata(pd, info); 1405 1406 if (backlight) 1407 nvidia_bl_init(par); 1408 1409 if (register_framebuffer(info) < 0) { 1410 printk(KERN_ERR PFX "error registering nVidia framebuffer\n"); 1411 goto err_out_iounmap_fb; 1412 } 1413 1414 1415 printk(KERN_INFO PFX 1416 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n", 1417 info->fix.id, 1418 par->FbMapSize / (1024 * 1024), info->fix.smem_start); 1419 1420 NVTRACE_LEAVE(); 1421 return 0; 1422 1423err_out_iounmap_fb: 1424 iounmap(info->screen_base); 1425err_out_free_base1: 1426 fb_destroy_modedb(info->monspecs.modedb); 1427 nvidia_delete_i2c_busses(par); 1428err_out_arch: 1429 iounmap(par->REGS); 1430 err_out_free_base0: 1431 pci_release_regions(pd); 1432err_out_enable: 1433 kfree(info->pixmap.addr); 1434err_out_kfree: 1435 framebuffer_release(info); 1436err_out: 1437 return -ENODEV; 1438} 1439 1440static void __devexit nvidiafb_remove(struct pci_dev *pd) 1441{ 1442 struct fb_info *info = pci_get_drvdata(pd); 1443 struct nvidia_par *par = info->par; 1444 1445 NVTRACE_ENTER(); 1446 1447 unregister_framebuffer(info); 1448 1449 nvidia_bl_exit(par); 1450 1451#ifdef CONFIG_MTRR 1452 if (par->mtrr.vram_valid) 1453 mtrr_del(par->mtrr.vram, info->fix.smem_start, 1454 info->fix.smem_len); 1455#endif /* CONFIG_MTRR */ 1456 1457 iounmap(info->screen_base); 1458 fb_destroy_modedb(info->monspecs.modedb); 1459 nvidia_delete_i2c_busses(par); 1460 iounmap(par->REGS); 1461 pci_release_regions(pd); 1462 kfree(info->pixmap.addr); 1463 framebuffer_release(info); 1464 pci_set_drvdata(pd, NULL); 1465 NVTRACE_LEAVE(); 1466} 1467 1468/* ------------------------------------------------------------------------- * 1469 * 1470 * initialization 1471 * 1472 * ------------------------------------------------------------------------- */ 1473 1474#ifndef MODULE 1475static int __devinit nvidiafb_setup(char *options) 1476{ 1477 char *this_opt; 1478 1479 NVTRACE_ENTER(); 1480 if (!options || !*options) 1481 return 0; 1482 1483 while ((this_opt = strsep(&options, ",")) != NULL) { 1484 if (!strncmp(this_opt, "forceCRTC", 9)) { 1485 char *p; 1486 1487 p = this_opt + 9; 1488 if (!*p || !*(++p)) 1489 continue; 1490 forceCRTC = *p - '0'; 1491 if (forceCRTC < 0 || forceCRTC > 1) 1492 forceCRTC = -1; 1493 } else if (!strncmp(this_opt, "flatpanel", 9)) { 1494 flatpanel = 1; 1495 } else if (!strncmp(this_opt, "hwcur", 5)) { 1496 hwcur = 1; 1497 } else if (!strncmp(this_opt, "noaccel", 6)) { 1498 noaccel = 1; 1499 } else if (!strncmp(this_opt, "noscale", 7)) { 1500 noscale = 1; 1501 } else if (!strncmp(this_opt, "reverse_i2c", 11)) { 1502 reverse_i2c = 1; 1503 } else if (!strncmp(this_opt, "paneltweak:", 11)) { 1504 paneltweak = simple_strtoul(this_opt+11, NULL, 0); 1505 } else if (!strncmp(this_opt, "vram:", 5)) { 1506 vram = simple_strtoul(this_opt+5, NULL, 0); 1507 } else if (!strncmp(this_opt, "backlight:", 10)) { 1508 backlight = simple_strtoul(this_opt+10, NULL, 0); 1509#ifdef CONFIG_MTRR 1510 } else if (!strncmp(this_opt, "nomtrr", 6)) { 1511 nomtrr = 1; 1512#endif 1513 } else if (!strncmp(this_opt, "fpdither:", 9)) { 1514 fpdither = simple_strtol(this_opt+9, NULL, 0); 1515 } else if (!strncmp(this_opt, "bpp:", 4)) { 1516 bpp = simple_strtoul(this_opt+4, NULL, 0); 1517 } else 1518 mode_option = this_opt; 1519 } 1520 NVTRACE_LEAVE(); 1521 return 0; 1522} 1523#endif /* !MODULE */ 1524 1525static struct pci_driver nvidiafb_driver = { 1526 .name = "nvidiafb", 1527 .id_table = nvidiafb_pci_tbl, 1528 .probe = nvidiafb_probe, 1529 .suspend = nvidiafb_suspend, 1530 .resume = nvidiafb_resume, 1531 .remove = __devexit_p(nvidiafb_remove), 1532}; 1533 1534/* ------------------------------------------------------------------------- * 1535 * 1536 * modularization 1537 * 1538 * ------------------------------------------------------------------------- */ 1539 1540static int __devinit nvidiafb_init(void) 1541{ 1542#ifndef MODULE 1543 char *option = NULL; 1544 1545 if (fb_get_options("nvidiafb", &option)) 1546 return -ENODEV; 1547 nvidiafb_setup(option); 1548#endif 1549 return pci_register_driver(&nvidiafb_driver); 1550} 1551 1552module_init(nvidiafb_init); 1553 1554static void __exit nvidiafb_exit(void) 1555{ 1556 pci_unregister_driver(&nvidiafb_driver); 1557} 1558 1559module_exit(nvidiafb_exit); 1560 1561module_param(flatpanel, int, 0); 1562MODULE_PARM_DESC(flatpanel, 1563 "Enables experimental flat panel support for some chipsets. " 1564 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); 1565module_param(fpdither, int, 0); 1566MODULE_PARM_DESC(fpdither, 1567 "Enables dithering of flat panel for 6 bits panels. " 1568 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); 1569module_param(hwcur, int, 0); 1570MODULE_PARM_DESC(hwcur, 1571 "Enables hardware cursor implementation. (0 or 1=enabled) " 1572 "(default=0)"); 1573module_param(noaccel, int, 0); 1574MODULE_PARM_DESC(noaccel, 1575 "Disables hardware acceleration. (0 or 1=disable) " 1576 "(default=0)"); 1577module_param(noscale, int, 0); 1578MODULE_PARM_DESC(noscale, 1579 "Disables screen scaleing. (0 or 1=disable) " 1580 "(default=0, do scaling)"); 1581module_param(paneltweak, int, 0); 1582MODULE_PARM_DESC(paneltweak, 1583 "Tweak display settings for flatpanels. " 1584 "(default=0, no tweaks)"); 1585module_param(forceCRTC, int, 0); 1586MODULE_PARM_DESC(forceCRTC, 1587 "Forces usage of a particular CRTC in case autodetection " 1588 "fails. (0 or 1) (default=autodetect)"); 1589module_param(vram, int, 0); 1590MODULE_PARM_DESC(vram, 1591 "amount of framebuffer memory to remap in MiB" 1592 "(default=0 - remap entire memory)"); 1593module_param(mode_option, charp, 0); 1594MODULE_PARM_DESC(mode_option, "Specify initial video mode"); 1595module_param(bpp, int, 0); 1596MODULE_PARM_DESC(bpp, "pixel width in bits" 1597 "(default=8)"); 1598module_param(reverse_i2c, int, 0); 1599MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus"); 1600#ifdef CONFIG_MTRR 1601module_param(nomtrr, bool, 0); 1602MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) " 1603 "(default=0)"); 1604#endif 1605 1606MODULE_AUTHOR("Antonino Daplas"); 1607MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset"); 1608MODULE_LICENSE("GPL"); 1609