1/* 2 * Copyright 2005-2006 Erik Waling 3 * Copyright 2006 Stephane Marchesin 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 25#include "drmP.h" 26#define NV_DEBUG_NOTRACE 27#include "nouveau_drv.h" 28#include "nouveau_hw.h" 29#include "nouveau_encoder.h" 30 31#include <linux/io-mapping.h> 32 33/* these defines are made up */ 34#define NV_CIO_CRE_44_HEADA 0x0 35#define NV_CIO_CRE_44_HEADB 0x3 36#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */ 37#define LEGACY_I2C_CRT 0x80 38#define LEGACY_I2C_PANEL 0x81 39#define LEGACY_I2C_TV 0x82 40 41#define EDID1_LEN 128 42 43#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) 44#define LOG_OLD_VALUE(x) 45 46#define ROM16(x) le16_to_cpu(*(uint16_t *)&(x)) 47#define ROM32(x) le32_to_cpu(*(uint32_t *)&(x)) 48 49struct init_exec { 50 bool execute; 51 bool repeat; 52}; 53 54static bool nv_cksum(const uint8_t *data, unsigned int length) 55{ 56 /* 57 * There's a few checksums in the BIOS, so here's a generic checking 58 * function. 59 */ 60 int i; 61 uint8_t sum = 0; 62 63 for (i = 0; i < length; i++) 64 sum += data[i]; 65 66 if (sum) 67 return true; 68 69 return false; 70} 71 72static int 73score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable) 74{ 75 if (!(data[0] == 0x55 && data[1] == 0xAA)) { 76 NV_TRACEWARN(dev, "... BIOS signature not found\n"); 77 return 0; 78 } 79 80 if (nv_cksum(data, data[2] * 512)) { 81 NV_TRACEWARN(dev, "... BIOS checksum invalid\n"); 82 /* if a ro image is somewhat bad, it's probably all rubbish */ 83 return writeable ? 2 : 1; 84 } else 85 NV_TRACE(dev, "... appears to be valid\n"); 86 87 return 3; 88} 89 90static void load_vbios_prom(struct drm_device *dev, uint8_t *data) 91{ 92 struct drm_nouveau_private *dev_priv = dev->dev_private; 93 uint32_t pci_nv_20, save_pci_nv_20; 94 int pcir_ptr; 95 int i; 96 97 if (dev_priv->card_type >= NV_50) 98 pci_nv_20 = 0x88050; 99 else 100 pci_nv_20 = NV_PBUS_PCI_NV_20; 101 102 /* enable ROM access */ 103 save_pci_nv_20 = nvReadMC(dev, pci_nv_20); 104 nvWriteMC(dev, pci_nv_20, 105 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 106 107 /* bail if no rom signature */ 108 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 || 109 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa) 110 goto out; 111 112 /* additional check (see note below) - read PCI record header */ 113 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) | 114 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8; 115 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' || 116 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' || 117 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' || 118 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R') 119 goto out; 120 121 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a 122 * a good read may be obtained by waiting or re-reading (cargocult: 5x) 123 * each byte. we'll hope pramin has something usable instead 124 */ 125 for (i = 0; i < NV_PROM_SIZE; i++) 126 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i); 127 128out: 129 /* disable ROM access */ 130 nvWriteMC(dev, pci_nv_20, 131 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED); 132} 133 134static void load_vbios_pramin(struct drm_device *dev, uint8_t *data) 135{ 136 struct drm_nouveau_private *dev_priv = dev->dev_private; 137 uint32_t old_bar0_pramin = 0; 138 int i; 139 140 if (dev_priv->card_type >= NV_50) { 141 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8; 142 143 if (!vbios_vram) 144 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000; 145 146 old_bar0_pramin = nv_rd32(dev, 0x1700); 147 nv_wr32(dev, 0x1700, vbios_vram >> 16); 148 } 149 150 /* bail if no rom signature */ 151 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 || 152 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa) 153 goto out; 154 155 for (i = 0; i < NV_PROM_SIZE; i++) 156 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i); 157 158out: 159 if (dev_priv->card_type >= NV_50) 160 nv_wr32(dev, 0x1700, old_bar0_pramin); 161} 162 163static void load_vbios_pci(struct drm_device *dev, uint8_t *data) 164{ 165 void __iomem *rom = NULL; 166 size_t rom_len; 167 int ret; 168 169 ret = pci_enable_rom(dev->pdev); 170 if (ret) 171 return; 172 173 rom = pci_map_rom(dev->pdev, &rom_len); 174 if (!rom) 175 goto out; 176 memcpy_fromio(data, rom, rom_len); 177 pci_unmap_rom(dev->pdev, rom); 178 179out: 180 pci_disable_rom(dev->pdev); 181} 182 183static void load_vbios_acpi(struct drm_device *dev, uint8_t *data) 184{ 185 int i; 186 int ret; 187 int size = 64 * 1024; 188 189 if (!nouveau_acpi_rom_supported(dev->pdev)) 190 return; 191 192 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) { 193 ret = nouveau_acpi_get_bios_chunk(data, 194 (i * ROM_BIOS_PAGE), 195 ROM_BIOS_PAGE); 196 if (ret <= 0) 197 break; 198 } 199 return; 200} 201 202struct methods { 203 const char desc[8]; 204 void (*loadbios)(struct drm_device *, uint8_t *); 205 const bool rw; 206}; 207 208static struct methods shadow_methods[] = { 209 { "PRAMIN", load_vbios_pramin, true }, 210 { "PROM", load_vbios_prom, false }, 211 { "PCIROM", load_vbios_pci, true }, 212 { "ACPI", load_vbios_acpi, true }, 213}; 214#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods) 215 216static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 217{ 218 struct methods *methods = shadow_methods; 219 int testscore = 3; 220 int scores[NUM_SHADOW_METHODS], i; 221 222 if (nouveau_vbios) { 223 for (i = 0; i < NUM_SHADOW_METHODS; i++) 224 if (!strcasecmp(nouveau_vbios, methods[i].desc)) 225 break; 226 227 if (i < NUM_SHADOW_METHODS) { 228 NV_INFO(dev, "Attempting to use BIOS image from %s\n", 229 methods[i].desc); 230 231 methods[i].loadbios(dev, data); 232 if (score_vbios(dev, data, methods[i].rw)) 233 return true; 234 } 235 236 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios); 237 } 238 239 for (i = 0; i < NUM_SHADOW_METHODS; i++) { 240 NV_TRACE(dev, "Attempting to load BIOS image from %s\n", 241 methods[i].desc); 242 data[0] = data[1] = 0; /* avoid reuse of previous image */ 243 methods[i].loadbios(dev, data); 244 scores[i] = score_vbios(dev, data, methods[i].rw); 245 if (scores[i] == testscore) 246 return true; 247 } 248 249 while (--testscore > 0) { 250 for (i = 0; i < NUM_SHADOW_METHODS; i++) { 251 if (scores[i] == testscore) { 252 NV_TRACE(dev, "Using BIOS image from %s\n", 253 methods[i].desc); 254 methods[i].loadbios(dev, data); 255 return true; 256 } 257 } 258 } 259 260 NV_ERROR(dev, "No valid BIOS image found\n"); 261 return false; 262} 263 264struct init_tbl_entry { 265 char *name; 266 uint8_t id; 267 /* Return: 268 * > 0: success, length of opcode 269 * 0: success, but abort further parsing of table (INIT_DONE etc) 270 * < 0: failure, table parsing will be aborted 271 */ 272 int (*handler)(struct nvbios *, uint16_t, struct init_exec *); 273}; 274 275struct bit_entry { 276 uint8_t id[2]; 277 uint16_t length; 278 uint16_t offset; 279}; 280 281static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *); 282 283#define MACRO_INDEX_SIZE 2 284#define MACRO_SIZE 8 285#define CONDITION_SIZE 12 286#define IO_FLAG_CONDITION_SIZE 9 287#define IO_CONDITION_SIZE 5 288#define MEM_INIT_SIZE 66 289 290static void still_alive(void) 291{ 292} 293 294static uint32_t 295munge_reg(struct nvbios *bios, uint32_t reg) 296{ 297 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 298 struct dcb_entry *dcbent = bios->display.output; 299 300 if (dev_priv->card_type < NV_50) 301 return reg; 302 303 if (reg & 0x40000000) { 304 BUG_ON(!dcbent); 305 306 reg += (ffs(dcbent->or) - 1) * 0x800; 307 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1)) 308 reg += 0x00000080; 309 } 310 311 reg &= ~0x60000000; 312 return reg; 313} 314 315static int 316valid_reg(struct nvbios *bios, uint32_t reg) 317{ 318 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 319 struct drm_device *dev = bios->dev; 320 321 /* C51 has misaligned regs on purpose. Marvellous */ 322 if (reg & 0x2 || 323 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51)) 324 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg); 325 326 /* warn on C51 regs that haven't been verified accessible in tracing */ 327 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 && 328 reg != 0x130d && reg != 0x1311 && reg != 0x60081d) 329 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n", 330 reg); 331 332 if (reg >= (8*1024*1024)) { 333 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg); 334 return 0; 335 } 336 337 return 1; 338} 339 340static bool 341valid_idx_port(struct nvbios *bios, uint16_t port) 342{ 343 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 344 struct drm_device *dev = bios->dev; 345 346 /* 347 * If adding more ports here, the read/write functions below will need 348 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 349 * used for the port in question 350 */ 351 if (dev_priv->card_type < NV_50) { 352 if (port == NV_CIO_CRX__COLOR) 353 return true; 354 if (port == NV_VIO_SRX) 355 return true; 356 } else { 357 if (port == NV_CIO_CRX__COLOR) 358 return true; 359 } 360 361 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n", 362 port); 363 364 return false; 365} 366 367static bool 368valid_port(struct nvbios *bios, uint16_t port) 369{ 370 struct drm_device *dev = bios->dev; 371 372 /* 373 * If adding more ports here, the read/write functions below will need 374 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is 375 * used for the port in question 376 */ 377 if (port == NV_VIO_VSE2) 378 return true; 379 380 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port); 381 382 return false; 383} 384 385static uint32_t 386bios_rd32(struct nvbios *bios, uint32_t reg) 387{ 388 uint32_t data; 389 390 reg = munge_reg(bios, reg); 391 if (!valid_reg(bios, reg)) 392 return 0; 393 394 /* 395 * C51 sometimes uses regs with bit0 set in the address. For these 396 * cases there should exist a translation in a BIOS table to an IO 397 * port address which the BIOS uses for accessing the reg 398 * 399 * These only seem to appear for the power control regs to a flat panel, 400 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs 401 * for 0x1308 and 0x1310 are used - hence the mask below. An S3 402 * suspend-resume mmio trace from a C51 will be required to see if this 403 * is true for the power microcode in 0x14.., or whether the direct IO 404 * port access method is needed 405 */ 406 if (reg & 0x1) 407 reg &= ~0x1; 408 409 data = nv_rd32(bios->dev, reg); 410 411 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 412 413 return data; 414} 415 416static void 417bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data) 418{ 419 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 420 421 reg = munge_reg(bios, reg); 422 if (!valid_reg(bios, reg)) 423 return; 424 425 /* see note in bios_rd32 */ 426 if (reg & 0x1) 427 reg &= 0xfffffffe; 428 429 LOG_OLD_VALUE(bios_rd32(bios, reg)); 430 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data); 431 432 if (dev_priv->vbios.execute) { 433 still_alive(); 434 nv_wr32(bios->dev, reg, data); 435 } 436} 437 438static uint8_t 439bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index) 440{ 441 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 442 struct drm_device *dev = bios->dev; 443 uint8_t data; 444 445 if (!valid_idx_port(bios, port)) 446 return 0; 447 448 if (dev_priv->card_type < NV_50) { 449 if (port == NV_VIO_SRX) 450 data = NVReadVgaSeq(dev, bios->state.crtchead, index); 451 else /* assume NV_CIO_CRX__COLOR */ 452 data = NVReadVgaCrtc(dev, bios->state.crtchead, index); 453 } else { 454 uint32_t data32; 455 456 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 457 data = (data32 >> ((index & 3) << 3)) & 0xff; 458 } 459 460 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, " 461 "Head: 0x%02X, Data: 0x%02X\n", 462 port, index, bios->state.crtchead, data); 463 return data; 464} 465 466static void 467bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data) 468{ 469 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 470 struct drm_device *dev = bios->dev; 471 472 if (!valid_idx_port(bios, port)) 473 return; 474 475 /* 476 * The current head is maintained in the nvbios member state.crtchead. 477 * We trap changes to CR44 and update the head variable and hence the 478 * register set written. 479 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance 480 * of the write, and to head1 after the write 481 */ 482 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 && 483 data != NV_CIO_CRE_44_HEADB) 484 bios->state.crtchead = 0; 485 486 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index)); 487 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, " 488 "Head: 0x%02X, Data: 0x%02X\n", 489 port, index, bios->state.crtchead, data); 490 491 if (bios->execute && dev_priv->card_type < NV_50) { 492 still_alive(); 493 if (port == NV_VIO_SRX) 494 NVWriteVgaSeq(dev, bios->state.crtchead, index, data); 495 else /* assume NV_CIO_CRX__COLOR */ 496 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data); 497 } else 498 if (bios->execute) { 499 uint32_t data32, shift = (index & 3) << 3; 500 501 still_alive(); 502 503 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3)); 504 data32 &= ~(0xff << shift); 505 data32 |= (data << shift); 506 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32); 507 } 508 509 if (port == NV_CIO_CRX__COLOR && 510 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB) 511 bios->state.crtchead = 1; 512} 513 514static uint8_t 515bios_port_rd(struct nvbios *bios, uint16_t port) 516{ 517 uint8_t data, head = bios->state.crtchead; 518 519 if (!valid_port(bios, port)) 520 return 0; 521 522 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port); 523 524 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 525 port, head, data); 526 527 return data; 528} 529 530static void 531bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data) 532{ 533 int head = bios->state.crtchead; 534 535 if (!valid_port(bios, port)) 536 return; 537 538 LOG_OLD_VALUE(bios_port_rd(bios, port)); 539 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n", 540 port, head, data); 541 542 if (!bios->execute) 543 return; 544 545 still_alive(); 546 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data); 547} 548 549static bool 550io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 551{ 552 /* 553 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte 554 * for the CRTC index; 1 byte for the mask to apply to the value 555 * retrieved from the CRTC; 1 byte for the shift right to apply to the 556 * masked CRTC value; 2 bytes for the offset to the flag array, to 557 * which the shifted value is added; 1 byte for the mask applied to the 558 * value read from the flag array; and 1 byte for the value to compare 559 * against the masked byte from the flag table. 560 */ 561 562 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE; 563 uint16_t crtcport = ROM16(bios->data[condptr]); 564 uint8_t crtcindex = bios->data[condptr + 2]; 565 uint8_t mask = bios->data[condptr + 3]; 566 uint8_t shift = bios->data[condptr + 4]; 567 uint16_t flagarray = ROM16(bios->data[condptr + 5]); 568 uint8_t flagarraymask = bios->data[condptr + 7]; 569 uint8_t cmpval = bios->data[condptr + 8]; 570 uint8_t data; 571 572 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 573 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, " 574 "Cmpval: 0x%02X\n", 575 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval); 576 577 data = bios_idxprt_rd(bios, crtcport, crtcindex); 578 579 data = bios->data[flagarray + ((data & mask) >> shift)]; 580 data &= flagarraymask; 581 582 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 583 offset, data, cmpval); 584 585 return (data == cmpval); 586} 587 588static bool 589bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 590{ 591 /* 592 * The condition table entry has 4 bytes for the address of the 593 * register to check, 4 bytes for a mask to apply to the register and 594 * 4 for a test comparison value 595 */ 596 597 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE; 598 uint32_t reg = ROM32(bios->data[condptr]); 599 uint32_t mask = ROM32(bios->data[condptr + 4]); 600 uint32_t cmpval = ROM32(bios->data[condptr + 8]); 601 uint32_t data; 602 603 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n", 604 offset, cond, reg, mask); 605 606 data = bios_rd32(bios, reg) & mask; 607 608 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 609 offset, data, cmpval); 610 611 return (data == cmpval); 612} 613 614static bool 615io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond) 616{ 617 /* 618 * The IO condition entry has 2 bytes for the IO port address; 1 byte 619 * for the index to write to io_port; 1 byte for the mask to apply to 620 * the byte read from io_port+1; and 1 byte for the value to compare 621 * against the masked byte. 622 */ 623 624 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE; 625 uint16_t io_port = ROM16(bios->data[condptr]); 626 uint8_t port_index = bios->data[condptr + 2]; 627 uint8_t mask = bios->data[condptr + 3]; 628 uint8_t cmpval = bios->data[condptr + 4]; 629 630 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask; 631 632 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n", 633 offset, data, cmpval); 634 635 return (data == cmpval); 636} 637 638static int 639nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) 640{ 641 struct drm_nouveau_private *dev_priv = dev->dev_private; 642 uint32_t reg0 = nv_rd32(dev, reg + 0); 643 uint32_t reg1 = nv_rd32(dev, reg + 4); 644 struct nouveau_pll_vals pll; 645 struct pll_lims pll_limits; 646 int ret; 647 648 ret = get_pll_limits(dev, reg, &pll_limits); 649 if (ret) 650 return ret; 651 652 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll); 653 if (!clk) 654 return -ERANGE; 655 656 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16); 657 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1; 658 659 if (dev_priv->vbios.execute) { 660 still_alive(); 661 nv_wr32(dev, reg + 4, reg1); 662 nv_wr32(dev, reg + 0, reg0); 663 } 664 665 return 0; 666} 667 668static int 669setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk) 670{ 671 struct drm_device *dev = bios->dev; 672 struct drm_nouveau_private *dev_priv = dev->dev_private; 673 /* clk in kHz */ 674 struct pll_lims pll_lim; 675 struct nouveau_pll_vals pllvals; 676 int ret; 677 678 if (dev_priv->card_type >= NV_50) 679 return nv50_pll_set(dev, reg, clk); 680 681 /* high regs (such as in the mac g5 table) are not -= 4 */ 682 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim); 683 if (ret) 684 return ret; 685 686 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals); 687 if (!clk) 688 return -ERANGE; 689 690 if (bios->execute) { 691 still_alive(); 692 nouveau_hw_setpll(dev, reg, &pllvals); 693 } 694 695 return 0; 696} 697 698static int dcb_entry_idx_from_crtchead(struct drm_device *dev) 699{ 700 struct drm_nouveau_private *dev_priv = dev->dev_private; 701 struct nvbios *bios = &dev_priv->vbios; 702 703 /* 704 * For the results of this function to be correct, CR44 must have been 705 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0, 706 * and the DCB table parsed, before the script calling the function is 707 * run. run_digital_op_script is example of how to do such setup 708 */ 709 710 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0); 711 712 if (dcb_entry > bios->dcb.entries) { 713 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently " 714 "(%02X)\n", dcb_entry); 715 dcb_entry = 0x7f; /* unused / invalid marker */ 716 } 717 718 return dcb_entry; 719} 720 721static int 722read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c) 723{ 724 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4; 725 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES; 726 int recordoffset = 0, rdofs = 1, wrofs = 0; 727 uint8_t port_type = 0; 728 729 if (!i2ctable) 730 return -EINVAL; 731 732 if (dcb_version >= 0x30) { 733 if (i2ctable[0] != dcb_version) /* necessary? */ 734 NV_WARN(dev, 735 "DCB I2C table version mismatch (%02X vs %02X)\n", 736 i2ctable[0], dcb_version); 737 dcb_i2c_ver = i2ctable[0]; 738 headerlen = i2ctable[1]; 739 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES) 740 i2c_entries = i2ctable[2]; 741 else 742 NV_WARN(dev, 743 "DCB I2C table has more entries than indexable " 744 "(%d entries, max %d)\n", i2ctable[2], 745 DCB_MAX_NUM_I2C_ENTRIES); 746 entry_len = i2ctable[3]; 747 /* [4] is i2c_default_indices, read in parse_dcb_table() */ 748 } 749 /* 750 * It's your own fault if you call this function on a DCB 1.1 BIOS -- 751 * the test below is for DCB 1.2 752 */ 753 if (dcb_version < 0x14) { 754 recordoffset = 2; 755 rdofs = 0; 756 wrofs = 1; 757 } 758 759 if (index == 0xf) 760 return 0; 761 if (index >= i2c_entries) { 762 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n", 763 index, i2ctable[2]); 764 return -ENOENT; 765 } 766 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) { 767 NV_ERROR(dev, "DCB I2C entry invalid\n"); 768 return -EINVAL; 769 } 770 771 if (dcb_i2c_ver >= 0x30) { 772 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index]; 773 774 /* 775 * Fixup for chips using same address offset for read and 776 * write. 777 */ 778 if (port_type == 4) /* seen on C51 */ 779 rdofs = wrofs = 1; 780 if (port_type >= 5) /* G80+ */ 781 rdofs = wrofs = 0; 782 } 783 784 if (dcb_i2c_ver >= 0x40) { 785 if (port_type != 5 && port_type != 6) 786 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type); 787 788 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]); 789 } 790 791 i2c->port_type = port_type; 792 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index]; 793 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index]; 794 795 return 0; 796} 797 798static struct nouveau_i2c_chan * 799init_i2c_device_find(struct drm_device *dev, int i2c_index) 800{ 801 struct drm_nouveau_private *dev_priv = dev->dev_private; 802 struct dcb_table *dcb = &dev_priv->vbios.dcb; 803 804 if (i2c_index == 0xff) { 805 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 806 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0; 807 int default_indices = dcb->i2c_default_indices; 808 809 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default) 810 shift = 4; 811 812 i2c_index = (default_indices >> shift) & 0xf; 813 } 814 if (i2c_index == 0x80) /* g80+ */ 815 i2c_index = dcb->i2c_default_indices & 0xf; 816 else 817 if (i2c_index == 0x81) 818 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4; 819 820 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) { 821 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index); 822 return NULL; 823 } 824 825 /* Make sure i2c table entry has been parsed, it may not 826 * have been if this is a bus not referenced by a DCB encoder 827 */ 828 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 829 i2c_index, &dcb->i2c[i2c_index]); 830 831 return nouveau_i2c_find(dev, i2c_index); 832} 833 834static uint32_t 835get_tmds_index_reg(struct drm_device *dev, uint8_t mlv) 836{ 837 /* 838 * For mlv < 0x80, it is an index into a table of TMDS base addresses. 839 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 840 * CR58 for CR57 = 0 to index a table of offsets to the basic 841 * 0x6808b0 address. 842 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 843 * CR58 for CR57 = 0 to index a table of offsets to the basic 844 * 0x6808b0 address, and then flip the offset by 8. 845 */ 846 847 struct drm_nouveau_private *dev_priv = dev->dev_private; 848 struct nvbios *bios = &dev_priv->vbios; 849 const int pramdac_offset[13] = { 850 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 851 const uint32_t pramdac_table[4] = { 852 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 853 854 if (mlv >= 0x80) { 855 int dcb_entry, dacoffset; 856 857 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */ 858 dcb_entry = dcb_entry_idx_from_crtchead(dev); 859 if (dcb_entry == 0x7f) 860 return 0; 861 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or]; 862 if (mlv == 0x81) 863 dacoffset ^= 8; 864 return 0x6808b0 + dacoffset; 865 } else { 866 if (mlv >= ARRAY_SIZE(pramdac_table)) { 867 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n", 868 mlv); 869 return 0; 870 } 871 return pramdac_table[mlv]; 872 } 873} 874 875static int 876init_io_restrict_prog(struct nvbios *bios, uint16_t offset, 877 struct init_exec *iexec) 878{ 879 /* 880 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2') 881 * 882 * offset (8 bit): opcode 883 * offset + 1 (16 bit): CRTC port 884 * offset + 3 (8 bit): CRTC index 885 * offset + 4 (8 bit): mask 886 * offset + 5 (8 bit): shift 887 * offset + 6 (8 bit): count 888 * offset + 7 (32 bit): register 889 * offset + 11 (32 bit): configuration 1 890 * ... 891 * 892 * Starting at offset + 11 there are "count" 32 bit values. 893 * To find out which value to use read index "CRTC index" on "CRTC 894 * port", AND this value with "mask" and then bit shift right "shift" 895 * bits. Read the appropriate value using this index and write to 896 * "register" 897 */ 898 899 uint16_t crtcport = ROM16(bios->data[offset + 1]); 900 uint8_t crtcindex = bios->data[offset + 3]; 901 uint8_t mask = bios->data[offset + 4]; 902 uint8_t shift = bios->data[offset + 5]; 903 uint8_t count = bios->data[offset + 6]; 904 uint32_t reg = ROM32(bios->data[offset + 7]); 905 uint8_t config; 906 uint32_t configval; 907 int len = 11 + count * 4; 908 909 if (!iexec->execute) 910 return len; 911 912 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 913 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 914 offset, crtcport, crtcindex, mask, shift, count, reg); 915 916 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 917 if (config > count) { 918 NV_ERROR(bios->dev, 919 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 920 offset, config, count); 921 return len; 922 } 923 924 configval = ROM32(bios->data[offset + 11 + config * 4]); 925 926 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config); 927 928 bios_wr32(bios, reg, configval); 929 930 return len; 931} 932 933static int 934init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 935{ 936 /* 937 * INIT_REPEAT opcode: 0x33 ('3') 938 * 939 * offset (8 bit): opcode 940 * offset + 1 (8 bit): count 941 * 942 * Execute script following this opcode up to INIT_REPEAT_END 943 * "count" times 944 */ 945 946 uint8_t count = bios->data[offset + 1]; 947 uint8_t i; 948 949 /* no iexec->execute check by design */ 950 951 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n", 952 offset, count); 953 954 iexec->repeat = true; 955 956 /* 957 * count - 1, as the script block will execute once when we leave this 958 * opcode -- this is compatible with bios behaviour as: 959 * a) the block is always executed at least once, even if count == 0 960 * b) the bios interpreter skips to the op following INIT_END_REPEAT, 961 * while we don't 962 */ 963 for (i = 0; i < count - 1; i++) 964 parse_init_table(bios, offset + 2, iexec); 965 966 iexec->repeat = false; 967 968 return 2; 969} 970 971static int 972init_io_restrict_pll(struct nvbios *bios, uint16_t offset, 973 struct init_exec *iexec) 974{ 975 /* 976 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4') 977 * 978 * offset (8 bit): opcode 979 * offset + 1 (16 bit): CRTC port 980 * offset + 3 (8 bit): CRTC index 981 * offset + 4 (8 bit): mask 982 * offset + 5 (8 bit): shift 983 * offset + 6 (8 bit): IO flag condition index 984 * offset + 7 (8 bit): count 985 * offset + 8 (32 bit): register 986 * offset + 12 (16 bit): frequency 1 987 * ... 988 * 989 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz). 990 * Set PLL register "register" to coefficients for frequency n, 991 * selected by reading index "CRTC index" of "CRTC port" ANDed with 992 * "mask" and shifted right by "shift". 993 * 994 * If "IO flag condition index" > 0, and condition met, double 995 * frequency before setting it. 996 */ 997 998 uint16_t crtcport = ROM16(bios->data[offset + 1]); 999 uint8_t crtcindex = bios->data[offset + 3]; 1000 uint8_t mask = bios->data[offset + 4]; 1001 uint8_t shift = bios->data[offset + 5]; 1002 int8_t io_flag_condition_idx = bios->data[offset + 6]; 1003 uint8_t count = bios->data[offset + 7]; 1004 uint32_t reg = ROM32(bios->data[offset + 8]); 1005 uint8_t config; 1006 uint16_t freq; 1007 int len = 12 + count * 2; 1008 1009 if (!iexec->execute) 1010 return len; 1011 1012 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1013 "Shift: 0x%02X, IO Flag Condition: 0x%02X, " 1014 "Count: 0x%02X, Reg: 0x%08X\n", 1015 offset, crtcport, crtcindex, mask, shift, 1016 io_flag_condition_idx, count, reg); 1017 1018 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1019 if (config > count) { 1020 NV_ERROR(bios->dev, 1021 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1022 offset, config, count); 1023 return len; 1024 } 1025 1026 freq = ROM16(bios->data[offset + 12 + config * 2]); 1027 1028 if (io_flag_condition_idx > 0) { 1029 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) { 1030 BIOSLOG(bios, "0x%04X: Condition fulfilled -- " 1031 "frequency doubled\n", offset); 1032 freq *= 2; 1033 } else 1034 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- " 1035 "frequency unchanged\n", offset); 1036 } 1037 1038 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n", 1039 offset, reg, config, freq); 1040 1041 setPLL(bios, reg, freq * 10); 1042 1043 return len; 1044} 1045 1046static int 1047init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1048{ 1049 /* 1050 * INIT_END_REPEAT opcode: 0x36 ('6') 1051 * 1052 * offset (8 bit): opcode 1053 * 1054 * Marks the end of the block for INIT_REPEAT to repeat 1055 */ 1056 1057 /* no iexec->execute check by design */ 1058 1059 /* 1060 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when 1061 * we're not in repeat mode 1062 */ 1063 if (iexec->repeat) 1064 return 0; 1065 1066 return 1; 1067} 1068 1069static int 1070init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1071{ 1072 /* 1073 * INIT_COPY opcode: 0x37 ('7') 1074 * 1075 * offset (8 bit): opcode 1076 * offset + 1 (32 bit): register 1077 * offset + 5 (8 bit): shift 1078 * offset + 6 (8 bit): srcmask 1079 * offset + 7 (16 bit): CRTC port 1080 * offset + 9 (8 bit): CRTC index 1081 * offset + 10 (8 bit): mask 1082 * 1083 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with 1084 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC 1085 * port 1086 */ 1087 1088 uint32_t reg = ROM32(bios->data[offset + 1]); 1089 uint8_t shift = bios->data[offset + 5]; 1090 uint8_t srcmask = bios->data[offset + 6]; 1091 uint16_t crtcport = ROM16(bios->data[offset + 7]); 1092 uint8_t crtcindex = bios->data[offset + 9]; 1093 uint8_t mask = bios->data[offset + 10]; 1094 uint32_t data; 1095 uint8_t crtcdata; 1096 1097 if (!iexec->execute) 1098 return 11; 1099 1100 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, " 1101 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n", 1102 offset, reg, shift, srcmask, crtcport, crtcindex, mask); 1103 1104 data = bios_rd32(bios, reg); 1105 1106 if (shift < 0x80) 1107 data >>= shift; 1108 else 1109 data <<= (0x100 - shift); 1110 1111 data &= srcmask; 1112 1113 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask; 1114 crtcdata |= (uint8_t)data; 1115 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata); 1116 1117 return 11; 1118} 1119 1120static int 1121init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1122{ 1123 /* 1124 * INIT_NOT opcode: 0x38 ('8') 1125 * 1126 * offset (8 bit): opcode 1127 * 1128 * Invert the current execute / no-execute condition (i.e. "else") 1129 */ 1130 if (iexec->execute) 1131 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset); 1132 else 1133 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset); 1134 1135 iexec->execute = !iexec->execute; 1136 return 1; 1137} 1138 1139static int 1140init_io_flag_condition(struct nvbios *bios, uint16_t offset, 1141 struct init_exec *iexec) 1142{ 1143 /* 1144 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9') 1145 * 1146 * offset (8 bit): opcode 1147 * offset + 1 (8 bit): condition number 1148 * 1149 * Check condition "condition number" in the IO flag condition table. 1150 * If condition not met skip subsequent opcodes until condition is 1151 * inverted (INIT_NOT), or we hit INIT_RESUME 1152 */ 1153 1154 uint8_t cond = bios->data[offset + 1]; 1155 1156 if (!iexec->execute) 1157 return 2; 1158 1159 if (io_flag_condition_met(bios, offset, cond)) 1160 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 1161 else { 1162 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 1163 iexec->execute = false; 1164 } 1165 1166 return 2; 1167} 1168 1169static int 1170init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1171{ 1172 /* 1173 * INIT_DP_CONDITION opcode: 0x3A ('') 1174 * 1175 * offset (8 bit): opcode 1176 * offset + 1 (8 bit): "sub" opcode 1177 * offset + 2 (8 bit): unknown 1178 * 1179 */ 1180 1181 struct bit_displayport_encoder_table *dpe = NULL; 1182 struct dcb_entry *dcb = bios->display.output; 1183 struct drm_device *dev = bios->dev; 1184 uint8_t cond = bios->data[offset + 1]; 1185 int dummy; 1186 1187 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond); 1188 1189 if (!iexec->execute) 1190 return 3; 1191 1192 dpe = nouveau_bios_dp_table(dev, dcb, &dummy); 1193 if (!dpe) { 1194 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset); 1195 return 3; 1196 } 1197 1198 switch (cond) { 1199 case 0: 1200 { 1201 struct dcb_connector_table_entry *ent = 1202 &bios->dcb.connector.entry[dcb->connector]; 1203 1204 if (ent->type != DCB_CONNECTOR_eDP) 1205 iexec->execute = false; 1206 } 1207 break; 1208 case 1: 1209 case 2: 1210 if (!(dpe->unknown & cond)) 1211 iexec->execute = false; 1212 break; 1213 case 5: 1214 { 1215 struct nouveau_i2c_chan *auxch; 1216 int ret; 1217 1218 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index); 1219 if (!auxch) { 1220 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset); 1221 return 3; 1222 } 1223 1224 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1); 1225 if (ret) { 1226 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret); 1227 return 3; 1228 } 1229 1230 if (cond & 1) 1231 iexec->execute = false; 1232 } 1233 break; 1234 default: 1235 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond); 1236 break; 1237 } 1238 1239 if (iexec->execute) 1240 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset); 1241 else 1242 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset); 1243 1244 return 3; 1245} 1246 1247static int 1248init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1249{ 1250 /* 1251 * INIT_3B opcode: 0x3B ('') 1252 * 1253 * offset (8 bit): opcode 1254 * offset + 1 (8 bit): crtc index 1255 * 1256 */ 1257 1258 uint8_t or = ffs(bios->display.output->or) - 1; 1259 uint8_t index = bios->data[offset + 1]; 1260 uint8_t data; 1261 1262 if (!iexec->execute) 1263 return 2; 1264 1265 data = bios_idxprt_rd(bios, 0x3d4, index); 1266 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or)); 1267 return 2; 1268} 1269 1270static int 1271init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1272{ 1273 /* 1274 * INIT_3C opcode: 0x3C ('') 1275 * 1276 * offset (8 bit): opcode 1277 * offset + 1 (8 bit): crtc index 1278 * 1279 */ 1280 1281 uint8_t or = ffs(bios->display.output->or) - 1; 1282 uint8_t index = bios->data[offset + 1]; 1283 uint8_t data; 1284 1285 if (!iexec->execute) 1286 return 2; 1287 1288 data = bios_idxprt_rd(bios, 0x3d4, index); 1289 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or)); 1290 return 2; 1291} 1292 1293static int 1294init_idx_addr_latched(struct nvbios *bios, uint16_t offset, 1295 struct init_exec *iexec) 1296{ 1297 /* 1298 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I') 1299 * 1300 * offset (8 bit): opcode 1301 * offset + 1 (32 bit): control register 1302 * offset + 5 (32 bit): data register 1303 * offset + 9 (32 bit): mask 1304 * offset + 13 (32 bit): data 1305 * offset + 17 (8 bit): count 1306 * offset + 18 (8 bit): address 1 1307 * offset + 19 (8 bit): data 1 1308 * ... 1309 * 1310 * For each of "count" address and data pairs, write "data n" to 1311 * "data register", read the current value of "control register", 1312 * and write it back once ANDed with "mask", ORed with "data", 1313 * and ORed with "address n" 1314 */ 1315 1316 uint32_t controlreg = ROM32(bios->data[offset + 1]); 1317 uint32_t datareg = ROM32(bios->data[offset + 5]); 1318 uint32_t mask = ROM32(bios->data[offset + 9]); 1319 uint32_t data = ROM32(bios->data[offset + 13]); 1320 uint8_t count = bios->data[offset + 17]; 1321 int len = 18 + count * 2; 1322 uint32_t value; 1323 int i; 1324 1325 if (!iexec->execute) 1326 return len; 1327 1328 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, " 1329 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n", 1330 offset, controlreg, datareg, mask, data, count); 1331 1332 for (i = 0; i < count; i++) { 1333 uint8_t instaddress = bios->data[offset + 18 + i * 2]; 1334 uint8_t instdata = bios->data[offset + 19 + i * 2]; 1335 1336 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n", 1337 offset, instaddress, instdata); 1338 1339 bios_wr32(bios, datareg, instdata); 1340 value = bios_rd32(bios, controlreg) & mask; 1341 value |= data; 1342 value |= instaddress; 1343 bios_wr32(bios, controlreg, value); 1344 } 1345 1346 return len; 1347} 1348 1349static int 1350init_io_restrict_pll2(struct nvbios *bios, uint16_t offset, 1351 struct init_exec *iexec) 1352{ 1353 /* 1354 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J') 1355 * 1356 * offset (8 bit): opcode 1357 * offset + 1 (16 bit): CRTC port 1358 * offset + 3 (8 bit): CRTC index 1359 * offset + 4 (8 bit): mask 1360 * offset + 5 (8 bit): shift 1361 * offset + 6 (8 bit): count 1362 * offset + 7 (32 bit): register 1363 * offset + 11 (32 bit): frequency 1 1364 * ... 1365 * 1366 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz). 1367 * Set PLL register "register" to coefficients for frequency n, 1368 * selected by reading index "CRTC index" of "CRTC port" ANDed with 1369 * "mask" and shifted right by "shift". 1370 */ 1371 1372 uint16_t crtcport = ROM16(bios->data[offset + 1]); 1373 uint8_t crtcindex = bios->data[offset + 3]; 1374 uint8_t mask = bios->data[offset + 4]; 1375 uint8_t shift = bios->data[offset + 5]; 1376 uint8_t count = bios->data[offset + 6]; 1377 uint32_t reg = ROM32(bios->data[offset + 7]); 1378 int len = 11 + count * 4; 1379 uint8_t config; 1380 uint32_t freq; 1381 1382 if (!iexec->execute) 1383 return len; 1384 1385 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 1386 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n", 1387 offset, crtcport, crtcindex, mask, shift, count, reg); 1388 1389 if (!reg) 1390 return len; 1391 1392 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift; 1393 if (config > count) { 1394 NV_ERROR(bios->dev, 1395 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n", 1396 offset, config, count); 1397 return len; 1398 } 1399 1400 freq = ROM32(bios->data[offset + 11 + config * 4]); 1401 1402 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n", 1403 offset, reg, config, freq); 1404 1405 setPLL(bios, reg, freq); 1406 1407 return len; 1408} 1409 1410static int 1411init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1412{ 1413 /* 1414 * INIT_PLL2 opcode: 0x4B ('K') 1415 * 1416 * offset (8 bit): opcode 1417 * offset + 1 (32 bit): register 1418 * offset + 5 (32 bit): freq 1419 * 1420 * Set PLL register "register" to coefficients for frequency "freq" 1421 */ 1422 1423 uint32_t reg = ROM32(bios->data[offset + 1]); 1424 uint32_t freq = ROM32(bios->data[offset + 5]); 1425 1426 if (!iexec->execute) 1427 return 9; 1428 1429 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n", 1430 offset, reg, freq); 1431 1432 setPLL(bios, reg, freq); 1433 return 9; 1434} 1435 1436static int 1437init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1438{ 1439 /* 1440 * INIT_I2C_BYTE opcode: 0x4C ('L') 1441 * 1442 * offset (8 bit): opcode 1443 * offset + 1 (8 bit): DCB I2C table entry index 1444 * offset + 2 (8 bit): I2C slave address 1445 * offset + 3 (8 bit): count 1446 * offset + 4 (8 bit): I2C register 1 1447 * offset + 5 (8 bit): mask 1 1448 * offset + 6 (8 bit): data 1 1449 * ... 1450 * 1451 * For each of "count" registers given by "I2C register n" on the device 1452 * addressed by "I2C slave address" on the I2C bus given by 1453 * "DCB I2C table entry index", read the register, AND the result with 1454 * "mask n" and OR it with "data n" before writing it back to the device 1455 */ 1456 1457 struct drm_device *dev = bios->dev; 1458 uint8_t i2c_index = bios->data[offset + 1]; 1459 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1460 uint8_t count = bios->data[offset + 3]; 1461 struct nouveau_i2c_chan *chan; 1462 int len = 4 + count * 3; 1463 int ret, i; 1464 1465 if (!iexec->execute) 1466 return len; 1467 1468 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1469 "Count: 0x%02X\n", 1470 offset, i2c_index, i2c_address, count); 1471 1472 chan = init_i2c_device_find(dev, i2c_index); 1473 if (!chan) { 1474 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1475 return len; 1476 } 1477 1478 for (i = 0; i < count; i++) { 1479 uint8_t reg = bios->data[offset + 4 + i * 3]; 1480 uint8_t mask = bios->data[offset + 5 + i * 3]; 1481 uint8_t data = bios->data[offset + 6 + i * 3]; 1482 union i2c_smbus_data val; 1483 1484 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1485 I2C_SMBUS_READ, reg, 1486 I2C_SMBUS_BYTE_DATA, &val); 1487 if (ret < 0) { 1488 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret); 1489 return len; 1490 } 1491 1492 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 1493 "Mask: 0x%02X, Data: 0x%02X\n", 1494 offset, reg, val.byte, mask, data); 1495 1496 if (!bios->execute) 1497 continue; 1498 1499 val.byte &= mask; 1500 val.byte |= data; 1501 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1502 I2C_SMBUS_WRITE, reg, 1503 I2C_SMBUS_BYTE_DATA, &val); 1504 if (ret < 0) { 1505 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1506 return len; 1507 } 1508 } 1509 1510 return len; 1511} 1512 1513static int 1514init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1515{ 1516 /* 1517 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M') 1518 * 1519 * offset (8 bit): opcode 1520 * offset + 1 (8 bit): DCB I2C table entry index 1521 * offset + 2 (8 bit): I2C slave address 1522 * offset + 3 (8 bit): count 1523 * offset + 4 (8 bit): I2C register 1 1524 * offset + 5 (8 bit): data 1 1525 * ... 1526 * 1527 * For each of "count" registers given by "I2C register n" on the device 1528 * addressed by "I2C slave address" on the I2C bus given by 1529 * "DCB I2C table entry index", set the register to "data n" 1530 */ 1531 1532 struct drm_device *dev = bios->dev; 1533 uint8_t i2c_index = bios->data[offset + 1]; 1534 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1535 uint8_t count = bios->data[offset + 3]; 1536 struct nouveau_i2c_chan *chan; 1537 int len = 4 + count * 2; 1538 int ret, i; 1539 1540 if (!iexec->execute) 1541 return len; 1542 1543 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1544 "Count: 0x%02X\n", 1545 offset, i2c_index, i2c_address, count); 1546 1547 chan = init_i2c_device_find(dev, i2c_index); 1548 if (!chan) { 1549 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1550 return len; 1551 } 1552 1553 for (i = 0; i < count; i++) { 1554 uint8_t reg = bios->data[offset + 4 + i * 2]; 1555 union i2c_smbus_data val; 1556 1557 val.byte = bios->data[offset + 5 + i * 2]; 1558 1559 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n", 1560 offset, reg, val.byte); 1561 1562 if (!bios->execute) 1563 continue; 1564 1565 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 1566 I2C_SMBUS_WRITE, reg, 1567 I2C_SMBUS_BYTE_DATA, &val); 1568 if (ret < 0) { 1569 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1570 return len; 1571 } 1572 } 1573 1574 return len; 1575} 1576 1577static int 1578init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1579{ 1580 /* 1581 * INIT_ZM_I2C opcode: 0x4E ('N') 1582 * 1583 * offset (8 bit): opcode 1584 * offset + 1 (8 bit): DCB I2C table entry index 1585 * offset + 2 (8 bit): I2C slave address 1586 * offset + 3 (8 bit): count 1587 * offset + 4 (8 bit): data 1 1588 * ... 1589 * 1590 * Send "count" bytes ("data n") to the device addressed by "I2C slave 1591 * address" on the I2C bus given by "DCB I2C table entry index" 1592 */ 1593 1594 struct drm_device *dev = bios->dev; 1595 uint8_t i2c_index = bios->data[offset + 1]; 1596 uint8_t i2c_address = bios->data[offset + 2] >> 1; 1597 uint8_t count = bios->data[offset + 3]; 1598 int len = 4 + count; 1599 struct nouveau_i2c_chan *chan; 1600 struct i2c_msg msg; 1601 uint8_t data[256]; 1602 int ret, i; 1603 1604 if (!iexec->execute) 1605 return len; 1606 1607 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, " 1608 "Count: 0x%02X\n", 1609 offset, i2c_index, i2c_address, count); 1610 1611 chan = init_i2c_device_find(dev, i2c_index); 1612 if (!chan) { 1613 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset); 1614 return len; 1615 } 1616 1617 for (i = 0; i < count; i++) { 1618 data[i] = bios->data[offset + 4 + i]; 1619 1620 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]); 1621 } 1622 1623 if (bios->execute) { 1624 msg.addr = i2c_address; 1625 msg.flags = 0; 1626 msg.len = count; 1627 msg.buf = data; 1628 ret = i2c_transfer(&chan->adapter, &msg, 1); 1629 if (ret != 1) { 1630 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret); 1631 return len; 1632 } 1633 } 1634 1635 return len; 1636} 1637 1638static int 1639init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1640{ 1641 /* 1642 * INIT_TMDS opcode: 0x4F ('O') (non-canon name) 1643 * 1644 * offset (8 bit): opcode 1645 * offset + 1 (8 bit): magic lookup value 1646 * offset + 2 (8 bit): TMDS address 1647 * offset + 3 (8 bit): mask 1648 * offset + 4 (8 bit): data 1649 * 1650 * Read the data reg for TMDS address "TMDS address", AND it with mask 1651 * and OR it with data, then write it back 1652 * "magic lookup value" determines which TMDS base address register is 1653 * used -- see get_tmds_index_reg() 1654 */ 1655 1656 struct drm_device *dev = bios->dev; 1657 uint8_t mlv = bios->data[offset + 1]; 1658 uint32_t tmdsaddr = bios->data[offset + 2]; 1659 uint8_t mask = bios->data[offset + 3]; 1660 uint8_t data = bios->data[offset + 4]; 1661 uint32_t reg, value; 1662 1663 if (!iexec->execute) 1664 return 5; 1665 1666 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, " 1667 "Mask: 0x%02X, Data: 0x%02X\n", 1668 offset, mlv, tmdsaddr, mask, data); 1669 1670 reg = get_tmds_index_reg(bios->dev, mlv); 1671 if (!reg) { 1672 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1673 return 5; 1674 } 1675 1676 bios_wr32(bios, reg, 1677 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE); 1678 value = (bios_rd32(bios, reg + 4) & mask) | data; 1679 bios_wr32(bios, reg + 4, value); 1680 bios_wr32(bios, reg, tmdsaddr); 1681 1682 return 5; 1683} 1684 1685static int 1686init_zm_tmds_group(struct nvbios *bios, uint16_t offset, 1687 struct init_exec *iexec) 1688{ 1689 /* 1690 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name) 1691 * 1692 * offset (8 bit): opcode 1693 * offset + 1 (8 bit): magic lookup value 1694 * offset + 2 (8 bit): count 1695 * offset + 3 (8 bit): addr 1 1696 * offset + 4 (8 bit): data 1 1697 * ... 1698 * 1699 * For each of "count" TMDS address and data pairs write "data n" to 1700 * "addr n". "magic lookup value" determines which TMDS base address 1701 * register is used -- see get_tmds_index_reg() 1702 */ 1703 1704 struct drm_device *dev = bios->dev; 1705 uint8_t mlv = bios->data[offset + 1]; 1706 uint8_t count = bios->data[offset + 2]; 1707 int len = 3 + count * 2; 1708 uint32_t reg; 1709 int i; 1710 1711 if (!iexec->execute) 1712 return len; 1713 1714 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n", 1715 offset, mlv, count); 1716 1717 reg = get_tmds_index_reg(bios->dev, mlv); 1718 if (!reg) { 1719 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset); 1720 return len; 1721 } 1722 1723 for (i = 0; i < count; i++) { 1724 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2]; 1725 uint8_t tmdsdata = bios->data[offset + 4 + i * 2]; 1726 1727 bios_wr32(bios, reg + 4, tmdsdata); 1728 bios_wr32(bios, reg, tmdsaddr); 1729 } 1730 1731 return len; 1732} 1733 1734static int 1735init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset, 1736 struct init_exec *iexec) 1737{ 1738 /* 1739 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q') 1740 * 1741 * offset (8 bit): opcode 1742 * offset + 1 (8 bit): CRTC index1 1743 * offset + 2 (8 bit): CRTC index2 1744 * offset + 3 (8 bit): baseaddr 1745 * offset + 4 (8 bit): count 1746 * offset + 5 (8 bit): data 1 1747 * ... 1748 * 1749 * For each of "count" address and data pairs, write "baseaddr + n" to 1750 * "CRTC index1" and "data n" to "CRTC index2" 1751 * Once complete, restore initial value read from "CRTC index1" 1752 */ 1753 uint8_t crtcindex1 = bios->data[offset + 1]; 1754 uint8_t crtcindex2 = bios->data[offset + 2]; 1755 uint8_t baseaddr = bios->data[offset + 3]; 1756 uint8_t count = bios->data[offset + 4]; 1757 int len = 5 + count; 1758 uint8_t oldaddr, data; 1759 int i; 1760 1761 if (!iexec->execute) 1762 return len; 1763 1764 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, " 1765 "BaseAddr: 0x%02X, Count: 0x%02X\n", 1766 offset, crtcindex1, crtcindex2, baseaddr, count); 1767 1768 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1); 1769 1770 for (i = 0; i < count; i++) { 1771 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, 1772 baseaddr + i); 1773 data = bios->data[offset + 5 + i]; 1774 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data); 1775 } 1776 1777 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr); 1778 1779 return len; 1780} 1781 1782static int 1783init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1784{ 1785 /* 1786 * INIT_CR opcode: 0x52 ('R') 1787 * 1788 * offset (8 bit): opcode 1789 * offset + 1 (8 bit): CRTC index 1790 * offset + 2 (8 bit): mask 1791 * offset + 3 (8 bit): data 1792 * 1793 * Assign the value of at "CRTC index" ANDed with mask and ORed with 1794 * data back to "CRTC index" 1795 */ 1796 1797 uint8_t crtcindex = bios->data[offset + 1]; 1798 uint8_t mask = bios->data[offset + 2]; 1799 uint8_t data = bios->data[offset + 3]; 1800 uint8_t value; 1801 1802 if (!iexec->execute) 1803 return 4; 1804 1805 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n", 1806 offset, crtcindex, mask, data); 1807 1808 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask; 1809 value |= data; 1810 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value); 1811 1812 return 4; 1813} 1814 1815static int 1816init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1817{ 1818 /* 1819 * INIT_ZM_CR opcode: 0x53 ('S') 1820 * 1821 * offset (8 bit): opcode 1822 * offset + 1 (8 bit): CRTC index 1823 * offset + 2 (8 bit): value 1824 * 1825 * Assign "value" to CRTC register with index "CRTC index". 1826 */ 1827 1828 uint8_t crtcindex = ROM32(bios->data[offset + 1]); 1829 uint8_t data = bios->data[offset + 2]; 1830 1831 if (!iexec->execute) 1832 return 3; 1833 1834 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data); 1835 1836 return 3; 1837} 1838 1839static int 1840init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1841{ 1842 /* 1843 * INIT_ZM_CR_GROUP opcode: 0x54 ('T') 1844 * 1845 * offset (8 bit): opcode 1846 * offset + 1 (8 bit): count 1847 * offset + 2 (8 bit): CRTC index 1 1848 * offset + 3 (8 bit): value 1 1849 * ... 1850 * 1851 * For "count", assign "value n" to CRTC register with index 1852 * "CRTC index n". 1853 */ 1854 1855 uint8_t count = bios->data[offset + 1]; 1856 int len = 2 + count * 2; 1857 int i; 1858 1859 if (!iexec->execute) 1860 return len; 1861 1862 for (i = 0; i < count; i++) 1863 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec); 1864 1865 return len; 1866} 1867 1868static int 1869init_condition_time(struct nvbios *bios, uint16_t offset, 1870 struct init_exec *iexec) 1871{ 1872 /* 1873 * INIT_CONDITION_TIME opcode: 0x56 ('V') 1874 * 1875 * offset (8 bit): opcode 1876 * offset + 1 (8 bit): condition number 1877 * offset + 2 (8 bit): retries / 50 1878 * 1879 * Check condition "condition number" in the condition table. 1880 * Bios code then sleeps for 2ms if the condition is not met, and 1881 * repeats up to "retries" times, but on one C51 this has proved 1882 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do 1883 * this, and bail after "retries" times, or 2s, whichever is less. 1884 * If still not met after retries, clear execution flag for this table. 1885 */ 1886 1887 uint8_t cond = bios->data[offset + 1]; 1888 uint16_t retries = bios->data[offset + 2] * 50; 1889 unsigned cnt; 1890 1891 if (!iexec->execute) 1892 return 3; 1893 1894 if (retries > 100) 1895 retries = 100; 1896 1897 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n", 1898 offset, cond, retries); 1899 1900 if (!bios->execute) /* avoid 2s delays when "faking" execution */ 1901 retries = 1; 1902 1903 for (cnt = 0; cnt < retries; cnt++) { 1904 if (bios_condition_met(bios, offset, cond)) { 1905 BIOSLOG(bios, "0x%04X: Condition met, continuing\n", 1906 offset); 1907 break; 1908 } else { 1909 BIOSLOG(bios, "0x%04X: " 1910 "Condition not met, sleeping for 20ms\n", 1911 offset); 1912 msleep(20); 1913 } 1914 } 1915 1916 if (!bios_condition_met(bios, offset, cond)) { 1917 NV_WARN(bios->dev, 1918 "0x%04X: Condition still not met after %dms, " 1919 "skipping following opcodes\n", offset, 20 * retries); 1920 iexec->execute = false; 1921 } 1922 1923 return 3; 1924} 1925 1926static int 1927init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1928{ 1929 /* 1930 * INIT_LTIME opcode: 0x57 ('V') 1931 * 1932 * offset (8 bit): opcode 1933 * offset + 1 (16 bit): time 1934 * 1935 * Sleep for "time" miliseconds. 1936 */ 1937 1938 unsigned time = ROM16(bios->data[offset + 1]); 1939 1940 if (!iexec->execute) 1941 return 3; 1942 1943 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X miliseconds\n", 1944 offset, time); 1945 1946 msleep(time); 1947 1948 return 3; 1949} 1950 1951static int 1952init_zm_reg_sequence(struct nvbios *bios, uint16_t offset, 1953 struct init_exec *iexec) 1954{ 1955 /* 1956 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X') 1957 * 1958 * offset (8 bit): opcode 1959 * offset + 1 (32 bit): base register 1960 * offset + 5 (8 bit): count 1961 * offset + 6 (32 bit): value 1 1962 * ... 1963 * 1964 * Starting at offset + 6 there are "count" 32 bit values. 1965 * For "count" iterations set "base register" + 4 * current_iteration 1966 * to "value current_iteration" 1967 */ 1968 1969 uint32_t basereg = ROM32(bios->data[offset + 1]); 1970 uint32_t count = bios->data[offset + 5]; 1971 int len = 6 + count * 4; 1972 int i; 1973 1974 if (!iexec->execute) 1975 return len; 1976 1977 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n", 1978 offset, basereg, count); 1979 1980 for (i = 0; i < count; i++) { 1981 uint32_t reg = basereg + i * 4; 1982 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]); 1983 1984 bios_wr32(bios, reg, data); 1985 } 1986 1987 return len; 1988} 1989 1990static int 1991init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 1992{ 1993 /* 1994 * INIT_SUB_DIRECT opcode: 0x5B ('[') 1995 * 1996 * offset (8 bit): opcode 1997 * offset + 1 (16 bit): subroutine offset (in bios) 1998 * 1999 * Calls a subroutine that will execute commands until INIT_DONE 2000 * is found. 2001 */ 2002 2003 uint16_t sub_offset = ROM16(bios->data[offset + 1]); 2004 2005 if (!iexec->execute) 2006 return 3; 2007 2008 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n", 2009 offset, sub_offset); 2010 2011 parse_init_table(bios, sub_offset, iexec); 2012 2013 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset); 2014 2015 return 3; 2016} 2017 2018static int 2019init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2020{ 2021 /* 2022 * INIT_I2C_IF opcode: 0x5E ('^') 2023 * 2024 * offset (8 bit): opcode 2025 * offset + 1 (8 bit): DCB I2C table entry index 2026 * offset + 2 (8 bit): I2C slave address 2027 * offset + 3 (8 bit): I2C register 2028 * offset + 4 (8 bit): mask 2029 * offset + 5 (8 bit): data 2030 * 2031 * Read the register given by "I2C register" on the device addressed 2032 * by "I2C slave address" on the I2C bus given by "DCB I2C table 2033 * entry index". Compare the result AND "mask" to "data". 2034 * If they're not equal, skip subsequent opcodes until condition is 2035 * inverted (INIT_NOT), or we hit INIT_RESUME 2036 */ 2037 2038 uint8_t i2c_index = bios->data[offset + 1]; 2039 uint8_t i2c_address = bios->data[offset + 2] >> 1; 2040 uint8_t reg = bios->data[offset + 3]; 2041 uint8_t mask = bios->data[offset + 4]; 2042 uint8_t data = bios->data[offset + 5]; 2043 struct nouveau_i2c_chan *chan; 2044 union i2c_smbus_data val; 2045 int ret; 2046 2047 /* no execute check by design */ 2048 2049 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n", 2050 offset, i2c_index, i2c_address); 2051 2052 chan = init_i2c_device_find(bios->dev, i2c_index); 2053 if (!chan) 2054 return -ENODEV; 2055 2056 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0, 2057 I2C_SMBUS_READ, reg, 2058 I2C_SMBUS_BYTE_DATA, &val); 2059 if (ret < 0) { 2060 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], " 2061 "Mask: 0x%02X, Data: 0x%02X\n", 2062 offset, reg, mask, data); 2063 iexec->execute = 0; 2064 return 6; 2065 } 2066 2067 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, " 2068 "Mask: 0x%02X, Data: 0x%02X\n", 2069 offset, reg, val.byte, mask, data); 2070 2071 iexec->execute = ((val.byte & mask) == data); 2072 2073 return 6; 2074} 2075 2076static int 2077init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2078{ 2079 /* 2080 * INIT_COPY_NV_REG opcode: 0x5F ('_') 2081 * 2082 * offset (8 bit): opcode 2083 * offset + 1 (32 bit): src reg 2084 * offset + 5 (8 bit): shift 2085 * offset + 6 (32 bit): src mask 2086 * offset + 10 (32 bit): xor 2087 * offset + 14 (32 bit): dst reg 2088 * offset + 18 (32 bit): dst mask 2089 * 2090 * Shift REGVAL("src reg") right by (signed) "shift", AND result with 2091 * "src mask", then XOR with "xor". Write this OR'd with 2092 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg" 2093 */ 2094 2095 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1])); 2096 uint8_t shift = bios->data[offset + 5]; 2097 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6])); 2098 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10])); 2099 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14])); 2100 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18])); 2101 uint32_t srcvalue, dstvalue; 2102 2103 if (!iexec->execute) 2104 return 22; 2105 2106 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, " 2107 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n", 2108 offset, srcreg, shift, srcmask, xor, dstreg, dstmask); 2109 2110 srcvalue = bios_rd32(bios, srcreg); 2111 2112 if (shift < 0x80) 2113 srcvalue >>= shift; 2114 else 2115 srcvalue <<= (0x100 - shift); 2116 2117 srcvalue = (srcvalue & srcmask) ^ xor; 2118 2119 dstvalue = bios_rd32(bios, dstreg) & dstmask; 2120 2121 bios_wr32(bios, dstreg, dstvalue | srcvalue); 2122 2123 return 22; 2124} 2125 2126static int 2127init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2128{ 2129 /* 2130 * INIT_ZM_INDEX_IO opcode: 0x62 ('b') 2131 * 2132 * offset (8 bit): opcode 2133 * offset + 1 (16 bit): CRTC port 2134 * offset + 3 (8 bit): CRTC index 2135 * offset + 4 (8 bit): data 2136 * 2137 * Write "data" to index "CRTC index" of "CRTC port" 2138 */ 2139 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2140 uint8_t crtcindex = bios->data[offset + 3]; 2141 uint8_t data = bios->data[offset + 4]; 2142 2143 if (!iexec->execute) 2144 return 5; 2145 2146 bios_idxprt_wr(bios, crtcport, crtcindex, data); 2147 2148 return 5; 2149} 2150 2151static inline void 2152bios_md32(struct nvbios *bios, uint32_t reg, 2153 uint32_t mask, uint32_t val) 2154{ 2155 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val); 2156} 2157 2158static uint32_t 2159peek_fb(struct drm_device *dev, struct io_mapping *fb, 2160 uint32_t off) 2161{ 2162 uint32_t val = 0; 2163 2164 if (off < pci_resource_len(dev->pdev, 1)) { 2165 uint8_t __iomem *p = 2166 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0); 2167 2168 val = ioread32(p + (off & ~PAGE_MASK)); 2169 2170 io_mapping_unmap_atomic(p, KM_USER0); 2171 } 2172 2173 return val; 2174} 2175 2176static void 2177poke_fb(struct drm_device *dev, struct io_mapping *fb, 2178 uint32_t off, uint32_t val) 2179{ 2180 if (off < pci_resource_len(dev->pdev, 1)) { 2181 uint8_t __iomem *p = 2182 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0); 2183 2184 iowrite32(val, p + (off & ~PAGE_MASK)); 2185 wmb(); 2186 2187 io_mapping_unmap_atomic(p, KM_USER0); 2188 } 2189} 2190 2191static inline bool 2192read_back_fb(struct drm_device *dev, struct io_mapping *fb, 2193 uint32_t off, uint32_t val) 2194{ 2195 poke_fb(dev, fb, off, val); 2196 return val == peek_fb(dev, fb, off); 2197} 2198 2199static int 2200nv04_init_compute_mem(struct nvbios *bios) 2201{ 2202 struct drm_device *dev = bios->dev; 2203 uint32_t patt = 0xdeadbeef; 2204 struct io_mapping *fb; 2205 int i; 2206 2207 /* Map the framebuffer aperture */ 2208 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2209 pci_resource_len(dev->pdev, 1)); 2210 if (!fb) 2211 return -ENOMEM; 2212 2213 /* Sequencer and refresh off */ 2214 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); 2215 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); 2216 2217 bios_md32(bios, NV04_PFB_BOOT_0, ~0, 2218 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB | 2219 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2220 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT); 2221 2222 for (i = 0; i < 4; i++) 2223 poke_fb(dev, fb, 4 * i, patt); 2224 2225 poke_fb(dev, fb, 0x400000, patt + 1); 2226 2227 if (peek_fb(dev, fb, 0) == patt + 1) { 2228 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 2229 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT); 2230 bios_md32(bios, NV04_PFB_DEBUG_0, 2231 NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2232 2233 for (i = 0; i < 4; i++) 2234 poke_fb(dev, fb, 4 * i, patt); 2235 2236 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff)) 2237 bios_md32(bios, NV04_PFB_BOOT_0, 2238 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2239 NV04_PFB_BOOT_0_RAM_AMOUNT, 2240 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2241 2242 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) != 2243 (patt & 0xffff0000)) { 2244 bios_md32(bios, NV04_PFB_BOOT_0, 2245 NV04_PFB_BOOT_0_RAM_WIDTH_128 | 2246 NV04_PFB_BOOT_0_RAM_AMOUNT, 2247 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2248 2249 } else if (peek_fb(dev, fb, 0) != patt) { 2250 if (read_back_fb(dev, fb, 0x800000, patt)) 2251 bios_md32(bios, NV04_PFB_BOOT_0, 2252 NV04_PFB_BOOT_0_RAM_AMOUNT, 2253 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2254 else 2255 bios_md32(bios, NV04_PFB_BOOT_0, 2256 NV04_PFB_BOOT_0_RAM_AMOUNT, 2257 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2258 2259 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, 2260 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT); 2261 2262 } else if (!read_back_fb(dev, fb, 0x800000, patt)) { 2263 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2264 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2265 2266 } 2267 2268 /* Refresh on, sequencer on */ 2269 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2270 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); 2271 2272 io_mapping_free(fb); 2273 return 0; 2274} 2275 2276static const uint8_t * 2277nv05_memory_config(struct nvbios *bios) 2278{ 2279 /* Defaults for BIOSes lacking a memory config table */ 2280 static const uint8_t default_config_tab[][2] = { 2281 { 0x24, 0x00 }, 2282 { 0x28, 0x00 }, 2283 { 0x24, 0x01 }, 2284 { 0x1f, 0x00 }, 2285 { 0x0f, 0x00 }, 2286 { 0x17, 0x00 }, 2287 { 0x06, 0x00 }, 2288 { 0x00, 0x00 } 2289 }; 2290 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 2291 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2; 2292 2293 if (bios->legacy.mem_init_tbl_ptr) 2294 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i]; 2295 else 2296 return default_config_tab[i]; 2297} 2298 2299static int 2300nv05_init_compute_mem(struct nvbios *bios) 2301{ 2302 struct drm_device *dev = bios->dev; 2303 const uint8_t *ramcfg = nv05_memory_config(bios); 2304 uint32_t patt = 0xdeadbeef; 2305 struct io_mapping *fb; 2306 int i, v; 2307 2308 /* Map the framebuffer aperture */ 2309 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2310 pci_resource_len(dev->pdev, 1)); 2311 if (!fb) 2312 return -ENOMEM; 2313 2314 /* Sequencer off */ 2315 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20); 2316 2317 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE) 2318 goto out; 2319 2320 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); 2321 2322 /* If present load the hardcoded scrambling table */ 2323 if (bios->legacy.mem_init_tbl_ptr) { 2324 uint32_t *scramble_tab = (uint32_t *)&bios->data[ 2325 bios->legacy.mem_init_tbl_ptr + 0x10]; 2326 2327 for (i = 0; i < 8; i++) 2328 bios_wr32(bios, NV04_PFB_SCRAMBLE(i), 2329 ROM32(scramble_tab[i])); 2330 } 2331 2332 /* Set memory type/width/length defaults depending on the straps */ 2333 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]); 2334 2335 if (ramcfg[1] & 0x80) 2336 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE); 2337 2338 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20); 2339 bios_md32(bios, NV04_PFB_CFG1, 0, 1); 2340 2341 /* Probe memory bus width */ 2342 for (i = 0; i < 4; i++) 2343 poke_fb(dev, fb, 4 * i, patt); 2344 2345 if (peek_fb(dev, fb, 0xc) != patt) 2346 bios_md32(bios, NV04_PFB_BOOT_0, 2347 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0); 2348 2349 /* Probe memory length */ 2350 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT; 2351 2352 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB && 2353 (!read_back_fb(dev, fb, 0x1000000, ++patt) || 2354 !read_back_fb(dev, fb, 0, ++patt))) 2355 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2356 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB); 2357 2358 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB && 2359 !read_back_fb(dev, fb, 0x800000, ++patt)) 2360 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2361 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); 2362 2363 if (!read_back_fb(dev, fb, 0x400000, ++patt)) 2364 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, 2365 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); 2366 2367out: 2368 /* Sequencer on */ 2369 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20); 2370 2371 io_mapping_free(fb); 2372 return 0; 2373} 2374 2375static int 2376nv10_init_compute_mem(struct nvbios *bios) 2377{ 2378 struct drm_device *dev = bios->dev; 2379 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2380 const int mem_width[] = { 0x10, 0x00, 0x20 }; 2381 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2); 2382 uint32_t patt = 0xdeadbeef; 2383 struct io_mapping *fb; 2384 int i, j, k; 2385 2386 /* Map the framebuffer aperture */ 2387 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2388 pci_resource_len(dev->pdev, 1)); 2389 if (!fb) 2390 return -ENOMEM; 2391 2392 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); 2393 2394 /* Probe memory bus width */ 2395 for (i = 0; i < mem_width_count; i++) { 2396 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]); 2397 2398 for (j = 0; j < 4; j++) { 2399 for (k = 0; k < 4; k++) 2400 poke_fb(dev, fb, 0x1c, 0); 2401 2402 poke_fb(dev, fb, 0x1c, patt); 2403 poke_fb(dev, fb, 0x3c, 0); 2404 2405 if (peek_fb(dev, fb, 0x1c) == patt) 2406 goto mem_width_found; 2407 } 2408 } 2409 2410mem_width_found: 2411 patt <<= 1; 2412 2413 /* Probe amount of installed memory */ 2414 for (i = 0; i < 4; i++) { 2415 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000; 2416 2417 poke_fb(dev, fb, off, patt); 2418 poke_fb(dev, fb, 0, 0); 2419 2420 peek_fb(dev, fb, 0); 2421 peek_fb(dev, fb, 0); 2422 peek_fb(dev, fb, 0); 2423 peek_fb(dev, fb, 0); 2424 2425 if (peek_fb(dev, fb, off) == patt) 2426 goto amount_found; 2427 } 2428 2429 /* IC missing - disable the upper half memory space. */ 2430 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0); 2431 2432amount_found: 2433 io_mapping_free(fb); 2434 return 0; 2435} 2436 2437static int 2438nv20_init_compute_mem(struct nvbios *bios) 2439{ 2440 struct drm_device *dev = bios->dev; 2441 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2442 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900); 2443 uint32_t amount, off; 2444 struct io_mapping *fb; 2445 2446 /* Map the framebuffer aperture */ 2447 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1), 2448 pci_resource_len(dev->pdev, 1)); 2449 if (!fb) 2450 return -ENOMEM; 2451 2452 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); 2453 2454 /* Allow full addressing */ 2455 bios_md32(bios, NV04_PFB_CFG0, 0, mask); 2456 2457 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); 2458 for (off = amount; off > 0x2000000; off -= 0x2000000) 2459 poke_fb(dev, fb, off - 4, off); 2460 2461 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA); 2462 if (amount != peek_fb(dev, fb, amount - 4)) 2463 /* IC missing - disable the upper half memory space. */ 2464 bios_md32(bios, NV04_PFB_CFG0, mask, 0); 2465 2466 io_mapping_free(fb); 2467 return 0; 2468} 2469 2470static int 2471init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2472{ 2473 /* 2474 * INIT_COMPUTE_MEM opcode: 0x63 ('c') 2475 * 2476 * offset (8 bit): opcode 2477 * 2478 * This opcode is meant to set the PFB memory config registers 2479 * appropriately so that we can correctly calculate how much VRAM it 2480 * has (on nv10 and better chipsets the amount of installed VRAM is 2481 * subsequently reported in NV_PFB_CSTATUS (0x10020C)). 2482 * 2483 * The implementation of this opcode in general consists of several 2484 * parts: 2485 * 2486 * 1) Determination of memory type and density. Only necessary for 2487 * really old chipsets, the memory type reported by the strap bits 2488 * (0x101000) is assumed to be accurate on nv05 and newer. 2489 * 2490 * 2) Determination of the memory bus width. Usually done by a cunning 2491 * combination of writes to offsets 0x1c and 0x3c in the fb, and 2492 * seeing whether the written values are read back correctly. 2493 * 2494 * Only necessary on nv0x-nv1x and nv34, on the other cards we can 2495 * trust the straps. 2496 * 2497 * 3) Determination of how many of the card's RAM pads have ICs 2498 * attached, usually done by a cunning combination of writes to an 2499 * offset slightly less than the maximum memory reported by 2500 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back. 2501 * 2502 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io 2503 * logs of the VBIOS and kmmio traces of the binary driver POSTing the 2504 * card show nothing being done for this opcode. Why is it still listed 2505 * in the table?! 2506 */ 2507 2508 /* no iexec->execute check by design */ 2509 2510 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2511 int ret; 2512 2513 if (dev_priv->chipset >= 0x40 || 2514 dev_priv->chipset == 0x1a || 2515 dev_priv->chipset == 0x1f) 2516 ret = 0; 2517 else if (dev_priv->chipset >= 0x20 && 2518 dev_priv->chipset != 0x34) 2519 ret = nv20_init_compute_mem(bios); 2520 else if (dev_priv->chipset >= 0x10) 2521 ret = nv10_init_compute_mem(bios); 2522 else if (dev_priv->chipset >= 0x5) 2523 ret = nv05_init_compute_mem(bios); 2524 else 2525 ret = nv04_init_compute_mem(bios); 2526 2527 if (ret) 2528 return ret; 2529 2530 return 1; 2531} 2532 2533static int 2534init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2535{ 2536 /* 2537 * INIT_RESET opcode: 0x65 ('e') 2538 * 2539 * offset (8 bit): opcode 2540 * offset + 1 (32 bit): register 2541 * offset + 5 (32 bit): value1 2542 * offset + 9 (32 bit): value2 2543 * 2544 * Assign "value1" to "register", then assign "value2" to "register" 2545 */ 2546 2547 uint32_t reg = ROM32(bios->data[offset + 1]); 2548 uint32_t value1 = ROM32(bios->data[offset + 5]); 2549 uint32_t value2 = ROM32(bios->data[offset + 9]); 2550 uint32_t pci_nv_19, pci_nv_20; 2551 2552 /* no iexec->execute check by design */ 2553 2554 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19); 2555 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00); 2556 2557 bios_wr32(bios, reg, value1); 2558 2559 udelay(10); 2560 2561 bios_wr32(bios, reg, value2); 2562 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19); 2563 2564 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20); 2565 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */ 2566 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20); 2567 2568 return 13; 2569} 2570 2571static int 2572init_configure_mem(struct nvbios *bios, uint16_t offset, 2573 struct init_exec *iexec) 2574{ 2575 /* 2576 * INIT_CONFIGURE_MEM opcode: 0x66 ('f') 2577 * 2578 * offset (8 bit): opcode 2579 * 2580 * Equivalent to INIT_DONE on bios version 3 or greater. 2581 * For early bios versions, sets up the memory registers, using values 2582 * taken from the memory init table 2583 */ 2584 2585 /* no iexec->execute check by design */ 2586 2587 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2588 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6; 2589 uint32_t reg, data; 2590 2591 if (bios->major_version > 2) 2592 return 0; 2593 2594 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd( 2595 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20); 2596 2597 if (bios->data[meminitoffs] & 1) 2598 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr; 2599 2600 for (reg = ROM32(bios->data[seqtbloffs]); 2601 reg != 0xffffffff; 2602 reg = ROM32(bios->data[seqtbloffs += 4])) { 2603 2604 switch (reg) { 2605 case NV04_PFB_PRE: 2606 data = NV04_PFB_PRE_CMD_PRECHARGE; 2607 break; 2608 case NV04_PFB_PAD: 2609 data = NV04_PFB_PAD_CKE_NORMAL; 2610 break; 2611 case NV04_PFB_REF: 2612 data = NV04_PFB_REF_CMD_REFRESH; 2613 break; 2614 default: 2615 data = ROM32(bios->data[meminitdata]); 2616 meminitdata += 4; 2617 if (data == 0xffffffff) 2618 continue; 2619 } 2620 2621 bios_wr32(bios, reg, data); 2622 } 2623 2624 return 1; 2625} 2626 2627static int 2628init_configure_clk(struct nvbios *bios, uint16_t offset, 2629 struct init_exec *iexec) 2630{ 2631 /* 2632 * INIT_CONFIGURE_CLK opcode: 0x67 ('g') 2633 * 2634 * offset (8 bit): opcode 2635 * 2636 * Equivalent to INIT_DONE on bios version 3 or greater. 2637 * For early bios versions, sets up the NVClk and MClk PLLs, using 2638 * values taken from the memory init table 2639 */ 2640 2641 /* no iexec->execute check by design */ 2642 2643 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4); 2644 int clock; 2645 2646 if (bios->major_version > 2) 2647 return 0; 2648 2649 clock = ROM16(bios->data[meminitoffs + 4]) * 10; 2650 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock); 2651 2652 clock = ROM16(bios->data[meminitoffs + 2]) * 10; 2653 if (bios->data[meminitoffs] & 1) /* DDR */ 2654 clock *= 2; 2655 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock); 2656 2657 return 1; 2658} 2659 2660static int 2661init_configure_preinit(struct nvbios *bios, uint16_t offset, 2662 struct init_exec *iexec) 2663{ 2664 /* 2665 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h') 2666 * 2667 * offset (8 bit): opcode 2668 * 2669 * Equivalent to INIT_DONE on bios version 3 or greater. 2670 * For early bios versions, does early init, loading ram and crystal 2671 * configuration from straps into CR3C 2672 */ 2673 2674 /* no iexec->execute check by design */ 2675 2676 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 2677 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6; 2678 2679 if (bios->major_version > 2) 2680 return 0; 2681 2682 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, 2683 NV_CIO_CRE_SCRATCH4__INDEX, cr3c); 2684 2685 return 1; 2686} 2687 2688static int 2689init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2690{ 2691 /* 2692 * INIT_IO opcode: 0x69 ('i') 2693 * 2694 * offset (8 bit): opcode 2695 * offset + 1 (16 bit): CRTC port 2696 * offset + 3 (8 bit): mask 2697 * offset + 4 (8 bit): data 2698 * 2699 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port" 2700 */ 2701 2702 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 2703 uint16_t crtcport = ROM16(bios->data[offset + 1]); 2704 uint8_t mask = bios->data[offset + 3]; 2705 uint8_t data = bios->data[offset + 4]; 2706 2707 if (!iexec->execute) 2708 return 5; 2709 2710 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n", 2711 offset, crtcport, mask, data); 2712 2713 /* 2714 * I have no idea what this does, but NVIDIA do this magic sequence 2715 * in the places where this INIT_IO happens.. 2716 */ 2717 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) { 2718 int i; 2719 2720 bios_wr32(bios, 0x614100, (bios_rd32( 2721 bios, 0x614100) & 0x0fffffff) | 0x00800000); 2722 2723 bios_wr32(bios, 0x00e18c, bios_rd32( 2724 bios, 0x00e18c) | 0x00020000); 2725 2726 bios_wr32(bios, 0x614900, (bios_rd32( 2727 bios, 0x614900) & 0x0fffffff) | 0x00800000); 2728 2729 bios_wr32(bios, 0x000200, bios_rd32( 2730 bios, 0x000200) & ~0x40000000); 2731 2732 mdelay(10); 2733 2734 bios_wr32(bios, 0x00e18c, bios_rd32( 2735 bios, 0x00e18c) & ~0x00020000); 2736 2737 bios_wr32(bios, 0x000200, bios_rd32( 2738 bios, 0x000200) | 0x40000000); 2739 2740 bios_wr32(bios, 0x614100, 0x00800018); 2741 bios_wr32(bios, 0x614900, 0x00800018); 2742 2743 mdelay(10); 2744 2745 bios_wr32(bios, 0x614100, 0x10000018); 2746 bios_wr32(bios, 0x614900, 0x10000018); 2747 2748 for (i = 0; i < 3; i++) 2749 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32( 2750 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0); 2751 2752 for (i = 0; i < 2; i++) 2753 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32( 2754 bios, 0x614300 + (i*0x800)) & 0xfffff0f0); 2755 2756 for (i = 0; i < 3; i++) 2757 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32( 2758 bios, 0x614380 + (i*0x800)) & 0xfffff0f0); 2759 2760 for (i = 0; i < 2; i++) 2761 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32( 2762 bios, 0x614200 + (i*0x800)) & 0xfffffff0); 2763 2764 for (i = 0; i < 2; i++) 2765 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32( 2766 bios, 0x614108 + (i*0x800)) & 0x0fffffff); 2767 return 5; 2768 } 2769 2770 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) | 2771 data); 2772 return 5; 2773} 2774 2775static int 2776init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2777{ 2778 /* 2779 * INIT_SUB opcode: 0x6B ('k') 2780 * 2781 * offset (8 bit): opcode 2782 * offset + 1 (8 bit): script number 2783 * 2784 * Execute script number "script number", as a subroutine 2785 */ 2786 2787 uint8_t sub = bios->data[offset + 1]; 2788 2789 if (!iexec->execute) 2790 return 2; 2791 2792 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub); 2793 2794 parse_init_table(bios, 2795 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]), 2796 iexec); 2797 2798 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub); 2799 2800 return 2; 2801} 2802 2803static int 2804init_ram_condition(struct nvbios *bios, uint16_t offset, 2805 struct init_exec *iexec) 2806{ 2807 /* 2808 * INIT_RAM_CONDITION opcode: 0x6D ('m') 2809 * 2810 * offset (8 bit): opcode 2811 * offset + 1 (8 bit): mask 2812 * offset + 2 (8 bit): cmpval 2813 * 2814 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval". 2815 * If condition not met skip subsequent opcodes until condition is 2816 * inverted (INIT_NOT), or we hit INIT_RESUME 2817 */ 2818 2819 uint8_t mask = bios->data[offset + 1]; 2820 uint8_t cmpval = bios->data[offset + 2]; 2821 uint8_t data; 2822 2823 if (!iexec->execute) 2824 return 3; 2825 2826 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask; 2827 2828 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 2829 offset, data, cmpval); 2830 2831 if (data == cmpval) 2832 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2833 else { 2834 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 2835 iexec->execute = false; 2836 } 2837 2838 return 3; 2839} 2840 2841static int 2842init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2843{ 2844 /* 2845 * INIT_NV_REG opcode: 0x6E ('n') 2846 * 2847 * offset (8 bit): opcode 2848 * offset + 1 (32 bit): register 2849 * offset + 5 (32 bit): mask 2850 * offset + 9 (32 bit): data 2851 * 2852 * Assign ((REGVAL("register") & "mask") | "data") to "register" 2853 */ 2854 2855 uint32_t reg = ROM32(bios->data[offset + 1]); 2856 uint32_t mask = ROM32(bios->data[offset + 5]); 2857 uint32_t data = ROM32(bios->data[offset + 9]); 2858 2859 if (!iexec->execute) 2860 return 13; 2861 2862 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n", 2863 offset, reg, mask, data); 2864 2865 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data); 2866 2867 return 13; 2868} 2869 2870static int 2871init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2872{ 2873 /* 2874 * INIT_MACRO opcode: 0x6F ('o') 2875 * 2876 * offset (8 bit): opcode 2877 * offset + 1 (8 bit): macro number 2878 * 2879 * Look up macro index "macro number" in the macro index table. 2880 * The macro index table entry has 1 byte for the index in the macro 2881 * table, and 1 byte for the number of times to repeat the macro. 2882 * The macro table entry has 4 bytes for the register address and 2883 * 4 bytes for the value to write to that register 2884 */ 2885 2886 uint8_t macro_index_tbl_idx = bios->data[offset + 1]; 2887 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE); 2888 uint8_t macro_tbl_idx = bios->data[tmp]; 2889 uint8_t count = bios->data[tmp + 1]; 2890 uint32_t reg, data; 2891 int i; 2892 2893 if (!iexec->execute) 2894 return 2; 2895 2896 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, " 2897 "Count: 0x%02X\n", 2898 offset, macro_index_tbl_idx, macro_tbl_idx, count); 2899 2900 for (i = 0; i < count; i++) { 2901 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE; 2902 2903 reg = ROM32(bios->data[macroentryptr]); 2904 data = ROM32(bios->data[macroentryptr + 4]); 2905 2906 bios_wr32(bios, reg, data); 2907 } 2908 2909 return 2; 2910} 2911 2912static int 2913init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2914{ 2915 /* 2916 * INIT_DONE opcode: 0x71 ('q') 2917 * 2918 * offset (8 bit): opcode 2919 * 2920 * End the current script 2921 */ 2922 2923 /* mild retval abuse to stop parsing this table */ 2924 return 0; 2925} 2926 2927static int 2928init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2929{ 2930 /* 2931 * INIT_RESUME opcode: 0x72 ('r') 2932 * 2933 * offset (8 bit): opcode 2934 * 2935 * End the current execute / no-execute condition 2936 */ 2937 2938 if (iexec->execute) 2939 return 1; 2940 2941 iexec->execute = true; 2942 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset); 2943 2944 return 1; 2945} 2946 2947static int 2948init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2949{ 2950 /* 2951 * INIT_TIME opcode: 0x74 ('t') 2952 * 2953 * offset (8 bit): opcode 2954 * offset + 1 (16 bit): time 2955 * 2956 * Sleep for "time" microseconds. 2957 */ 2958 2959 unsigned time = ROM16(bios->data[offset + 1]); 2960 2961 if (!iexec->execute) 2962 return 3; 2963 2964 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n", 2965 offset, time); 2966 2967 if (time < 1000) 2968 udelay(time); 2969 else 2970 msleep((time + 900) / 1000); 2971 2972 return 3; 2973} 2974 2975static int 2976init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 2977{ 2978 /* 2979 * INIT_CONDITION opcode: 0x75 ('u') 2980 * 2981 * offset (8 bit): opcode 2982 * offset + 1 (8 bit): condition number 2983 * 2984 * Check condition "condition number" in the condition table. 2985 * If condition not met skip subsequent opcodes until condition is 2986 * inverted (INIT_NOT), or we hit INIT_RESUME 2987 */ 2988 2989 uint8_t cond = bios->data[offset + 1]; 2990 2991 if (!iexec->execute) 2992 return 2; 2993 2994 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond); 2995 2996 if (bios_condition_met(bios, offset, cond)) 2997 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 2998 else { 2999 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 3000 iexec->execute = false; 3001 } 3002 3003 return 2; 3004} 3005 3006static int 3007init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3008{ 3009 /* 3010 * INIT_IO_CONDITION opcode: 0x76 3011 * 3012 * offset (8 bit): opcode 3013 * offset + 1 (8 bit): condition number 3014 * 3015 * Check condition "condition number" in the io condition table. 3016 * If condition not met skip subsequent opcodes until condition is 3017 * inverted (INIT_NOT), or we hit INIT_RESUME 3018 */ 3019 3020 uint8_t cond = bios->data[offset + 1]; 3021 3022 if (!iexec->execute) 3023 return 2; 3024 3025 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond); 3026 3027 if (io_condition_met(bios, offset, cond)) 3028 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset); 3029 else { 3030 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset); 3031 iexec->execute = false; 3032 } 3033 3034 return 2; 3035} 3036 3037static int 3038init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3039{ 3040 /* 3041 * INIT_INDEX_IO opcode: 0x78 ('x') 3042 * 3043 * offset (8 bit): opcode 3044 * offset + 1 (16 bit): CRTC port 3045 * offset + 3 (8 bit): CRTC index 3046 * offset + 4 (8 bit): mask 3047 * offset + 5 (8 bit): data 3048 * 3049 * Read value at index "CRTC index" on "CRTC port", AND with "mask", 3050 * OR with "data", write-back 3051 */ 3052 3053 uint16_t crtcport = ROM16(bios->data[offset + 1]); 3054 uint8_t crtcindex = bios->data[offset + 3]; 3055 uint8_t mask = bios->data[offset + 4]; 3056 uint8_t data = bios->data[offset + 5]; 3057 uint8_t value; 3058 3059 if (!iexec->execute) 3060 return 6; 3061 3062 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, " 3063 "Data: 0x%02X\n", 3064 offset, crtcport, crtcindex, mask, data); 3065 3066 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data; 3067 bios_idxprt_wr(bios, crtcport, crtcindex, value); 3068 3069 return 6; 3070} 3071 3072static int 3073init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3074{ 3075 /* 3076 * INIT_PLL opcode: 0x79 ('y') 3077 * 3078 * offset (8 bit): opcode 3079 * offset + 1 (32 bit): register 3080 * offset + 5 (16 bit): freq 3081 * 3082 * Set PLL register "register" to coefficients for frequency (10kHz) 3083 * "freq" 3084 */ 3085 3086 uint32_t reg = ROM32(bios->data[offset + 1]); 3087 uint16_t freq = ROM16(bios->data[offset + 5]); 3088 3089 if (!iexec->execute) 3090 return 7; 3091 3092 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq); 3093 3094 setPLL(bios, reg, freq * 10); 3095 3096 return 7; 3097} 3098 3099static int 3100init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3101{ 3102 /* 3103 * INIT_ZM_REG opcode: 0x7A ('z') 3104 * 3105 * offset (8 bit): opcode 3106 * offset + 1 (32 bit): register 3107 * offset + 5 (32 bit): value 3108 * 3109 * Assign "value" to "register" 3110 */ 3111 3112 uint32_t reg = ROM32(bios->data[offset + 1]); 3113 uint32_t value = ROM32(bios->data[offset + 5]); 3114 3115 if (!iexec->execute) 3116 return 9; 3117 3118 if (reg == 0x000200) 3119 value |= 1; 3120 3121 bios_wr32(bios, reg, value); 3122 3123 return 9; 3124} 3125 3126static int 3127init_ram_restrict_pll(struct nvbios *bios, uint16_t offset, 3128 struct init_exec *iexec) 3129{ 3130 /* 3131 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('') 3132 * 3133 * offset (8 bit): opcode 3134 * offset + 1 (8 bit): PLL type 3135 * offset + 2 (32 bit): frequency 0 3136 * 3137 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 3138 * ram_restrict_table_ptr. The value read from there is used to select 3139 * a frequency from the table starting at 'frequency 0' to be 3140 * programmed into the PLL corresponding to 'type'. 3141 * 3142 * The PLL limits table on cards using this opcode has a mapping of 3143 * 'type' to the relevant registers. 3144 */ 3145 3146 struct drm_device *dev = bios->dev; 3147 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2; 3148 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap]; 3149 uint8_t type = bios->data[offset + 1]; 3150 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]); 3151 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry; 3152 int len = 2 + bios->ram_restrict_group_count * 4; 3153 int i; 3154 3155 if (!iexec->execute) 3156 return len; 3157 3158 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) { 3159 NV_ERROR(dev, "PLL limits table not version 3.x\n"); 3160 return len; /* deliberate, allow default clocks to remain */ 3161 } 3162 3163 entry = pll_limits + pll_limits[1]; 3164 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) { 3165 if (entry[0] == type) { 3166 uint32_t reg = ROM32(entry[3]); 3167 3168 BIOSLOG(bios, "0x%04X: " 3169 "Type %02x Reg 0x%08x Freq %dKHz\n", 3170 offset, type, reg, freq); 3171 3172 setPLL(bios, reg, freq); 3173 return len; 3174 } 3175 } 3176 3177 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type); 3178 return len; 3179} 3180 3181static int 3182init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3183{ 3184 /* 3185 * INIT_8C opcode: 0x8C ('') 3186 * 3187 * NOP so far.... 3188 * 3189 */ 3190 3191 return 1; 3192} 3193 3194static int 3195init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3196{ 3197 /* 3198 * INIT_8D opcode: 0x8D ('') 3199 * 3200 * NOP so far.... 3201 * 3202 */ 3203 3204 return 1; 3205} 3206 3207static int 3208init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3209{ 3210 /* 3211 * INIT_GPIO opcode: 0x8E ('') 3212 * 3213 * offset (8 bit): opcode 3214 * 3215 * Loop over all entries in the DCB GPIO table, and initialise 3216 * each GPIO according to various values listed in each entry 3217 */ 3218 3219 struct drm_nouveau_private *dev_priv = bios->dev->dev_private; 3220 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; 3221 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; 3222 int i; 3223 3224 if (dev_priv->card_type < NV_50) { 3225 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n"); 3226 return 1; 3227 } 3228 3229 if (!iexec->execute) 3230 return 1; 3231 3232 for (i = 0; i < bios->dcb.gpio.entries; i++) { 3233 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i]; 3234 uint32_t r, s, v; 3235 3236 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry); 3237 3238 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n", 3239 offset, gpio->tag, gpio->state_default); 3240 if (bios->execute) 3241 pgpio->set(bios->dev, gpio->tag, gpio->state_default); 3242 3243 /* The NVIDIA binary driver doesn't appear to actually do 3244 * any of this, my VBIOS does however. 3245 */ 3246 /* Not a clue, needs de-magicing */ 3247 r = nv50_gpio_ctl[gpio->line >> 4]; 3248 s = (gpio->line & 0x0f); 3249 v = bios_rd32(bios, r) & ~(0x00010001 << s); 3250 switch ((gpio->entry & 0x06000000) >> 25) { 3251 case 1: 3252 v |= (0x00000001 << s); 3253 break; 3254 case 2: 3255 v |= (0x00010000 << s); 3256 break; 3257 default: 3258 break; 3259 } 3260 bios_wr32(bios, r, v); 3261 } 3262 3263 return 1; 3264} 3265 3266static int 3267init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset, 3268 struct init_exec *iexec) 3269{ 3270 /* 3271 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('') 3272 * 3273 * offset (8 bit): opcode 3274 * offset + 1 (32 bit): reg 3275 * offset + 5 (8 bit): regincrement 3276 * offset + 6 (8 bit): count 3277 * offset + 7 (32 bit): value 1,1 3278 * ... 3279 * 3280 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at 3281 * ram_restrict_table_ptr. The value read from here is 'n', and 3282 * "value 1,n" gets written to "reg". This repeats "count" times and on 3283 * each iteration 'm', "reg" increases by "regincrement" and 3284 * "value m,n" is used. The extent of n is limited by a number read 3285 * from the 'M' BIT table, herein called "blocklen" 3286 */ 3287 3288 uint32_t reg = ROM32(bios->data[offset + 1]); 3289 uint8_t regincrement = bios->data[offset + 5]; 3290 uint8_t count = bios->data[offset + 6]; 3291 uint32_t strap_ramcfg, data; 3292 /* previously set by 'M' BIT table */ 3293 uint16_t blocklen = bios->ram_restrict_group_count * 4; 3294 int len = 7 + count * blocklen; 3295 uint8_t index; 3296 int i; 3297 3298 /* critical! to know the length of the opcode */; 3299 if (!blocklen) { 3300 NV_ERROR(bios->dev, 3301 "0x%04X: Zero block length - has the M table " 3302 "been parsed?\n", offset); 3303 return -EINVAL; 3304 } 3305 3306 if (!iexec->execute) 3307 return len; 3308 3309 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf; 3310 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg]; 3311 3312 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, " 3313 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n", 3314 offset, reg, regincrement, count, strap_ramcfg, index); 3315 3316 for (i = 0; i < count; i++) { 3317 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]); 3318 3319 bios_wr32(bios, reg, data); 3320 3321 reg += regincrement; 3322 } 3323 3324 return len; 3325} 3326 3327static int 3328init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3329{ 3330 /* 3331 * INIT_COPY_ZM_REG opcode: 0x90 ('') 3332 * 3333 * offset (8 bit): opcode 3334 * offset + 1 (32 bit): src reg 3335 * offset + 5 (32 bit): dst reg 3336 * 3337 * Put contents of "src reg" into "dst reg" 3338 */ 3339 3340 uint32_t srcreg = ROM32(bios->data[offset + 1]); 3341 uint32_t dstreg = ROM32(bios->data[offset + 5]); 3342 3343 if (!iexec->execute) 3344 return 9; 3345 3346 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg)); 3347 3348 return 9; 3349} 3350 3351static int 3352init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset, 3353 struct init_exec *iexec) 3354{ 3355 /* 3356 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('') 3357 * 3358 * offset (8 bit): opcode 3359 * offset + 1 (32 bit): dst reg 3360 * offset + 5 (8 bit): count 3361 * offset + 6 (32 bit): data 1 3362 * ... 3363 * 3364 * For each of "count" values write "data n" to "dst reg" 3365 */ 3366 3367 uint32_t reg = ROM32(bios->data[offset + 1]); 3368 uint8_t count = bios->data[offset + 5]; 3369 int len = 6 + count * 4; 3370 int i; 3371 3372 if (!iexec->execute) 3373 return len; 3374 3375 for (i = 0; i < count; i++) { 3376 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]); 3377 bios_wr32(bios, reg, data); 3378 } 3379 3380 return len; 3381} 3382 3383static int 3384init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3385{ 3386 /* 3387 * INIT_RESERVED opcode: 0x92 ('') 3388 * 3389 * offset (8 bit): opcode 3390 * 3391 * Seemingly does nothing 3392 */ 3393 3394 return 1; 3395} 3396 3397static int 3398init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3399{ 3400 /* 3401 * INIT_96 opcode: 0x96 ('') 3402 * 3403 * offset (8 bit): opcode 3404 * offset + 1 (32 bit): sreg 3405 * offset + 5 (8 bit): sshift 3406 * offset + 6 (8 bit): smask 3407 * offset + 7 (8 bit): index 3408 * offset + 8 (32 bit): reg 3409 * offset + 12 (32 bit): mask 3410 * offset + 16 (8 bit): shift 3411 * 3412 */ 3413 3414 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2); 3415 uint32_t reg = ROM32(bios->data[offset + 8]); 3416 uint32_t mask = ROM32(bios->data[offset + 12]); 3417 uint32_t val; 3418 3419 val = bios_rd32(bios, ROM32(bios->data[offset + 1])); 3420 if (bios->data[offset + 5] < 0x80) 3421 val >>= bios->data[offset + 5]; 3422 else 3423 val <<= (0x100 - bios->data[offset + 5]); 3424 val &= bios->data[offset + 6]; 3425 3426 val = bios->data[ROM16(bios->data[xlatptr]) + val]; 3427 val <<= bios->data[offset + 16]; 3428 3429 if (!iexec->execute) 3430 return 17; 3431 3432 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val); 3433 return 17; 3434} 3435 3436static int 3437init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3438{ 3439 /* 3440 * INIT_97 opcode: 0x97 ('') 3441 * 3442 * offset (8 bit): opcode 3443 * offset + 1 (32 bit): register 3444 * offset + 5 (32 bit): mask 3445 * offset + 9 (32 bit): value 3446 * 3447 * Adds "value" to "register" preserving the fields specified 3448 * by "mask" 3449 */ 3450 3451 uint32_t reg = ROM32(bios->data[offset + 1]); 3452 uint32_t mask = ROM32(bios->data[offset + 5]); 3453 uint32_t add = ROM32(bios->data[offset + 9]); 3454 uint32_t val; 3455 3456 val = bios_rd32(bios, reg); 3457 val = (val & mask) | ((val + add) & ~mask); 3458 3459 if (!iexec->execute) 3460 return 13; 3461 3462 bios_wr32(bios, reg, val); 3463 return 13; 3464} 3465 3466static int 3467init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3468{ 3469 /* 3470 * INIT_AUXCH opcode: 0x98 ('') 3471 * 3472 * offset (8 bit): opcode 3473 * offset + 1 (32 bit): address 3474 * offset + 5 (8 bit): count 3475 * offset + 6 (8 bit): mask 0 3476 * offset + 7 (8 bit): data 0 3477 * ... 3478 * 3479 */ 3480 3481 struct drm_device *dev = bios->dev; 3482 struct nouveau_i2c_chan *auxch; 3483 uint32_t addr = ROM32(bios->data[offset + 1]); 3484 uint8_t count = bios->data[offset + 5]; 3485 int len = 6 + count * 2; 3486 int ret, i; 3487 3488 if (!bios->display.output) { 3489 NV_ERROR(dev, "INIT_AUXCH: no active output\n"); 3490 return len; 3491 } 3492 3493 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3494 if (!auxch) { 3495 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n", 3496 bios->display.output->i2c_index); 3497 return len; 3498 } 3499 3500 if (!iexec->execute) 3501 return len; 3502 3503 offset += 6; 3504 for (i = 0; i < count; i++, offset += 2) { 3505 uint8_t data; 3506 3507 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1); 3508 if (ret) { 3509 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret); 3510 return len; 3511 } 3512 3513 data &= bios->data[offset + 0]; 3514 data |= bios->data[offset + 1]; 3515 3516 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1); 3517 if (ret) { 3518 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret); 3519 return len; 3520 } 3521 } 3522 3523 return len; 3524} 3525 3526static int 3527init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3528{ 3529 /* 3530 * INIT_ZM_AUXCH opcode: 0x99 ('') 3531 * 3532 * offset (8 bit): opcode 3533 * offset + 1 (32 bit): address 3534 * offset + 5 (8 bit): count 3535 * offset + 6 (8 bit): data 0 3536 * ... 3537 * 3538 */ 3539 3540 struct drm_device *dev = bios->dev; 3541 struct nouveau_i2c_chan *auxch; 3542 uint32_t addr = ROM32(bios->data[offset + 1]); 3543 uint8_t count = bios->data[offset + 5]; 3544 int len = 6 + count; 3545 int ret, i; 3546 3547 if (!bios->display.output) { 3548 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n"); 3549 return len; 3550 } 3551 3552 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index); 3553 if (!auxch) { 3554 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n", 3555 bios->display.output->i2c_index); 3556 return len; 3557 } 3558 3559 if (!iexec->execute) 3560 return len; 3561 3562 offset += 6; 3563 for (i = 0; i < count; i++, offset++) { 3564 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1); 3565 if (ret) { 3566 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret); 3567 return len; 3568 } 3569 } 3570 3571 return len; 3572} 3573 3574static int 3575init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) 3576{ 3577 /* 3578 * INIT_I2C_LONG_IF opcode: 0x9A ('') 3579 * 3580 * offset (8 bit): opcode 3581 * offset + 1 (8 bit): DCB I2C table entry index 3582 * offset + 2 (8 bit): I2C slave address 3583 * offset + 3 (16 bit): I2C register 3584 * offset + 5 (8 bit): mask 3585 * offset + 6 (8 bit): data 3586 * 3587 * Read the register given by "I2C register" on the device addressed 3588 * by "I2C slave address" on the I2C bus given by "DCB I2C table 3589 * entry index". Compare the result AND "mask" to "data". 3590 * If they're not equal, skip subsequent opcodes until condition is 3591 * inverted (INIT_NOT), or we hit INIT_RESUME 3592 */ 3593 3594 uint8_t i2c_index = bios->data[offset + 1]; 3595 uint8_t i2c_address = bios->data[offset + 2] >> 1; 3596 uint8_t reglo = bios->data[offset + 3]; 3597 uint8_t reghi = bios->data[offset + 4]; 3598 uint8_t mask = bios->data[offset + 5]; 3599 uint8_t data = bios->data[offset + 6]; 3600 struct nouveau_i2c_chan *chan; 3601 uint8_t buf0[2] = { reghi, reglo }; 3602 uint8_t buf1[1]; 3603 struct i2c_msg msg[2] = { 3604 { i2c_address, 0, 1, buf0 }, 3605 { i2c_address, I2C_M_RD, 1, buf1 }, 3606 }; 3607 int ret; 3608 3609 /* no execute check by design */ 3610 3611 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n", 3612 offset, i2c_index, i2c_address); 3613 3614 chan = init_i2c_device_find(bios->dev, i2c_index); 3615 if (!chan) 3616 return -ENODEV; 3617 3618 3619 ret = i2c_transfer(&chan->adapter, msg, 2); 3620 if (ret < 0) { 3621 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], " 3622 "Mask: 0x%02X, Data: 0x%02X\n", 3623 offset, reghi, reglo, mask, data); 3624 iexec->execute = 0; 3625 return 7; 3626 } 3627 3628 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, " 3629 "Mask: 0x%02X, Data: 0x%02X\n", 3630 offset, reghi, reglo, buf1[0], mask, data); 3631 3632 iexec->execute = ((buf1[0] & mask) == data); 3633 3634 return 7; 3635} 3636 3637static struct init_tbl_entry itbl_entry[] = { 3638 /* command name , id , length , offset , mult , command handler */ 3639 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */ 3640 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog }, 3641 { "INIT_REPEAT" , 0x33, init_repeat }, 3642 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll }, 3643 { "INIT_END_REPEAT" , 0x36, init_end_repeat }, 3644 { "INIT_COPY" , 0x37, init_copy }, 3645 { "INIT_NOT" , 0x38, init_not }, 3646 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition }, 3647 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition }, 3648 { "INIT_OP_3B" , 0x3B, init_op_3b }, 3649 { "INIT_OP_3C" , 0x3C, init_op_3c }, 3650 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched }, 3651 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 }, 3652 { "INIT_PLL2" , 0x4B, init_pll2 }, 3653 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte }, 3654 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte }, 3655 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c }, 3656 { "INIT_TMDS" , 0x4F, init_tmds }, 3657 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group }, 3658 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch }, 3659 { "INIT_CR" , 0x52, init_cr }, 3660 { "INIT_ZM_CR" , 0x53, init_zm_cr }, 3661 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group }, 3662 { "INIT_CONDITION_TIME" , 0x56, init_condition_time }, 3663 { "INIT_LTIME" , 0x57, init_ltime }, 3664 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence }, 3665 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */ 3666 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct }, 3667 { "INIT_I2C_IF" , 0x5E, init_i2c_if }, 3668 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg }, 3669 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io }, 3670 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem }, 3671 { "INIT_RESET" , 0x65, init_reset }, 3672 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem }, 3673 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk }, 3674 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit }, 3675 { "INIT_IO" , 0x69, init_io }, 3676 { "INIT_SUB" , 0x6B, init_sub }, 3677 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition }, 3678 { "INIT_NV_REG" , 0x6E, init_nv_reg }, 3679 { "INIT_MACRO" , 0x6F, init_macro }, 3680 { "INIT_DONE" , 0x71, init_done }, 3681 { "INIT_RESUME" , 0x72, init_resume }, 3682 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */ 3683 { "INIT_TIME" , 0x74, init_time }, 3684 { "INIT_CONDITION" , 0x75, init_condition }, 3685 { "INIT_IO_CONDITION" , 0x76, init_io_condition }, 3686 { "INIT_INDEX_IO" , 0x78, init_index_io }, 3687 { "INIT_PLL" , 0x79, init_pll }, 3688 { "INIT_ZM_REG" , 0x7A, init_zm_reg }, 3689 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll }, 3690 { "INIT_8C" , 0x8C, init_8c }, 3691 { "INIT_8D" , 0x8D, init_8d }, 3692 { "INIT_GPIO" , 0x8E, init_gpio }, 3693 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group }, 3694 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg }, 3695 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched }, 3696 { "INIT_RESERVED" , 0x92, init_reserved }, 3697 { "INIT_96" , 0x96, init_96 }, 3698 { "INIT_97" , 0x97, init_97 }, 3699 { "INIT_AUXCH" , 0x98, init_auxch }, 3700 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch }, 3701 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if }, 3702 { NULL , 0 , NULL } 3703}; 3704 3705#define MAX_TABLE_OPS 1000 3706 3707static int 3708parse_init_table(struct nvbios *bios, unsigned int offset, 3709 struct init_exec *iexec) 3710{ 3711 /* 3712 * Parses all commands in an init table. 3713 * 3714 * We start out executing all commands found in the init table. Some 3715 * opcodes may change the status of iexec->execute to SKIP, which will 3716 * cause the following opcodes to perform no operation until the value 3717 * is changed back to EXECUTE. 3718 */ 3719 3720 int count = 0, i, ret; 3721 uint8_t id; 3722 3723 /* 3724 * Loop until INIT_DONE causes us to break out of the loop 3725 * (or until offset > bios length just in case... ) 3726 * (and no more than MAX_TABLE_OPS iterations, just in case... ) 3727 */ 3728 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) { 3729 id = bios->data[offset]; 3730 3731 /* Find matching id in itbl_entry */ 3732 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++) 3733 ; 3734 3735 if (!itbl_entry[i].name) { 3736 NV_ERROR(bios->dev, 3737 "0x%04X: Init table command not found: " 3738 "0x%02X\n", offset, id); 3739 return -ENOENT; 3740 } 3741 3742 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset, 3743 itbl_entry[i].id, itbl_entry[i].name); 3744 3745 /* execute eventual command handler */ 3746 ret = (*itbl_entry[i].handler)(bios, offset, iexec); 3747 if (ret < 0) { 3748 NV_ERROR(bios->dev, "0x%04X: Failed parsing init " 3749 "table opcode: %s %d\n", offset, 3750 itbl_entry[i].name, ret); 3751 } 3752 3753 if (ret <= 0) 3754 break; 3755 3756 /* 3757 * Add the offset of the current command including all data 3758 * of that command. The offset will then be pointing on the 3759 * next op code. 3760 */ 3761 offset += ret; 3762 } 3763 3764 if (offset >= bios->length) 3765 NV_WARN(bios->dev, 3766 "Offset 0x%04X greater than known bios image length. " 3767 "Corrupt image?\n", offset); 3768 if (count >= MAX_TABLE_OPS) 3769 NV_WARN(bios->dev, 3770 "More than %d opcodes to a table is unlikely, " 3771 "is the bios image corrupt?\n", MAX_TABLE_OPS); 3772 3773 return 0; 3774} 3775 3776static void 3777parse_init_tables(struct nvbios *bios) 3778{ 3779 /* Loops and calls parse_init_table() for each present table. */ 3780 3781 int i = 0; 3782 uint16_t table; 3783 struct init_exec iexec = {true, false}; 3784 3785 if (bios->old_style_init) { 3786 if (bios->init_script_tbls_ptr) 3787 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec); 3788 if (bios->extra_init_script_tbl_ptr) 3789 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec); 3790 3791 return; 3792 } 3793 3794 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) { 3795 NV_INFO(bios->dev, 3796 "Parsing VBIOS init table %d at offset 0x%04X\n", 3797 i / 2, table); 3798 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table); 3799 3800 parse_init_table(bios, table, &iexec); 3801 i += 2; 3802 } 3803} 3804 3805static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) 3806{ 3807 int compare_record_len, i = 0; 3808 uint16_t compareclk, scriptptr = 0; 3809 3810 if (bios->major_version < 5) /* pre BIT */ 3811 compare_record_len = 3; 3812 else 3813 compare_record_len = 4; 3814 3815 do { 3816 compareclk = ROM16(bios->data[clktable + compare_record_len * i]); 3817 if (pxclk >= compareclk * 10) { 3818 if (bios->major_version < 5) { 3819 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; 3820 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); 3821 } else 3822 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); 3823 break; 3824 } 3825 i++; 3826 } while (compareclk); 3827 3828 return scriptptr; 3829} 3830 3831static void 3832run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, 3833 struct dcb_entry *dcbent, int head, bool dl) 3834{ 3835 struct drm_nouveau_private *dev_priv = dev->dev_private; 3836 struct nvbios *bios = &dev_priv->vbios; 3837 struct init_exec iexec = {true, false}; 3838 3839 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", 3840 scriptptr); 3841 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44, 3842 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA); 3843 /* note: if dcb entries have been merged, index may be misleading */ 3844 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index); 3845 parse_init_table(bios, scriptptr, &iexec); 3846 3847 nv04_dfp_bind_head(dev, dcbent, head, dl); 3848} 3849 3850static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script) 3851{ 3852 struct drm_nouveau_private *dev_priv = dev->dev_private; 3853 struct nvbios *bios = &dev_priv->vbios; 3854 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0); 3855 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); 3856 3857 if (!bios->fp.xlated_entry || !sub || !scriptofs) 3858 return -EINVAL; 3859 3860 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link); 3861 3862 if (script == LVDS_PANEL_OFF) { 3863 /* off-on delay in ms */ 3864 msleep(ROM16(bios->data[bios->fp.xlated_entry + 7])); 3865 } 3866#ifdef __powerpc__ 3867 /* Powerbook specific quirks */ 3868 if (script == LVDS_RESET && 3869 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 || 3870 dev->pci_device == 0x0329)) 3871 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); 3872#endif 3873 3874 return 0; 3875} 3876 3877static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3878{ 3879 /* 3880 * The BIT LVDS table's header has the information to setup the 3881 * necessary registers. Following the standard 4 byte header are: 3882 * A bitmask byte and a dual-link transition pxclk value for use in 3883 * selecting the init script when not using straps; 4 script pointers 3884 * for panel power, selected by output and on/off; and 8 table pointers 3885 * for panel init, the needed one determined by output, and bits in the 3886 * conf byte. These tables are similar to the TMDS tables, consisting 3887 * of a list of pxclks and script pointers. 3888 */ 3889 struct drm_nouveau_private *dev_priv = dev->dev_private; 3890 struct nvbios *bios = &dev_priv->vbios; 3891 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 3892 uint16_t scriptptr = 0, clktable; 3893 3894 /* 3895 * For now we assume version 3.0 table - g80 support will need some 3896 * changes 3897 */ 3898 3899 switch (script) { 3900 case LVDS_INIT: 3901 return -ENOSYS; 3902 case LVDS_BACKLIGHT_ON: 3903 case LVDS_PANEL_ON: 3904 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]); 3905 break; 3906 case LVDS_BACKLIGHT_OFF: 3907 case LVDS_PANEL_OFF: 3908 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); 3909 break; 3910 case LVDS_RESET: 3911 clktable = bios->fp.lvdsmanufacturerpointer + 15; 3912 if (dcbent->or == 4) 3913 clktable += 8; 3914 3915 if (dcbent->lvdsconf.use_straps_for_mode) { 3916 if (bios->fp.dual_link) 3917 clktable += 4; 3918 if (bios->fp.if_is_24bit) 3919 clktable += 2; 3920 } else { 3921 /* using EDID */ 3922 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; 3923 3924 if (bios->fp.dual_link) { 3925 clktable += 4; 3926 cmpval_24bit <<= 1; 3927 } 3928 3929 if (bios->fp.strapless_is_24bit & cmpval_24bit) 3930 clktable += 2; 3931 } 3932 3933 clktable = ROM16(bios->data[clktable]); 3934 if (!clktable) { 3935 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 3936 return -ENOENT; 3937 } 3938 scriptptr = clkcmptable(bios, clktable, pxclk); 3939 } 3940 3941 if (!scriptptr) { 3942 NV_ERROR(dev, "LVDS output init script not found\n"); 3943 return -ENOENT; 3944 } 3945 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); 3946 3947 return 0; 3948} 3949 3950int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk) 3951{ 3952 /* 3953 * LVDS operations are multiplexed in an effort to present a single API 3954 * which works with two vastly differing underlying structures. 3955 * This acts as the demux 3956 */ 3957 3958 struct drm_nouveau_private *dev_priv = dev->dev_private; 3959 struct nvbios *bios = &dev_priv->vbios; 3960 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 3961 uint32_t sel_clk_binding, sel_clk; 3962 int ret; 3963 3964 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver || 3965 (lvds_ver >= 0x30 && script == LVDS_INIT)) 3966 return 0; 3967 3968 if (!bios->fp.lvds_init_run) { 3969 bios->fp.lvds_init_run = true; 3970 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk); 3971 } 3972 3973 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change) 3974 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk); 3975 if (script == LVDS_RESET && bios->fp.power_off_for_reset) 3976 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); 3977 3978 NV_TRACE(dev, "Calling LVDS script %d:\n", script); 3979 3980 /* don't let script change pll->head binding */ 3981 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 3982 3983 if (lvds_ver < 0x30) 3984 ret = call_lvds_manufacturer_script(dev, dcbent, head, script); 3985 else 3986 ret = run_lvds_table(dev, dcbent, head, script, pxclk); 3987 3988 bios->fp.last_script_invoc = (script << 1 | head); 3989 3990 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 3991 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 3992 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ 3993 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0); 3994 3995 return ret; 3996} 3997 3998struct lvdstableheader { 3999 uint8_t lvds_ver, headerlen, recordlen; 4000}; 4001 4002static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth) 4003{ 4004 /* 4005 * BMP version (0xa) LVDS table has a simple header of version and 4006 * record length. The BIT LVDS table has the typical BIT table header: 4007 * version byte, header length byte, record length byte, and a byte for 4008 * the maximum number of records that can be held in the table. 4009 */ 4010 4011 uint8_t lvds_ver, headerlen, recordlen; 4012 4013 memset(lth, 0, sizeof(struct lvdstableheader)); 4014 4015 if (bios->fp.lvdsmanufacturerpointer == 0x0) { 4016 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n"); 4017 return -EINVAL; 4018 } 4019 4020 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 4021 4022 switch (lvds_ver) { 4023 case 0x0a: /* pre NV40 */ 4024 headerlen = 2; 4025 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 4026 break; 4027 case 0x30: /* NV4x */ 4028 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 4029 if (headerlen < 0x1f) { 4030 NV_ERROR(dev, "LVDS table header not understood\n"); 4031 return -EINVAL; 4032 } 4033 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 4034 break; 4035 case 0x40: /* G80/G90 */ 4036 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 4037 if (headerlen < 0x7) { 4038 NV_ERROR(dev, "LVDS table header not understood\n"); 4039 return -EINVAL; 4040 } 4041 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 4042 break; 4043 default: 4044 NV_ERROR(dev, 4045 "LVDS table revision %d.%d not currently supported\n", 4046 lvds_ver >> 4, lvds_ver & 0xf); 4047 return -ENOSYS; 4048 } 4049 4050 lth->lvds_ver = lvds_ver; 4051 lth->headerlen = headerlen; 4052 lth->recordlen = recordlen; 4053 4054 return 0; 4055} 4056 4057static int 4058get_fp_strap(struct drm_device *dev, struct nvbios *bios) 4059{ 4060 struct drm_nouveau_private *dev_priv = dev->dev_private; 4061 4062 /* 4063 * The fp strap is normally dictated by the "User Strap" in 4064 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the 4065 * Internal_Flags struct at 0x48 is set, the user strap gets overriden 4066 * by the PCI subsystem ID during POST, but not before the previous user 4067 * strap has been committed to CR58 for CR57=0xf on head A, which may be 4068 * read and used instead 4069 */ 4070 4071 if (bios->major_version < 5 && bios->data[0x48] & 0x4) 4072 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; 4073 4074 if (dev_priv->card_type >= NV_50) 4075 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; 4076 else 4077 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; 4078} 4079 4080static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) 4081{ 4082 uint8_t *fptable; 4083 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; 4084 int ret, ofs, fpstrapping; 4085 struct lvdstableheader lth; 4086 4087 if (bios->fp.fptablepointer == 0x0) { 4088 /* Apple cards don't have the fp table; the laptops use DDC */ 4089 /* The table is also missing on some x86 IGPs */ 4090#ifndef __powerpc__ 4091 NV_ERROR(dev, "Pointer to flat panel table invalid\n"); 4092#endif 4093 bios->digital_min_front_porch = 0x4b; 4094 return 0; 4095 } 4096 4097 fptable = &bios->data[bios->fp.fptablepointer]; 4098 fptable_ver = fptable[0]; 4099 4100 switch (fptable_ver) { 4101 /* 4102 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no 4103 * version field, and miss one of the spread spectrum/PWM bytes. 4104 * This could affect early GF2Go parts (not seen any appropriate ROMs 4105 * though). Here we assume that a version of 0x05 matches this case 4106 * (combining with a BMP version check would be better), as the 4107 * common case for the panel type field is 0x0005, and that is in 4108 * fact what we are reading the first byte of. 4109 */ 4110 case 0x05: /* some NV10, 11, 15, 16 */ 4111 recordlen = 42; 4112 ofs = -1; 4113 break; 4114 case 0x10: /* some NV15/16, and NV11+ */ 4115 recordlen = 44; 4116 ofs = 0; 4117 break; 4118 case 0x20: /* NV40+ */ 4119 headerlen = fptable[1]; 4120 recordlen = fptable[2]; 4121 fpentries = fptable[3]; 4122 /* 4123 * fptable[4] is the minimum 4124 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap 4125 */ 4126 bios->digital_min_front_porch = fptable[4]; 4127 ofs = -7; 4128 break; 4129 default: 4130 NV_ERROR(dev, 4131 "FP table revision %d.%d not currently supported\n", 4132 fptable_ver >> 4, fptable_ver & 0xf); 4133 return -ENOSYS; 4134 } 4135 4136 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */ 4137 return 0; 4138 4139 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 4140 if (ret) 4141 return ret; 4142 4143 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { 4144 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + 4145 lth.headerlen + 1; 4146 bios->fp.xlatwidth = lth.recordlen; 4147 } 4148 if (bios->fp.fpxlatetableptr == 0x0) { 4149 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n"); 4150 return -EINVAL; 4151 } 4152 4153 fpstrapping = get_fp_strap(dev, bios); 4154 4155 fpindex = bios->data[bios->fp.fpxlatetableptr + 4156 fpstrapping * bios->fp.xlatwidth]; 4157 4158 if (fpindex > fpentries) { 4159 NV_ERROR(dev, "Bad flat panel table index\n"); 4160 return -ENOENT; 4161 } 4162 4163 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ 4164 if (lth.lvds_ver > 0x10) 4165 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; 4166 4167 /* 4168 * If either the strap or xlated fpindex value are 0xf there is no 4169 * panel using a strap-derived bios mode present. this condition 4170 * includes, but is different from, the DDC panel indicator above 4171 */ 4172 if (fpstrapping == 0xf || fpindex == 0xf) 4173 return 0; 4174 4175 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + 4176 recordlen * fpindex + ofs; 4177 4178 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", 4179 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, 4180 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, 4181 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); 4182 4183 return 0; 4184} 4185 4186bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) 4187{ 4188 struct drm_nouveau_private *dev_priv = dev->dev_private; 4189 struct nvbios *bios = &dev_priv->vbios; 4190 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; 4191 4192 if (!mode) /* just checking whether we can produce a mode */ 4193 return bios->fp.mode_ptr; 4194 4195 memset(mode, 0, sizeof(struct drm_display_mode)); 4196 /* 4197 * For version 1.0 (version in byte 0): 4198 * bytes 1-2 are "panel type", including bits on whether Colour/mono, 4199 * single/dual link, and type (TFT etc.) 4200 * bytes 3-6 are bits per colour in RGBX 4201 */ 4202 mode->clock = ROM16(mode_entry[7]) * 10; 4203 /* bytes 9-10 is HActive */ 4204 mode->hdisplay = ROM16(mode_entry[11]) + 1; 4205 /* 4206 * bytes 13-14 is HValid Start 4207 * bytes 15-16 is HValid End 4208 */ 4209 mode->hsync_start = ROM16(mode_entry[17]) + 1; 4210 mode->hsync_end = ROM16(mode_entry[19]) + 1; 4211 mode->htotal = ROM16(mode_entry[21]) + 1; 4212 /* bytes 23-24, 27-30 similarly, but vertical */ 4213 mode->vdisplay = ROM16(mode_entry[25]) + 1; 4214 mode->vsync_start = ROM16(mode_entry[31]) + 1; 4215 mode->vsync_end = ROM16(mode_entry[33]) + 1; 4216 mode->vtotal = ROM16(mode_entry[35]) + 1; 4217 mode->flags |= (mode_entry[37] & 0x10) ? 4218 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4219 mode->flags |= (mode_entry[37] & 0x1) ? 4220 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4221 /* 4222 * bytes 38-39 relate to spread spectrum settings 4223 * bytes 40-43 are something to do with PWM 4224 */ 4225 4226 mode->status = MODE_OK; 4227 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 4228 drm_mode_set_name(mode); 4229 return bios->fp.mode_ptr; 4230} 4231 4232int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit) 4233{ 4234 /* 4235 * The LVDS table header is (mostly) described in 4236 * parse_lvds_manufacturer_table_header(): the BIT header additionally 4237 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if 4238 * straps are not being used for the panel, this specifies the frequency 4239 * at which modes should be set up in the dual link style. 4240 * 4241 * Following the header, the BMP (ver 0xa) table has several records, 4242 * indexed by a separate xlat table, indexed in turn by the fp strap in 4243 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script 4244 * numbers for use by INIT_SUB which controlled panel init and power, 4245 * and finally a dword of ms to sleep between power off and on 4246 * operations. 4247 * 4248 * In the BIT versions, the table following the header serves as an 4249 * integrated config and xlat table: the records in the table are 4250 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has 4251 * two bytes - the first as a config byte, the second for indexing the 4252 * fp mode table pointed to by the BIT 'D' table 4253 * 4254 * DDC is not used until after card init, so selecting the correct table 4255 * entry and setting the dual link flag for EDID equipped panels, 4256 * requiring tests against the native-mode pixel clock, cannot be done 4257 * until later, when this function should be called with non-zero pxclk 4258 */ 4259 struct drm_nouveau_private *dev_priv = dev->dev_private; 4260 struct nvbios *bios = &dev_priv->vbios; 4261 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; 4262 struct lvdstableheader lth; 4263 uint16_t lvdsofs; 4264 int ret, chip_version = bios->chip_version; 4265 4266 ret = parse_lvds_manufacturer_table_header(dev, bios, <h); 4267 if (ret) 4268 return ret; 4269 4270 switch (lth.lvds_ver) { 4271 case 0x0a: /* pre NV40 */ 4272 lvdsmanufacturerindex = bios->data[ 4273 bios->fp.fpxlatemanufacturertableptr + 4274 fpstrapping]; 4275 4276 /* we're done if this isn't the EDID panel case */ 4277 if (!pxclk) 4278 break; 4279 4280 if (chip_version < 0x25) { 4281 /* nv17 behaviour 4282 * 4283 * It seems the old style lvds script pointer is reused 4284 * to select 18/24 bit colour depth for EDID panels. 4285 */ 4286 lvdsmanufacturerindex = 4287 (bios->legacy.lvds_single_a_script_ptr & 1) ? 4288 2 : 0; 4289 if (pxclk >= bios->fp.duallink_transition_clk) 4290 lvdsmanufacturerindex++; 4291 } else if (chip_version < 0x30) { 4292 /* nv28 behaviour (off-chip encoder) 4293 * 4294 * nv28 does a complex dance of first using byte 121 of 4295 * the EDID to choose the lvdsmanufacturerindex, then 4296 * later attempting to match the EDID manufacturer and 4297 * product IDs in a table (signature 'pidt' (panel id 4298 * table?)), setting an lvdsmanufacturerindex of 0 and 4299 * an fp strap of the match index (or 0xf if none) 4300 */ 4301 lvdsmanufacturerindex = 0; 4302 } else { 4303 /* nv31, nv34 behaviour */ 4304 lvdsmanufacturerindex = 0; 4305 if (pxclk >= bios->fp.duallink_transition_clk) 4306 lvdsmanufacturerindex = 2; 4307 if (pxclk >= 140000) 4308 lvdsmanufacturerindex = 3; 4309 } 4310 4311 /* 4312 * nvidia set the high nibble of (cr57=f, cr58) to 4313 * lvdsmanufacturerindex in this case; we don't 4314 */ 4315 break; 4316 case 0x30: /* NV4x */ 4317 case 0x40: /* G80/G90 */ 4318 lvdsmanufacturerindex = fpstrapping; 4319 break; 4320 default: 4321 NV_ERROR(dev, "LVDS table revision not currently supported\n"); 4322 return -ENOSYS; 4323 } 4324 4325 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex; 4326 switch (lth.lvds_ver) { 4327 case 0x0a: 4328 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1; 4329 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2; 4330 bios->fp.dual_link = bios->data[lvdsofs] & 4; 4331 bios->fp.link_c_increment = bios->data[lvdsofs] & 8; 4332 *if_is_24bit = bios->data[lvdsofs] & 16; 4333 break; 4334 case 0x30: 4335 case 0x40: 4336 /* 4337 * No sign of the "power off for reset" or "reset for panel 4338 * on" bits, but it's safer to assume we should 4339 */ 4340 bios->fp.power_off_for_reset = true; 4341 bios->fp.reset_after_pclk_change = true; 4342 4343 /* 4344 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is 4345 * over-written, and if_is_24bit isn't used 4346 */ 4347 bios->fp.dual_link = bios->data[lvdsofs] & 1; 4348 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; 4349 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; 4350 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; 4351 break; 4352 } 4353 4354 /* Dell Latitude D620 reports a too-high value for the dual-link 4355 * transition freq, causing us to program the panel incorrectly. 4356 * 4357 * It doesn't appear the VBIOS actually uses its transition freq 4358 * (90000kHz), instead it uses the "Number of LVDS channels" field 4359 * out of the panel ID structure (http://www.spwg.org/). 4360 * 4361 * For the moment, a quirk will do :) 4362 */ 4363 if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2)) 4364 bios->fp.duallink_transition_clk = 80000; 4365 4366 /* set dual_link flag for EDID case */ 4367 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 4368 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 4369 4370 *dl = bios->fp.dual_link; 4371 4372 return 0; 4373} 4374 4375static uint8_t * 4376bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent, 4377 uint16_t record, int record_len, int record_nr, 4378 bool match_link) 4379{ 4380 struct drm_nouveau_private *dev_priv = dev->dev_private; 4381 struct nvbios *bios = &dev_priv->vbios; 4382 uint32_t entry; 4383 uint16_t table; 4384 int i, v; 4385 4386 switch (dcbent->type) { 4387 case OUTPUT_TMDS: 4388 case OUTPUT_LVDS: 4389 case OUTPUT_DP: 4390 break; 4391 default: 4392 match_link = false; 4393 break; 4394 } 4395 4396 for (i = 0; i < record_nr; i++, record += record_len) { 4397 table = ROM16(bios->data[record]); 4398 if (!table) 4399 continue; 4400 entry = ROM32(bios->data[table]); 4401 4402 if (match_link) { 4403 v = (entry & 0x00c00000) >> 22; 4404 if (!(v & dcbent->sorconf.link)) 4405 continue; 4406 } 4407 4408 v = (entry & 0x000f0000) >> 16; 4409 if (!(v & dcbent->or)) 4410 continue; 4411 4412 v = (entry & 0x000000f0) >> 4; 4413 if (v != dcbent->location) 4414 continue; 4415 4416 v = (entry & 0x0000000f); 4417 if (v != dcbent->type) 4418 continue; 4419 4420 return &bios->data[table]; 4421 } 4422 4423 return NULL; 4424} 4425 4426void * 4427nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent, 4428 int *length) 4429{ 4430 struct drm_nouveau_private *dev_priv = dev->dev_private; 4431 struct nvbios *bios = &dev_priv->vbios; 4432 uint8_t *table; 4433 4434 if (!bios->display.dp_table_ptr) { 4435 NV_ERROR(dev, "No pointer to DisplayPort table\n"); 4436 return NULL; 4437 } 4438 table = &bios->data[bios->display.dp_table_ptr]; 4439 4440 if (table[0] != 0x20 && table[0] != 0x21) { 4441 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n", 4442 table[0]); 4443 return NULL; 4444 } 4445 4446 *length = table[4]; 4447 return bios_output_config_match(dev, dcbent, 4448 bios->display.dp_table_ptr + table[1], 4449 table[2], table[3], table[0] >= 0x21); 4450} 4451 4452int 4453nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, 4454 uint32_t sub, int pxclk) 4455{ 4456 /* 4457 * The display script table is located by the BIT 'U' table. 4458 * 4459 * It contains an array of pointers to various tables describing 4460 * a particular output type. The first 32-bits of the output 4461 * tables contains similar information to a DCB entry, and is 4462 * used to decide whether that particular table is suitable for 4463 * the output you want to access. 4464 * 4465 * The "record header length" field here seems to indicate the 4466 * offset of the first configuration entry in the output tables. 4467 * This is 10 on most cards I've seen, but 12 has been witnessed 4468 * on DP cards, and there's another script pointer within the 4469 * header. 4470 * 4471 * offset + 0 ( 8 bits): version 4472 * offset + 1 ( 8 bits): header length 4473 * offset + 2 ( 8 bits): record length 4474 * offset + 3 ( 8 bits): number of records 4475 * offset + 4 ( 8 bits): record header length 4476 * offset + 5 (16 bits): pointer to first output script table 4477 */ 4478 4479 struct drm_nouveau_private *dev_priv = dev->dev_private; 4480 struct nvbios *bios = &dev_priv->vbios; 4481 uint8_t *table = &bios->data[bios->display.script_table_ptr]; 4482 uint8_t *otable = NULL; 4483 uint16_t script; 4484 int i = 0; 4485 4486 if (!bios->display.script_table_ptr) { 4487 NV_ERROR(dev, "No pointer to output script table\n"); 4488 return 1; 4489 } 4490 4491 /* 4492 * Nothing useful has been in any of the pre-2.0 tables I've seen, 4493 * so until they are, we really don't need to care. 4494 */ 4495 if (table[0] < 0x20) 4496 return 1; 4497 4498 if (table[0] != 0x20 && table[0] != 0x21) { 4499 NV_ERROR(dev, "Output script table version 0x%02x unknown\n", 4500 table[0]); 4501 return 1; 4502 } 4503 4504 /* 4505 * The output script tables describing a particular output type 4506 * look as follows: 4507 * 4508 * offset + 0 (32 bits): output this table matches (hash of DCB) 4509 * offset + 4 ( 8 bits): unknown 4510 * offset + 5 ( 8 bits): number of configurations 4511 * offset + 6 (16 bits): pointer to some script 4512 * offset + 8 (16 bits): pointer to some script 4513 * 4514 * headerlen == 10 4515 * offset + 10 : configuration 0 4516 * 4517 * headerlen == 12 4518 * offset + 10 : pointer to some script 4519 * offset + 12 : configuration 0 4520 * 4521 * Each config entry is as follows: 4522 * 4523 * offset + 0 (16 bits): unknown, assumed to be a match value 4524 * offset + 2 (16 bits): pointer to script table (clock set?) 4525 * offset + 4 (16 bits): pointer to script table (reset?) 4526 * 4527 * There doesn't appear to be a count value to say how many 4528 * entries exist in each script table, instead, a 0 value in 4529 * the first 16-bit word seems to indicate both the end of the 4530 * list and the default entry. The second 16-bit word in the 4531 * script tables is a pointer to the script to execute. 4532 */ 4533 4534 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", 4535 dcbent->type, dcbent->location, dcbent->or); 4536 otable = bios_output_config_match(dev, dcbent, table[1] + 4537 bios->display.script_table_ptr, 4538 table[2], table[3], table[0] >= 0x21); 4539 if (!otable) { 4540 NV_DEBUG_KMS(dev, "failed to match any output table\n"); 4541 return 1; 4542 } 4543 4544 if (pxclk < -2 || pxclk > 0) { 4545 /* Try to find matching script table entry */ 4546 for (i = 0; i < otable[5]; i++) { 4547 if (ROM16(otable[table[4] + i*6]) == sub) 4548 break; 4549 } 4550 4551 if (i == otable[5]) { 4552 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, " 4553 "using first\n", 4554 sub, dcbent->type, dcbent->or); 4555 i = 0; 4556 } 4557 } 4558 4559 if (pxclk == 0) { 4560 script = ROM16(otable[6]); 4561 if (!script) { 4562 NV_DEBUG_KMS(dev, "output script 0 not found\n"); 4563 return 1; 4564 } 4565 4566 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script); 4567 nouveau_bios_run_init_table(dev, script, dcbent); 4568 } else 4569 if (pxclk == -1) { 4570 script = ROM16(otable[8]); 4571 if (!script) { 4572 NV_DEBUG_KMS(dev, "output script 1 not found\n"); 4573 return 1; 4574 } 4575 4576 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script); 4577 nouveau_bios_run_init_table(dev, script, dcbent); 4578 } else 4579 if (pxclk == -2) { 4580 if (table[4] >= 12) 4581 script = ROM16(otable[10]); 4582 else 4583 script = 0; 4584 if (!script) { 4585 NV_DEBUG_KMS(dev, "output script 2 not found\n"); 4586 return 1; 4587 } 4588 4589 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script); 4590 nouveau_bios_run_init_table(dev, script, dcbent); 4591 } else 4592 if (pxclk > 0) { 4593 script = ROM16(otable[table[4] + i*6 + 2]); 4594 if (script) 4595 script = clkcmptable(bios, script, pxclk); 4596 if (!script) { 4597 NV_DEBUG_KMS(dev, "clock script 0 not found\n"); 4598 return 1; 4599 } 4600 4601 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script); 4602 nouveau_bios_run_init_table(dev, script, dcbent); 4603 } else 4604 if (pxclk < 0) { 4605 script = ROM16(otable[table[4] + i*6 + 4]); 4606 if (script) 4607 script = clkcmptable(bios, script, -pxclk); 4608 if (!script) { 4609 NV_DEBUG_KMS(dev, "clock script 1 not found\n"); 4610 return 1; 4611 } 4612 4613 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script); 4614 nouveau_bios_run_init_table(dev, script, dcbent); 4615 } 4616 4617 return 0; 4618} 4619 4620 4621int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk) 4622{ 4623 /* 4624 * the pxclk parameter is in kHz 4625 * 4626 * This runs the TMDS regs setting code found on BIT bios cards 4627 * 4628 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and 4629 * ffs(or) == 3, use the second. 4630 */ 4631 4632 struct drm_nouveau_private *dev_priv = dev->dev_private; 4633 struct nvbios *bios = &dev_priv->vbios; 4634 int cv = bios->chip_version; 4635 uint16_t clktable = 0, scriptptr; 4636 uint32_t sel_clk_binding, sel_clk; 4637 4638 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ 4639 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && 4640 dcbent->location != DCB_LOC_ON_CHIP) 4641 return 0; 4642 4643 switch (ffs(dcbent->or)) { 4644 case 1: 4645 clktable = bios->tmds.output0_script_ptr; 4646 break; 4647 case 2: 4648 case 3: 4649 clktable = bios->tmds.output1_script_ptr; 4650 break; 4651 } 4652 4653 if (!clktable) { 4654 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 4655 return -EINVAL; 4656 } 4657 4658 scriptptr = clkcmptable(bios, clktable, pxclk); 4659 4660 if (!scriptptr) { 4661 NV_ERROR(dev, "TMDS output init script not found\n"); 4662 return -ENOENT; 4663 } 4664 4665 /* don't let script change pll->head binding */ 4666 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000; 4667 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); 4668 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 4669 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 4670 4671 return 0; 4672} 4673 4674int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) 4675{ 4676 /* 4677 * PLL limits table 4678 * 4679 * Version 0x10: NV30, NV31 4680 * One byte header (version), one record of 24 bytes 4681 * Version 0x11: NV36 - Not implemented 4682 * Seems to have same record style as 0x10, but 3 records rather than 1 4683 * Version 0x20: Found on Geforce 6 cards 4684 * Trivial 4 byte BIT header. 31 (0x1f) byte record length 4685 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards 4686 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record 4687 * length in general, some (integrated) have an extra configuration byte 4688 * Version 0x30: Found on Geforce 8, separates the register mapping 4689 * from the limits tables. 4690 */ 4691 4692 struct drm_nouveau_private *dev_priv = dev->dev_private; 4693 struct nvbios *bios = &dev_priv->vbios; 4694 int cv = bios->chip_version, pllindex = 0; 4695 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0; 4696 uint32_t crystal_strap_mask, crystal_straps; 4697 4698 if (!bios->pll_limit_tbl_ptr) { 4699 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || 4700 cv >= 0x40) { 4701 NV_ERROR(dev, "Pointer to PLL limits table invalid\n"); 4702 return -EINVAL; 4703 } 4704 } else 4705 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr]; 4706 4707 crystal_strap_mask = 1 << 6; 4708 /* open coded dev->twoHeads test */ 4709 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20) 4710 crystal_strap_mask |= 1 << 22; 4711 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 4712 crystal_strap_mask; 4713 4714 switch (pll_lim_ver) { 4715 /* 4716 * We use version 0 to indicate a pre limit table bios (single stage 4717 * pll) and load the hard coded limits instead. 4718 */ 4719 case 0: 4720 break; 4721 case 0x10: 4722 case 0x11: 4723 /* 4724 * Strictly v0x11 has 3 entries, but the last two don't seem 4725 * to get used. 4726 */ 4727 headerlen = 1; 4728 recordlen = 0x18; 4729 entries = 1; 4730 pllindex = 0; 4731 break; 4732 case 0x20: 4733 case 0x21: 4734 case 0x30: 4735 case 0x40: 4736 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1]; 4737 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2]; 4738 entries = bios->data[bios->pll_limit_tbl_ptr + 3]; 4739 break; 4740 default: 4741 NV_ERROR(dev, "PLL limits table revision 0x%X not currently " 4742 "supported\n", pll_lim_ver); 4743 return -ENOSYS; 4744 } 4745 4746 /* initialize all members to zero */ 4747 memset(pll_lim, 0, sizeof(struct pll_lims)); 4748 4749 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { 4750 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; 4751 4752 pll_lim->vco1.minfreq = ROM32(pll_rec[0]); 4753 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]); 4754 pll_lim->vco2.minfreq = ROM32(pll_rec[8]); 4755 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]); 4756 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]); 4757 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]); 4758 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX; 4759 4760 /* these values taken from nv30/31/36 */ 4761 pll_lim->vco1.min_n = 0x1; 4762 if (cv == 0x36) 4763 pll_lim->vco1.min_n = 0x5; 4764 pll_lim->vco1.max_n = 0xff; 4765 pll_lim->vco1.min_m = 0x1; 4766 pll_lim->vco1.max_m = 0xd; 4767 pll_lim->vco2.min_n = 0x4; 4768 /* 4769 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this 4770 * table version (apart from nv35)), N2 is compared to 4771 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and 4772 * save a comparison 4773 */ 4774 pll_lim->vco2.max_n = 0x28; 4775 if (cv == 0x30 || cv == 0x35) 4776 /* only 5 bits available for N2 on nv30/35 */ 4777 pll_lim->vco2.max_n = 0x1f; 4778 pll_lim->vco2.min_m = 0x1; 4779 pll_lim->vco2.max_m = 0x4; 4780 pll_lim->max_log2p = 0x7; 4781 pll_lim->max_usable_log2p = 0x6; 4782 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { 4783 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; 4784 uint32_t reg = 0; /* default match */ 4785 uint8_t *pll_rec; 4786 int i; 4787 4788 /* 4789 * First entry is default match, if nothing better. warn if 4790 * reg field nonzero 4791 */ 4792 if (ROM32(bios->data[plloffs])) 4793 NV_WARN(dev, "Default PLL limit entry has non-zero " 4794 "register field\n"); 4795 4796 if (limit_match > MAX_PLL_TYPES) 4797 /* we've been passed a reg as the match */ 4798 reg = limit_match; 4799 else /* limit match is a pll type */ 4800 for (i = 1; i < entries && !reg; i++) { 4801 uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]); 4802 4803 if (limit_match == NVPLL && 4804 (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000)) 4805 reg = cmpreg; 4806 if (limit_match == MPLL && 4807 (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020)) 4808 reg = cmpreg; 4809 if (limit_match == VPLL1 && 4810 (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010)) 4811 reg = cmpreg; 4812 if (limit_match == VPLL2 && 4813 (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018)) 4814 reg = cmpreg; 4815 } 4816 4817 for (i = 1; i < entries; i++) 4818 if (ROM32(bios->data[plloffs + recordlen * i]) == reg) { 4819 pllindex = i; 4820 break; 4821 } 4822 4823 pll_rec = &bios->data[plloffs + recordlen * pllindex]; 4824 4825 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", 4826 pllindex ? reg : 0); 4827 4828 /* 4829 * Frequencies are stored in tables in MHz, kHz are more 4830 * useful, so we convert. 4831 */ 4832 4833 /* What output frequencies can each VCO generate? */ 4834 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000; 4835 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000; 4836 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000; 4837 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000; 4838 4839 /* What input frequencies they accept (past the m-divider)? */ 4840 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000; 4841 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000; 4842 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000; 4843 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000; 4844 4845 /* What values are accepted as multiplier and divider? */ 4846 pll_lim->vco1.min_n = pll_rec[20]; 4847 pll_lim->vco1.max_n = pll_rec[21]; 4848 pll_lim->vco1.min_m = pll_rec[22]; 4849 pll_lim->vco1.max_m = pll_rec[23]; 4850 pll_lim->vco2.min_n = pll_rec[24]; 4851 pll_lim->vco2.max_n = pll_rec[25]; 4852 pll_lim->vco2.min_m = pll_rec[26]; 4853 pll_lim->vco2.max_m = pll_rec[27]; 4854 4855 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29]; 4856 if (pll_lim->max_log2p > 0x7) 4857 /* pll decoding in nv_hw.c assumes never > 7 */ 4858 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n", 4859 pll_lim->max_log2p); 4860 if (cv < 0x60) 4861 pll_lim->max_usable_log2p = 0x6; 4862 pll_lim->log2p_bias = pll_rec[30]; 4863 4864 if (recordlen > 0x22) 4865 pll_lim->refclk = ROM32(pll_rec[31]); 4866 4867 if (recordlen > 0x23 && pll_rec[35]) 4868 NV_WARN(dev, 4869 "Bits set in PLL configuration byte (%x)\n", 4870 pll_rec[35]); 4871 4872 /* C51 special not seen elsewhere */ 4873 if (cv == 0x51 && !pll_lim->refclk) { 4874 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); 4875 4876 if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) || 4877 ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) { 4878 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) 4879 pll_lim->refclk = 200000; 4880 else 4881 pll_lim->refclk = 25000; 4882 } 4883 } 4884 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */ 4885 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4886 uint8_t *record = NULL; 4887 int i; 4888 4889 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4890 limit_match); 4891 4892 for (i = 0; i < entries; i++, entry += recordlen) { 4893 if (ROM32(entry[3]) == limit_match) { 4894 record = &bios->data[ROM16(entry[1])]; 4895 break; 4896 } 4897 } 4898 4899 if (!record) { 4900 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4901 "limits table", limit_match); 4902 return -ENOENT; 4903 } 4904 4905 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4906 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4907 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000; 4908 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000; 4909 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000; 4910 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000; 4911 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000; 4912 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000; 4913 pll_lim->vco1.min_n = record[16]; 4914 pll_lim->vco1.max_n = record[17]; 4915 pll_lim->vco1.min_m = record[18]; 4916 pll_lim->vco1.max_m = record[19]; 4917 pll_lim->vco2.min_n = record[20]; 4918 pll_lim->vco2.max_n = record[21]; 4919 pll_lim->vco2.min_m = record[22]; 4920 pll_lim->vco2.max_m = record[23]; 4921 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25]; 4922 pll_lim->log2p_bias = record[27]; 4923 pll_lim->refclk = ROM32(record[28]); 4924 } else if (pll_lim_ver) { /* ver 0x40 */ 4925 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen]; 4926 uint8_t *record = NULL; 4927 int i; 4928 4929 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", 4930 limit_match); 4931 4932 for (i = 0; i < entries; i++, entry += recordlen) { 4933 if (ROM32(entry[3]) == limit_match) { 4934 record = &bios->data[ROM16(entry[1])]; 4935 break; 4936 } 4937 } 4938 4939 if (!record) { 4940 NV_ERROR(dev, "Register 0x%08x not found in PLL " 4941 "limits table", limit_match); 4942 return -ENOENT; 4943 } 4944 4945 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000; 4946 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000; 4947 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000; 4948 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000; 4949 pll_lim->vco1.min_m = record[8]; 4950 pll_lim->vco1.max_m = record[9]; 4951 pll_lim->vco1.min_n = record[10]; 4952 pll_lim->vco1.max_n = record[11]; 4953 pll_lim->min_p = record[12]; 4954 pll_lim->max_p = record[13]; 4955 /* where did this go to?? */ 4956 if ((entry[0] & 0xf0) == 0x80) 4957 pll_lim->refclk = 27000; 4958 else 4959 pll_lim->refclk = 100000; 4960 } 4961 4962 /* 4963 * By now any valid limit table ought to have set a max frequency for 4964 * vco1, so if it's zero it's either a pre limit table bios, or one 4965 * with an empty limit table (seen on nv18) 4966 */ 4967 if (!pll_lim->vco1.maxfreq) { 4968 pll_lim->vco1.minfreq = bios->fminvco; 4969 pll_lim->vco1.maxfreq = bios->fmaxvco; 4970 pll_lim->vco1.min_inputfreq = 0; 4971 pll_lim->vco1.max_inputfreq = INT_MAX; 4972 pll_lim->vco1.min_n = 0x1; 4973 pll_lim->vco1.max_n = 0xff; 4974 pll_lim->vco1.min_m = 0x1; 4975 if (crystal_straps == 0) { 4976 /* nv05 does this, nv11 doesn't, nv10 unknown */ 4977 if (cv < 0x11) 4978 pll_lim->vco1.min_m = 0x7; 4979 pll_lim->vco1.max_m = 0xd; 4980 } else { 4981 if (cv < 0x11) 4982 pll_lim->vco1.min_m = 0x8; 4983 pll_lim->vco1.max_m = 0xe; 4984 } 4985 if (cv < 0x17 || cv == 0x1a || cv == 0x20) 4986 pll_lim->max_log2p = 4; 4987 else 4988 pll_lim->max_log2p = 5; 4989 pll_lim->max_usable_log2p = pll_lim->max_log2p; 4990 } 4991 4992 if (!pll_lim->refclk) 4993 switch (crystal_straps) { 4994 case 0: 4995 pll_lim->refclk = 13500; 4996 break; 4997 case (1 << 6): 4998 pll_lim->refclk = 14318; 4999 break; 5000 case (1 << 22): 5001 pll_lim->refclk = 27000; 5002 break; 5003 case (1 << 22 | 1 << 6): 5004 pll_lim->refclk = 25000; 5005 break; 5006 } 5007 5008 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq); 5009 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq); 5010 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq); 5011 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq); 5012 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n); 5013 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n); 5014 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m); 5015 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m); 5016 if (pll_lim->vco2.maxfreq) { 5017 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq); 5018 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq); 5019 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq); 5020 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq); 5021 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n); 5022 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n); 5023 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m); 5024 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m); 5025 } 5026 if (!pll_lim->max_p) { 5027 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p); 5028 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias); 5029 } else { 5030 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p); 5031 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p); 5032 } 5033 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk); 5034 5035 return 0; 5036} 5037 5038static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset) 5039{ 5040 /* 5041 * offset + 0 (8 bits): Micro version 5042 * offset + 1 (8 bits): Minor version 5043 * offset + 2 (8 bits): Chip version 5044 * offset + 3 (8 bits): Major version 5045 */ 5046 5047 bios->major_version = bios->data[offset + 3]; 5048 bios->chip_version = bios->data[offset + 2]; 5049 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", 5050 bios->data[offset + 3], bios->data[offset + 2], 5051 bios->data[offset + 1], bios->data[offset]); 5052} 5053 5054static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset) 5055{ 5056 /* 5057 * Parses the init table segment for pointers used in script execution. 5058 * 5059 * offset + 0 (16 bits): init script tables pointer 5060 * offset + 2 (16 bits): macro index table pointer 5061 * offset + 4 (16 bits): macro table pointer 5062 * offset + 6 (16 bits): condition table pointer 5063 * offset + 8 (16 bits): io condition table pointer 5064 * offset + 10 (16 bits): io flag condition table pointer 5065 * offset + 12 (16 bits): init function table pointer 5066 */ 5067 5068 bios->init_script_tbls_ptr = ROM16(bios->data[offset]); 5069 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]); 5070 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]); 5071 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]); 5072 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]); 5073 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]); 5074 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]); 5075} 5076 5077static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5078{ 5079 /* 5080 * Parses the load detect values for g80 cards. 5081 * 5082 * offset + 0 (16 bits): loadval table pointer 5083 */ 5084 5085 uint16_t load_table_ptr; 5086 uint8_t version, headerlen, entrylen, num_entries; 5087 5088 if (bitentry->length != 3) { 5089 NV_ERROR(dev, "Do not understand BIT A table\n"); 5090 return -EINVAL; 5091 } 5092 5093 load_table_ptr = ROM16(bios->data[bitentry->offset]); 5094 5095 if (load_table_ptr == 0x0) { 5096 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n"); 5097 return -EINVAL; 5098 } 5099 5100 version = bios->data[load_table_ptr]; 5101 5102 if (version != 0x10) { 5103 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n", 5104 version >> 4, version & 0xF); 5105 return -ENOSYS; 5106 } 5107 5108 headerlen = bios->data[load_table_ptr + 1]; 5109 entrylen = bios->data[load_table_ptr + 2]; 5110 num_entries = bios->data[load_table_ptr + 3]; 5111 5112 if (headerlen != 4 || entrylen != 4 || num_entries != 2) { 5113 NV_ERROR(dev, "Do not understand BIT loadval table\n"); 5114 return -EINVAL; 5115 } 5116 5117 /* First entry is normal dac, 2nd tv-out perhaps? */ 5118 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; 5119 5120 return 0; 5121} 5122 5123static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5124{ 5125 /* 5126 * offset + 8 (16 bits): PLL limits table pointer 5127 * 5128 * There's more in here, but that's unknown. 5129 */ 5130 5131 if (bitentry->length < 10) { 5132 NV_ERROR(dev, "Do not understand BIT C table\n"); 5133 return -EINVAL; 5134 } 5135 5136 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]); 5137 5138 return 0; 5139} 5140 5141static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5142{ 5143 /* 5144 * Parses the flat panel table segment that the bit entry points to. 5145 * Starting at bitentry->offset: 5146 * 5147 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte 5148 * records beginning with a freq. 5149 * offset + 2 (16 bits): mode table pointer 5150 */ 5151 5152 if (bitentry->length != 4) { 5153 NV_ERROR(dev, "Do not understand BIT display table\n"); 5154 return -EINVAL; 5155 } 5156 5157 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]); 5158 5159 return 0; 5160} 5161 5162static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5163{ 5164 /* 5165 * Parses the init table segment that the bit entry points to. 5166 * 5167 * See parse_script_table_pointers for layout 5168 */ 5169 5170 if (bitentry->length < 14) { 5171 NV_ERROR(dev, "Do not understand init table\n"); 5172 return -EINVAL; 5173 } 5174 5175 parse_script_table_pointers(bios, bitentry->offset); 5176 5177 if (bitentry->length >= 16) 5178 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]); 5179 if (bitentry->length >= 18) 5180 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]); 5181 5182 return 0; 5183} 5184 5185static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5186{ 5187 /* 5188 * BIT 'i' (info?) table 5189 * 5190 * offset + 0 (32 bits): BIOS version dword (as in B table) 5191 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?) 5192 * offset + 13 (16 bits): pointer to table containing DAC load 5193 * detection comparison values 5194 * 5195 * There's other things in the table, purpose unknown 5196 */ 5197 5198 uint16_t daccmpoffset; 5199 uint8_t dacver, dacheaderlen; 5200 5201 if (bitentry->length < 6) { 5202 NV_ERROR(dev, "BIT i table too short for needed information\n"); 5203 return -EINVAL; 5204 } 5205 5206 parse_bios_version(dev, bios, bitentry->offset); 5207 5208 /* 5209 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's 5210 * Quadro identity crisis), other bits possibly as for BMP feature byte 5211 */ 5212 bios->feature_byte = bios->data[bitentry->offset + 5]; 5213 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; 5214 5215 if (bitentry->length < 15) { 5216 NV_WARN(dev, "BIT i table not long enough for DAC load " 5217 "detection comparison table\n"); 5218 return -EINVAL; 5219 } 5220 5221 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]); 5222 5223 /* doesn't exist on g80 */ 5224 if (!daccmpoffset) 5225 return 0; 5226 5227 /* 5228 * The first value in the table, following the header, is the 5229 * comparison value, the second entry is a comparison value for 5230 * TV load detection. 5231 */ 5232 5233 dacver = bios->data[daccmpoffset]; 5234 dacheaderlen = bios->data[daccmpoffset + 1]; 5235 5236 if (dacver != 0x00 && dacver != 0x10) { 5237 NV_WARN(dev, "DAC load detection comparison table version " 5238 "%d.%d not known\n", dacver >> 4, dacver & 0xf); 5239 return -ENOSYS; 5240 } 5241 5242 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); 5243 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); 5244 5245 return 0; 5246} 5247 5248static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5249{ 5250 /* 5251 * Parses the LVDS table segment that the bit entry points to. 5252 * Starting at bitentry->offset: 5253 * 5254 * offset + 0 (16 bits): LVDS strap xlate table pointer 5255 */ 5256 5257 if (bitentry->length != 2) { 5258 NV_ERROR(dev, "Do not understand BIT LVDS table\n"); 5259 return -EINVAL; 5260 } 5261 5262 /* 5263 * No idea if it's still called the LVDS manufacturer table, but 5264 * the concept's close enough. 5265 */ 5266 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]); 5267 5268 return 0; 5269} 5270 5271static int 5272parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5273 struct bit_entry *bitentry) 5274{ 5275 /* 5276 * offset + 2 (8 bits): number of options in an 5277 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set 5278 * offset + 3 (16 bits): pointer to strap xlate table for RAM 5279 * restrict option selection 5280 * 5281 * There's a bunch of bits in this table other than the RAM restrict 5282 * stuff that we don't use - their use currently unknown 5283 */ 5284 5285 /* 5286 * Older bios versions don't have a sufficiently long table for 5287 * what we want 5288 */ 5289 if (bitentry->length < 0x5) 5290 return 0; 5291 5292 if (bitentry->id[1] < 2) { 5293 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; 5294 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); 5295 } else { 5296 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; 5297 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); 5298 } 5299 5300 return 0; 5301} 5302 5303static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) 5304{ 5305 /* 5306 * Parses the pointer to the TMDS table 5307 * 5308 * Starting at bitentry->offset: 5309 * 5310 * offset + 0 (16 bits): TMDS table pointer 5311 * 5312 * The TMDS table is typically found just before the DCB table, with a 5313 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being 5314 * length?) 5315 * 5316 * At offset +7 is a pointer to a script, which I don't know how to 5317 * run yet. 5318 * At offset +9 is a pointer to another script, likewise 5319 * Offset +11 has a pointer to a table where the first word is a pxclk 5320 * frequency and the second word a pointer to a script, which should be 5321 * run if the comparison pxclk frequency is less than the pxclk desired. 5322 * This repeats for decreasing comparison frequencies 5323 * Offset +13 has a pointer to a similar table 5324 * The selection of table (and possibly +7/+9 script) is dictated by 5325 * "or" from the DCB. 5326 */ 5327 5328 uint16_t tmdstableptr, script1, script2; 5329 5330 if (bitentry->length != 2) { 5331 NV_ERROR(dev, "Do not understand BIT TMDS table\n"); 5332 return -EINVAL; 5333 } 5334 5335 tmdstableptr = ROM16(bios->data[bitentry->offset]); 5336 if (!tmdstableptr) { 5337 NV_ERROR(dev, "Pointer to TMDS table invalid\n"); 5338 return -EINVAL; 5339 } 5340 5341 NV_INFO(dev, "TMDS table version %d.%d\n", 5342 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); 5343 5344 /* nv50+ has v2.0, but we don't parse it atm */ 5345 if (bios->data[tmdstableptr] != 0x11) 5346 return -ENOSYS; 5347 5348 /* 5349 * These two scripts are odd: they don't seem to get run even when 5350 * they are not stubbed. 5351 */ 5352 script1 = ROM16(bios->data[tmdstableptr + 7]); 5353 script2 = ROM16(bios->data[tmdstableptr + 9]); 5354 if (bios->data[script1] != 'q' || bios->data[script2] != 'q') 5355 NV_WARN(dev, "TMDS table script pointers not stubbed\n"); 5356 5357 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); 5358 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); 5359 5360 return 0; 5361} 5362 5363static int 5364parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5365 struct bit_entry *bitentry) 5366{ 5367 /* 5368 * Parses the pointer to the G80 output script tables 5369 * 5370 * Starting at bitentry->offset: 5371 * 5372 * offset + 0 (16 bits): output script table pointer 5373 */ 5374 5375 uint16_t outputscripttableptr; 5376 5377 if (bitentry->length != 3) { 5378 NV_ERROR(dev, "Do not understand BIT U table\n"); 5379 return -EINVAL; 5380 } 5381 5382 outputscripttableptr = ROM16(bios->data[bitentry->offset]); 5383 bios->display.script_table_ptr = outputscripttableptr; 5384 return 0; 5385} 5386 5387static int 5388parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios, 5389 struct bit_entry *bitentry) 5390{ 5391 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]); 5392 return 0; 5393} 5394 5395struct bit_table { 5396 const char id; 5397 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *); 5398}; 5399 5400#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) 5401 5402static int 5403parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, 5404 struct bit_table *table) 5405{ 5406 struct drm_device *dev = bios->dev; 5407 uint8_t maxentries = bios->data[bitoffset + 4]; 5408 int i, offset; 5409 struct bit_entry bitentry; 5410 5411 for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) { 5412 bitentry.id[0] = bios->data[offset]; 5413 5414 if (bitentry.id[0] != table->id) 5415 continue; 5416 5417 bitentry.id[1] = bios->data[offset + 1]; 5418 bitentry.length = ROM16(bios->data[offset + 2]); 5419 bitentry.offset = ROM16(bios->data[offset + 4]); 5420 5421 return table->parse_fn(dev, bios, &bitentry); 5422 } 5423 5424 NV_INFO(dev, "BIT table '%c' not found\n", table->id); 5425 return -ENOSYS; 5426} 5427 5428static int 5429parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset) 5430{ 5431 int ret; 5432 5433 /* 5434 * The only restriction on parsing order currently is having 'i' first 5435 * for use of bios->*_version or bios->feature_byte while parsing; 5436 * functions shouldn't be actually *doing* anything apart from pulling 5437 * data from the image into the bios struct, thus no interdependencies 5438 */ 5439 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i)); 5440 if (ret) /* info? */ 5441 return ret; 5442 if (bios->major_version >= 0x60) /* g80+ */ 5443 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A)); 5444 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C)); 5445 if (ret) 5446 return ret; 5447 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display)); 5448 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init)); 5449 if (ret) 5450 return ret; 5451 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */ 5452 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); 5453 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds)); 5454 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U)); 5455 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport)); 5456 5457 return 0; 5458} 5459 5460static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset) 5461{ 5462 /* 5463 * Parses the BMP structure for useful things, but does not act on them 5464 * 5465 * offset + 5: BMP major version 5466 * offset + 6: BMP minor version 5467 * offset + 9: BMP feature byte 5468 * offset + 10: BCD encoded BIOS version 5469 * 5470 * offset + 18: init script table pointer (for bios versions < 5.10h) 5471 * offset + 20: extra init script table pointer (for bios 5472 * versions < 5.10h) 5473 * 5474 * offset + 24: memory init table pointer (used on early bios versions) 5475 * offset + 26: SDR memory sequencing setup data table 5476 * offset + 28: DDR memory sequencing setup data table 5477 * 5478 * offset + 54: index of I2C CRTC pair to use for CRT output 5479 * offset + 55: index of I2C CRTC pair to use for TV output 5480 * offset + 56: index of I2C CRTC pair to use for flat panel output 5481 * offset + 58: write CRTC index for I2C pair 0 5482 * offset + 59: read CRTC index for I2C pair 0 5483 * offset + 60: write CRTC index for I2C pair 1 5484 * offset + 61: read CRTC index for I2C pair 1 5485 * 5486 * offset + 67: maximum internal PLL frequency (single stage PLL) 5487 * offset + 71: minimum internal PLL frequency (single stage PLL) 5488 * 5489 * offset + 75: script table pointers, as described in 5490 * parse_script_table_pointers 5491 * 5492 * offset + 89: TMDS single link output A table pointer 5493 * offset + 91: TMDS single link output B table pointer 5494 * offset + 95: LVDS single link output A table pointer 5495 * offset + 105: flat panel timings table pointer 5496 * offset + 107: flat panel strapping translation table pointer 5497 * offset + 117: LVDS manufacturer panel config table pointer 5498 * offset + 119: LVDS manufacturer strapping translation table pointer 5499 * 5500 * offset + 142: PLL limits table pointer 5501 * 5502 * offset + 156: minimum pixel clock for LVDS dual link 5503 */ 5504 5505 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; 5506 uint16_t bmplength; 5507 uint16_t legacy_scripts_offset, legacy_i2c_offset; 5508 5509 /* load needed defaults in case we can't parse this info */ 5510 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX; 5511 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX; 5512 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX; 5513 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX; 5514 bios->digital_min_front_porch = 0x4b; 5515 bios->fmaxvco = 256000; 5516 bios->fminvco = 128000; 5517 bios->fp.duallink_transition_clk = 90000; 5518 5519 bmp_version_major = bmp[5]; 5520 bmp_version_minor = bmp[6]; 5521 5522 NV_TRACE(dev, "BMP version %d.%d\n", 5523 bmp_version_major, bmp_version_minor); 5524 5525 /* 5526 * Make sure that 0x36 is blank and can't be mistaken for a DCB 5527 * pointer on early versions 5528 */ 5529 if (bmp_version_major < 5) 5530 *(uint16_t *)&bios->data[0x36] = 0; 5531 5532 /* 5533 * Seems that the minor version was 1 for all major versions prior 5534 * to 5. Version 6 could theoretically exist, but I suspect BIT 5535 * happened instead. 5536 */ 5537 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { 5538 NV_ERROR(dev, "You have an unsupported BMP version. " 5539 "Please send in your bios\n"); 5540 return -ENOSYS; 5541 } 5542 5543 if (bmp_version_major == 0) 5544 /* nothing that's currently useful in this version */ 5545 return 0; 5546 else if (bmp_version_major == 1) 5547 bmplength = 44; /* exact for 1.01 */ 5548 else if (bmp_version_major == 2) 5549 bmplength = 48; /* exact for 2.01 */ 5550 else if (bmp_version_major == 3) 5551 bmplength = 54; 5552 /* guessed - mem init tables added in this version */ 5553 else if (bmp_version_major == 4 || bmp_version_minor < 0x1) 5554 /* don't know if 5.0 exists... */ 5555 bmplength = 62; 5556 /* guessed - BMP I2C indices added in version 4*/ 5557 else if (bmp_version_minor < 0x6) 5558 bmplength = 67; /* exact for 5.01 */ 5559 else if (bmp_version_minor < 0x10) 5560 bmplength = 75; /* exact for 5.06 */ 5561 else if (bmp_version_minor == 0x10) 5562 bmplength = 89; /* exact for 5.10h */ 5563 else if (bmp_version_minor < 0x14) 5564 bmplength = 118; /* exact for 5.11h */ 5565 else if (bmp_version_minor < 0x24) 5566 /* 5567 * Not sure of version where pll limits came in; 5568 * certainly exist by 0x24 though. 5569 */ 5570 /* length not exact: this is long enough to get lvds members */ 5571 bmplength = 123; 5572 else if (bmp_version_minor < 0x27) 5573 /* 5574 * Length not exact: this is long enough to get pll limit 5575 * member 5576 */ 5577 bmplength = 144; 5578 else 5579 /* 5580 * Length not exact: this is long enough to get dual link 5581 * transition clock. 5582 */ 5583 bmplength = 158; 5584 5585 /* checksum */ 5586 if (nv_cksum(bmp, 8)) { 5587 NV_ERROR(dev, "Bad BMP checksum\n"); 5588 return -EINVAL; 5589 } 5590 5591 /* 5592 * Bit 4 seems to indicate either a mobile bios or a quadro card -- 5593 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl 5594 * (not nv10gl), bit 5 that the flat panel tables are present, and 5595 * bit 6 a tv bios. 5596 */ 5597 bios->feature_byte = bmp[9]; 5598 5599 parse_bios_version(dev, bios, offset + 10); 5600 5601 if (bmp_version_major < 5 || bmp_version_minor < 0x10) 5602 bios->old_style_init = true; 5603 legacy_scripts_offset = 18; 5604 if (bmp_version_major < 2) 5605 legacy_scripts_offset -= 4; 5606 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]); 5607 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]); 5608 5609 if (bmp_version_major > 2) { /* appears in BMP 3 */ 5610 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]); 5611 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]); 5612 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]); 5613 } 5614 5615 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ 5616 if (bmplength > 61) 5617 legacy_i2c_offset = offset + 54; 5618 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; 5619 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; 5620 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; 5621 if (bios->data[legacy_i2c_offset + 4]) 5622 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4]; 5623 if (bios->data[legacy_i2c_offset + 5]) 5624 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5]; 5625 if (bios->data[legacy_i2c_offset + 6]) 5626 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6]; 5627 if (bios->data[legacy_i2c_offset + 7]) 5628 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7]; 5629 5630 if (bmplength > 74) { 5631 bios->fmaxvco = ROM32(bmp[67]); 5632 bios->fminvco = ROM32(bmp[71]); 5633 } 5634 if (bmplength > 88) 5635 parse_script_table_pointers(bios, offset + 75); 5636 if (bmplength > 94) { 5637 bios->tmds.output0_script_ptr = ROM16(bmp[89]); 5638 bios->tmds.output1_script_ptr = ROM16(bmp[91]); 5639 /* 5640 * Never observed in use with lvds scripts, but is reused for 5641 * 18/24 bit panel interface default for EDID equipped panels 5642 * (if_is_24bit not set directly to avoid any oscillation). 5643 */ 5644 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]); 5645 } 5646 if (bmplength > 108) { 5647 bios->fp.fptablepointer = ROM16(bmp[105]); 5648 bios->fp.fpxlatetableptr = ROM16(bmp[107]); 5649 bios->fp.xlatwidth = 1; 5650 } 5651 if (bmplength > 120) { 5652 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]); 5653 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]); 5654 } 5655 if (bmplength > 143) 5656 bios->pll_limit_tbl_ptr = ROM16(bmp[142]); 5657 5658 if (bmplength > 157) 5659 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10; 5660 5661 return 0; 5662} 5663 5664static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) 5665{ 5666 int i, j; 5667 5668 for (i = 0; i <= (n - len); i++) { 5669 for (j = 0; j < len; j++) 5670 if (data[i + j] != str[j]) 5671 break; 5672 if (j == len) 5673 return i; 5674 } 5675 5676 return 0; 5677} 5678 5679static struct dcb_gpio_entry * 5680new_gpio_entry(struct nvbios *bios) 5681{ 5682 struct dcb_gpio_table *gpio = &bios->dcb.gpio; 5683 5684 return &gpio->entry[gpio->entries++]; 5685} 5686 5687struct dcb_gpio_entry * 5688nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag) 5689{ 5690 struct drm_nouveau_private *dev_priv = dev->dev_private; 5691 struct nvbios *bios = &dev_priv->vbios; 5692 int i; 5693 5694 for (i = 0; i < bios->dcb.gpio.entries; i++) { 5695 if (bios->dcb.gpio.entry[i].tag != tag) 5696 continue; 5697 5698 return &bios->dcb.gpio.entry[i]; 5699 } 5700 5701 return NULL; 5702} 5703 5704static void 5705parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset) 5706{ 5707 struct dcb_gpio_entry *gpio; 5708 uint16_t ent = ROM16(bios->data[offset]); 5709 uint8_t line = ent & 0x1f, 5710 tag = ent >> 5 & 0x3f, 5711 flags = ent >> 11 & 0x1f; 5712 5713 if (tag == 0x3f) 5714 return; 5715 5716 gpio = new_gpio_entry(bios); 5717 5718 gpio->tag = tag; 5719 gpio->line = line; 5720 gpio->invert = flags != 4; 5721 gpio->entry = ent; 5722} 5723 5724static void 5725parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) 5726{ 5727 uint32_t entry = ROM32(bios->data[offset]); 5728 struct dcb_gpio_entry *gpio; 5729 5730 if ((entry & 0x0000ff00) == 0x0000ff00) 5731 return; 5732 5733 gpio = new_gpio_entry(bios); 5734 gpio->tag = (entry & 0x0000ff00) >> 8; 5735 gpio->line = (entry & 0x0000001f) >> 0; 5736 gpio->state_default = (entry & 0x01000000) >> 24; 5737 gpio->state[0] = (entry & 0x18000000) >> 27; 5738 gpio->state[1] = (entry & 0x60000000) >> 29; 5739 gpio->entry = entry; 5740} 5741 5742static void 5743parse_dcb_gpio_table(struct nvbios *bios) 5744{ 5745 struct drm_device *dev = bios->dev; 5746 uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr; 5747 uint8_t *gpio_table = &bios->data[gpio_table_ptr]; 5748 int header_len = gpio_table[1], 5749 entries = gpio_table[2], 5750 entry_len = gpio_table[3]; 5751 void (*parse_entry)(struct nvbios *, uint16_t) = NULL; 5752 int i; 5753 5754 if (bios->dcb.version >= 0x40) { 5755 if (gpio_table_ptr && entry_len != 4) { 5756 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5757 return; 5758 } 5759 5760 parse_entry = parse_dcb40_gpio_entry; 5761 5762 } else if (bios->dcb.version >= 0x30) { 5763 if (gpio_table_ptr && entry_len != 2) { 5764 NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); 5765 return; 5766 } 5767 5768 parse_entry = parse_dcb30_gpio_entry; 5769 5770 } else if (bios->dcb.version >= 0x22) { 5771 /* 5772 * DCBs older than v3.0 don't really have a GPIO 5773 * table, instead they keep some GPIO info at fixed 5774 * locations. 5775 */ 5776 uint16_t dcbptr = ROM16(bios->data[0x36]); 5777 uint8_t *tvdac_gpio = &bios->data[dcbptr - 5]; 5778 5779 if (tvdac_gpio[0] & 1) { 5780 struct dcb_gpio_entry *gpio = new_gpio_entry(bios); 5781 5782 gpio->tag = DCB_GPIO_TVDAC0; 5783 gpio->line = tvdac_gpio[1] >> 4; 5784 gpio->invert = tvdac_gpio[0] & 2; 5785 } 5786 } else { 5787 /* 5788 * No systematic way to store GPIO info on pre-v2.2 5789 * DCBs, try to match the PCI device IDs. 5790 */ 5791 5792 /* Apple iMac G4 NV18 */ 5793 if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) { 5794 struct dcb_gpio_entry *gpio = new_gpio_entry(bios); 5795 5796 gpio->tag = DCB_GPIO_TVDAC0; 5797 gpio->line = 4; 5798 } 5799 5800 } 5801 5802 if (!gpio_table_ptr) 5803 return; 5804 5805 if (entries > DCB_MAX_NUM_GPIO_ENTRIES) { 5806 NV_WARN(dev, "Too many entries in the DCB GPIO table.\n"); 5807 entries = DCB_MAX_NUM_GPIO_ENTRIES; 5808 } 5809 5810 for (i = 0; i < entries; i++) 5811 parse_entry(bios, gpio_table_ptr + header_len + entry_len * i); 5812} 5813 5814struct dcb_connector_table_entry * 5815nouveau_bios_connector_entry(struct drm_device *dev, int index) 5816{ 5817 struct drm_nouveau_private *dev_priv = dev->dev_private; 5818 struct nvbios *bios = &dev_priv->vbios; 5819 struct dcb_connector_table_entry *cte; 5820 5821 if (index >= bios->dcb.connector.entries) 5822 return NULL; 5823 5824 cte = &bios->dcb.connector.entry[index]; 5825 if (cte->type == 0xff) 5826 return NULL; 5827 5828 return cte; 5829} 5830 5831static enum dcb_connector_type 5832divine_connector_type(struct nvbios *bios, int index) 5833{ 5834 struct dcb_table *dcb = &bios->dcb; 5835 unsigned encoders = 0, type = DCB_CONNECTOR_NONE; 5836 int i; 5837 5838 for (i = 0; i < dcb->entries; i++) { 5839 if (dcb->entry[i].connector == index) 5840 encoders |= (1 << dcb->entry[i].type); 5841 } 5842 5843 if (encoders & (1 << OUTPUT_DP)) { 5844 if (encoders & (1 << OUTPUT_TMDS)) 5845 type = DCB_CONNECTOR_DP; 5846 else 5847 type = DCB_CONNECTOR_eDP; 5848 } else 5849 if (encoders & (1 << OUTPUT_TMDS)) { 5850 if (encoders & (1 << OUTPUT_ANALOG)) 5851 type = DCB_CONNECTOR_DVI_I; 5852 else 5853 type = DCB_CONNECTOR_DVI_D; 5854 } else 5855 if (encoders & (1 << OUTPUT_ANALOG)) { 5856 type = DCB_CONNECTOR_VGA; 5857 } else 5858 if (encoders & (1 << OUTPUT_LVDS)) { 5859 type = DCB_CONNECTOR_LVDS; 5860 } else 5861 if (encoders & (1 << OUTPUT_TV)) { 5862 type = DCB_CONNECTOR_TV_0; 5863 } 5864 5865 return type; 5866} 5867 5868static void 5869apply_dcb_connector_quirks(struct nvbios *bios, int idx) 5870{ 5871 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx]; 5872 struct drm_device *dev = bios->dev; 5873 5874 /* Gigabyte NX85T */ 5875 if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) { 5876 if (cte->type == DCB_CONNECTOR_HDMI_1) 5877 cte->type = DCB_CONNECTOR_DVI_I; 5878 } 5879} 5880 5881static void 5882parse_dcb_connector_table(struct nvbios *bios) 5883{ 5884 struct drm_device *dev = bios->dev; 5885 struct dcb_connector_table *ct = &bios->dcb.connector; 5886 struct dcb_connector_table_entry *cte; 5887 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr]; 5888 uint8_t *entry; 5889 int i; 5890 5891 if (!bios->dcb.connector_table_ptr) { 5892 NV_DEBUG_KMS(dev, "No DCB connector table present\n"); 5893 return; 5894 } 5895 5896 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n", 5897 conntab[0], conntab[1], conntab[2], conntab[3]); 5898 if ((conntab[0] != 0x30 && conntab[0] != 0x40) || 5899 (conntab[3] != 2 && conntab[3] != 4)) { 5900 NV_ERROR(dev, " Unknown! Please report.\n"); 5901 return; 5902 } 5903 5904 ct->entries = conntab[2]; 5905 5906 entry = conntab + conntab[1]; 5907 cte = &ct->entry[0]; 5908 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) { 5909 cte->index = i; 5910 if (conntab[3] == 2) 5911 cte->entry = ROM16(entry[0]); 5912 else 5913 cte->entry = ROM32(entry[0]); 5914 5915 cte->type = (cte->entry & 0x000000ff) >> 0; 5916 cte->index2 = (cte->entry & 0x00000f00) >> 8; 5917 switch (cte->entry & 0x00033000) { 5918 case 0x00001000: 5919 cte->gpio_tag = 0x07; 5920 break; 5921 case 0x00002000: 5922 cte->gpio_tag = 0x08; 5923 break; 5924 case 0x00010000: 5925 cte->gpio_tag = 0x51; 5926 break; 5927 case 0x00020000: 5928 cte->gpio_tag = 0x52; 5929 break; 5930 default: 5931 cte->gpio_tag = 0xff; 5932 break; 5933 } 5934 5935 if (cte->type == 0xff) 5936 continue; 5937 5938 apply_dcb_connector_quirks(bios, i); 5939 5940 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n", 5941 i, cte->entry, cte->type, cte->index, cte->gpio_tag); 5942 5943 /* check for known types, fallback to guessing the type 5944 * from attached encoders if we hit an unknown. 5945 */ 5946 switch (cte->type) { 5947 case DCB_CONNECTOR_VGA: 5948 case DCB_CONNECTOR_TV_0: 5949 case DCB_CONNECTOR_TV_1: 5950 case DCB_CONNECTOR_TV_3: 5951 case DCB_CONNECTOR_DVI_I: 5952 case DCB_CONNECTOR_DVI_D: 5953 case DCB_CONNECTOR_LVDS: 5954 case DCB_CONNECTOR_DP: 5955 case DCB_CONNECTOR_eDP: 5956 case DCB_CONNECTOR_HDMI_0: 5957 case DCB_CONNECTOR_HDMI_1: 5958 break; 5959 default: 5960 cte->type = divine_connector_type(bios, cte->index); 5961 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type); 5962 break; 5963 } 5964 5965 if (nouveau_override_conntype) { 5966 int type = divine_connector_type(bios, cte->index); 5967 if (type != cte->type) 5968 NV_WARN(dev, " -> type 0x%02x\n", cte->type); 5969 } 5970 5971 } 5972} 5973 5974static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) 5975{ 5976 struct dcb_entry *entry = &dcb->entry[dcb->entries]; 5977 5978 memset(entry, 0, sizeof(struct dcb_entry)); 5979 entry->index = dcb->entries++; 5980 5981 return entry; 5982} 5983 5984static void fabricate_vga_output(struct dcb_table *dcb, int i2c, int heads) 5985{ 5986 struct dcb_entry *entry = new_dcb_entry(dcb); 5987 5988 entry->type = 0; 5989 entry->i2c_index = i2c; 5990 entry->heads = heads; 5991 entry->location = DCB_LOC_ON_CHIP; 5992 entry->or = 1; 5993} 5994 5995static void fabricate_dvi_i_output(struct dcb_table *dcb, bool twoHeads) 5996{ 5997 struct dcb_entry *entry = new_dcb_entry(dcb); 5998 5999 entry->type = 2; 6000 entry->i2c_index = LEGACY_I2C_PANEL; 6001 entry->heads = twoHeads ? 3 : 1; 6002 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 6003 entry->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */ 6004 entry->duallink_possible = false; /* SiI164 and co. are single link */ 6005 6006} 6007 6008static void fabricate_tv_output(struct dcb_table *dcb, bool twoHeads) 6009{ 6010 struct dcb_entry *entry = new_dcb_entry(dcb); 6011 6012 entry->type = 1; 6013 entry->i2c_index = LEGACY_I2C_TV; 6014 entry->heads = twoHeads ? 3 : 1; 6015 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ 6016} 6017 6018static bool 6019parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 6020 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 6021{ 6022 entry->type = conn & 0xf; 6023 entry->i2c_index = (conn >> 4) & 0xf; 6024 entry->heads = (conn >> 8) & 0xf; 6025 if (dcb->version >= 0x40) 6026 entry->connector = (conn >> 12) & 0xf; 6027 entry->bus = (conn >> 16) & 0xf; 6028 entry->location = (conn >> 20) & 0x3; 6029 entry->or = (conn >> 24) & 0xf; 6030 6031 switch (entry->type) { 6032 case OUTPUT_ANALOG: 6033 /* 6034 * Although the rest of a CRT conf dword is usually 6035 * zeros, mac biosen have stuff there so we must mask 6036 */ 6037 entry->crtconf.maxfreq = (dcb->version < 0x30) ? 6038 (conf & 0xffff) * 10 : 6039 (conf & 0xff) * 10000; 6040 break; 6041 case OUTPUT_LVDS: 6042 { 6043 uint32_t mask; 6044 if (conf & 0x1) 6045 entry->lvdsconf.use_straps_for_mode = true; 6046 if (dcb->version < 0x22) { 6047 mask = ~0xd; 6048 /* 6049 * The laptop in bug 14567 lies and claims to not use 6050 * straps when it does, so assume all DCB 2.0 laptops 6051 * use straps, until a broken EDID using one is produced 6052 */ 6053 entry->lvdsconf.use_straps_for_mode = true; 6054 /* 6055 * Both 0x4 and 0x8 show up in v2.0 tables; assume they 6056 * mean the same thing (probably wrong, but might work) 6057 */ 6058 if (conf & 0x4 || conf & 0x8) 6059 entry->lvdsconf.use_power_scripts = true; 6060 } else { 6061 mask = ~0x7; 6062 if (conf & 0x2) 6063 entry->lvdsconf.use_acpi_for_edid = true; 6064 if (conf & 0x4) 6065 entry->lvdsconf.use_power_scripts = true; 6066 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; 6067 } 6068 if (conf & mask) { 6069 /* 6070 * Until we even try to use these on G8x, it's 6071 * useless reporting unknown bits. They all are. 6072 */ 6073 if (dcb->version >= 0x40) 6074 break; 6075 6076 NV_ERROR(dev, "Unknown LVDS configuration bits, " 6077 "please report\n"); 6078 } 6079 break; 6080 } 6081 case OUTPUT_TV: 6082 { 6083 if (dcb->version >= 0x30) 6084 entry->tvconf.has_component_output = conf & (0x8 << 4); 6085 else 6086 entry->tvconf.has_component_output = false; 6087 6088 break; 6089 } 6090 case OUTPUT_DP: 6091 entry->dpconf.sor.link = (conf & 0x00000030) >> 4; 6092 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21; 6093 switch ((conf & 0x0f000000) >> 24) { 6094 case 0xf: 6095 entry->dpconf.link_nr = 4; 6096 break; 6097 case 0x3: 6098 entry->dpconf.link_nr = 2; 6099 break; 6100 default: 6101 entry->dpconf.link_nr = 1; 6102 break; 6103 } 6104 break; 6105 case OUTPUT_TMDS: 6106 if (dcb->version >= 0x40) 6107 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; 6108 else if (dcb->version >= 0x30) 6109 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8; 6110 else if (dcb->version >= 0x22) 6111 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4; 6112 6113 break; 6114 case OUTPUT_EOL: 6115 /* weird g80 mobile type that "nv" treats as a terminator */ 6116 dcb->entries--; 6117 return false; 6118 default: 6119 break; 6120 } 6121 6122 if (dcb->version < 0x40) { 6123 /* Normal entries consist of a single bit, but dual link has 6124 * the next most significant bit set too 6125 */ 6126 entry->duallink_possible = 6127 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); 6128 } else { 6129 entry->duallink_possible = (entry->sorconf.link == 3); 6130 } 6131 6132 /* unsure what DCB version introduces this, 3.0? */ 6133 if (conf & 0x100000) 6134 entry->i2c_upper_default = true; 6135 6136 return true; 6137} 6138 6139static bool 6140parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, 6141 uint32_t conn, uint32_t conf, struct dcb_entry *entry) 6142{ 6143 switch (conn & 0x0000000f) { 6144 case 0: 6145 entry->type = OUTPUT_ANALOG; 6146 break; 6147 case 1: 6148 entry->type = OUTPUT_TV; 6149 break; 6150 case 2: 6151 case 4: 6152 if (conn & 0x10) 6153 entry->type = OUTPUT_LVDS; 6154 else 6155 entry->type = OUTPUT_TMDS; 6156 break; 6157 case 3: 6158 entry->type = OUTPUT_LVDS; 6159 break; 6160 default: 6161 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 6162 return false; 6163 } 6164 6165 entry->i2c_index = (conn & 0x0003c000) >> 14; 6166 entry->heads = ((conn & 0x001c0000) >> 18) + 1; 6167 entry->or = entry->heads; /* same as heads, hopefully safe enough */ 6168 entry->location = (conn & 0x01e00000) >> 21; 6169 entry->bus = (conn & 0x0e000000) >> 25; 6170 entry->duallink_possible = false; 6171 6172 switch (entry->type) { 6173 case OUTPUT_ANALOG: 6174 entry->crtconf.maxfreq = (conf & 0xffff) * 10; 6175 break; 6176 case OUTPUT_TV: 6177 entry->tvconf.has_component_output = false; 6178 break; 6179 case OUTPUT_LVDS: 6180 if ((conn & 0x00003f00) != 0x10) 6181 entry->lvdsconf.use_straps_for_mode = true; 6182 entry->lvdsconf.use_power_scripts = true; 6183 break; 6184 default: 6185 break; 6186 } 6187 6188 return true; 6189} 6190 6191static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb, 6192 uint32_t conn, uint32_t conf) 6193{ 6194 struct dcb_entry *entry = new_dcb_entry(dcb); 6195 bool ret; 6196 6197 if (dcb->version >= 0x20) 6198 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); 6199 else 6200 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); 6201 if (!ret) 6202 return ret; 6203 6204 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 6205 entry->i2c_index, &dcb->i2c[entry->i2c_index]); 6206 6207 return true; 6208} 6209 6210static 6211void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) 6212{ 6213 /* 6214 * DCB v2.0 lists each output combination separately. 6215 * Here we merge compatible entries to have fewer outputs, with 6216 * more options 6217 */ 6218 6219 int i, newentries = 0; 6220 6221 for (i = 0; i < dcb->entries; i++) { 6222 struct dcb_entry *ient = &dcb->entry[i]; 6223 int j; 6224 6225 for (j = i + 1; j < dcb->entries; j++) { 6226 struct dcb_entry *jent = &dcb->entry[j]; 6227 6228 if (jent->type == 100) /* already merged entry */ 6229 continue; 6230 6231 /* merge heads field when all other fields the same */ 6232 if (jent->i2c_index == ient->i2c_index && 6233 jent->type == ient->type && 6234 jent->location == ient->location && 6235 jent->or == ient->or) { 6236 NV_TRACE(dev, "Merging DCB entries %d and %d\n", 6237 i, j); 6238 ient->heads |= jent->heads; 6239 jent->type = 100; /* dummy value */ 6240 } 6241 } 6242 } 6243 6244 /* Compact entries merged into others out of dcb */ 6245 for (i = 0; i < dcb->entries; i++) { 6246 if (dcb->entry[i].type == 100) 6247 continue; 6248 6249 if (newentries != i) { 6250 dcb->entry[newentries] = dcb->entry[i]; 6251 dcb->entry[newentries].index = newentries; 6252 } 6253 newentries++; 6254 } 6255 6256 dcb->entries = newentries; 6257} 6258 6259static bool 6260apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf) 6261{ 6262 /* Dell Precision M6300 6263 * DCB entry 2: 02025312 00000010 6264 * DCB entry 3: 02026312 00000020 6265 * 6266 * Identical, except apparently a different connector on a 6267 * different SOR link. Not a clue how we're supposed to know 6268 * which one is in use if it even shares an i2c line... 6269 * 6270 * Ignore the connector on the second SOR link to prevent 6271 * nasty problems until this is sorted (assuming it's not a 6272 * VBIOS bug). 6273 */ 6274 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) { 6275 if (*conn == 0x02026312 && *conf == 0x00000020) 6276 return false; 6277 } 6278 6279 return true; 6280} 6281 6282static int 6283parse_dcb_table(struct drm_device *dev, struct nvbios *bios, bool twoHeads) 6284{ 6285 struct drm_nouveau_private *dev_priv = dev->dev_private; 6286 struct dcb_table *dcb = &bios->dcb; 6287 uint16_t dcbptr = 0, i2ctabptr = 0; 6288 uint8_t *dcbtable; 6289 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES; 6290 bool configblock = true; 6291 int recordlength = 8, confofs = 4; 6292 int i; 6293 6294 /* get the offset from 0x36 */ 6295 if (dev_priv->card_type > NV_04) { 6296 dcbptr = ROM16(bios->data[0x36]); 6297 if (dcbptr == 0x0000) 6298 NV_WARN(dev, "No output data (DCB) found in BIOS\n"); 6299 } 6300 6301 /* this situation likely means a really old card, pre DCB */ 6302 if (dcbptr == 0x0) { 6303 NV_INFO(dev, "Assuming a CRT output exists\n"); 6304 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 6305 6306 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) 6307 fabricate_tv_output(dcb, twoHeads); 6308 6309 return 0; 6310 } 6311 6312 dcbtable = &bios->data[dcbptr]; 6313 6314 /* get DCB version */ 6315 dcb->version = dcbtable[0]; 6316 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n", 6317 dcb->version >> 4, dcb->version & 0xf); 6318 6319 if (dcb->version >= 0x20) { /* NV17+ */ 6320 uint32_t sig; 6321 6322 if (dcb->version >= 0x30) { /* NV40+ */ 6323 headerlen = dcbtable[1]; 6324 entries = dcbtable[2]; 6325 recordlength = dcbtable[3]; 6326 i2ctabptr = ROM16(dcbtable[4]); 6327 sig = ROM32(dcbtable[6]); 6328 dcb->gpio_table_ptr = ROM16(dcbtable[10]); 6329 dcb->connector_table_ptr = ROM16(dcbtable[20]); 6330 } else { 6331 i2ctabptr = ROM16(dcbtable[2]); 6332 sig = ROM32(dcbtable[4]); 6333 headerlen = 8; 6334 } 6335 6336 if (sig != 0x4edcbdcb) { 6337 NV_ERROR(dev, "Bad Display Configuration Block " 6338 "signature (%08X)\n", sig); 6339 return -EINVAL; 6340 } 6341 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */ 6342 char sig[8] = { 0 }; 6343 6344 strncpy(sig, (char *)&dcbtable[-7], 7); 6345 i2ctabptr = ROM16(dcbtable[2]); 6346 recordlength = 10; 6347 confofs = 6; 6348 6349 if (strcmp(sig, "DEV_REC")) { 6350 NV_ERROR(dev, "Bad Display Configuration Block " 6351 "signature (%s)\n", sig); 6352 return -EINVAL; 6353 } 6354 } else { 6355 /* 6356 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always 6357 * has the same single (crt) entry, even when tv-out present, so 6358 * the conclusion is this version cannot really be used. 6359 * v1.2 tables (some NV6/10, and NV15+) normally have the same 6360 * 5 entries, which are not specific to the card and so no use. 6361 * v1.2 does have an I2C table that read_dcb_i2c_table can 6362 * handle, but cards exist (nv11 in #14821) with a bad i2c table 6363 * pointer, so use the indices parsed in parse_bmp_structure. 6364 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful 6365 */ 6366 NV_TRACEWARN(dev, "No useful information in BIOS output table; " 6367 "adding all possible outputs\n"); 6368 fabricate_vga_output(dcb, LEGACY_I2C_CRT, 1); 6369 6370 /* 6371 * Attempt to detect TV before DVI because the test 6372 * for the former is more accurate and it rules the 6373 * latter out. 6374 */ 6375 if (nv04_tv_identify(dev, 6376 bios->legacy.i2c_indices.tv) >= 0) 6377 fabricate_tv_output(dcb, twoHeads); 6378 6379 else if (bios->tmds.output0_script_ptr || 6380 bios->tmds.output1_script_ptr) 6381 fabricate_dvi_i_output(dcb, twoHeads); 6382 6383 return 0; 6384 } 6385 6386 if (!i2ctabptr) 6387 NV_WARN(dev, "No pointer to DCB I2C port table\n"); 6388 else { 6389 dcb->i2c_table = &bios->data[i2ctabptr]; 6390 if (dcb->version >= 0x30) 6391 dcb->i2c_default_indices = dcb->i2c_table[4]; 6392 6393 /* 6394 * Parse the "management" I2C bus, used for hardware 6395 * monitoring and some external TMDS transmitters. 6396 */ 6397 if (dcb->version >= 0x22) { 6398 int idx = (dcb->version >= 0x40 ? 6399 dcb->i2c_default_indices & 0xf : 6400 2); 6401 6402 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table, 6403 idx, &dcb->i2c[idx]); 6404 } 6405 } 6406 6407 if (entries > DCB_MAX_NUM_ENTRIES) 6408 entries = DCB_MAX_NUM_ENTRIES; 6409 6410 for (i = 0; i < entries; i++) { 6411 uint32_t connection, config = 0; 6412 6413 connection = ROM32(dcbtable[headerlen + recordlength * i]); 6414 if (configblock) 6415 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]); 6416 6417 /* seen on an NV11 with DCB v1.5 */ 6418 if (connection == 0x00000000) 6419 break; 6420 6421 /* seen on an NV17 with DCB v2.0 */ 6422 if (connection == 0xffffffff) 6423 break; 6424 6425 if ((connection & 0x0000000f) == 0x0000000f) 6426 continue; 6427 6428 if (!apply_dcb_encoder_quirks(dev, i, &connection, &config)) 6429 continue; 6430 6431 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n", 6432 dcb->entries, connection, config); 6433 6434 if (!parse_dcb_entry(dev, dcb, connection, config)) 6435 break; 6436 } 6437 6438 /* 6439 * apart for v2.1+ not being known for requiring merging, this 6440 * guarantees dcbent->index is the index of the entry in the rom image 6441 */ 6442 if (dcb->version < 0x21) 6443 merge_like_dcb_entries(dev, dcb); 6444 6445 if (!dcb->entries) 6446 return -ENXIO; 6447 6448 parse_dcb_gpio_table(bios); 6449 parse_dcb_connector_table(bios); 6450 return 0; 6451} 6452 6453static void 6454fixup_legacy_connector(struct nvbios *bios) 6455{ 6456 struct dcb_table *dcb = &bios->dcb; 6457 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { }; 6458 6459 /* 6460 * DCB 3.0 also has the table in most cases, but there are some cards 6461 * where the table is filled with stub entries, and the DCB entriy 6462 * indices are all 0. We don't need the connector indices on pre-G80 6463 * chips (yet?) so limit the use to DCB 4.0 and above. 6464 */ 6465 if (dcb->version >= 0x40) 6466 return; 6467 6468 dcb->connector.entries = 0; 6469 6470 /* 6471 * No known connector info before v3.0, so make it up. the rule here 6472 * is: anything on the same i2c bus is considered to be on the same 6473 * connector. any output without an associated i2c bus is assigned 6474 * its own unique connector index. 6475 */ 6476 for (i = 0; i < dcb->entries; i++) { 6477 /* 6478 * Ignore the I2C index for on-chip TV-out, as there 6479 * are cards with bogus values (nv31m in bug 23212), 6480 * and it's otherwise useless. 6481 */ 6482 if (dcb->entry[i].type == OUTPUT_TV && 6483 dcb->entry[i].location == DCB_LOC_ON_CHIP) 6484 dcb->entry[i].i2c_index = 0xf; 6485 i2c = dcb->entry[i].i2c_index; 6486 6487 if (i2c_conn[i2c]) { 6488 dcb->entry[i].connector = i2c_conn[i2c] - 1; 6489 continue; 6490 } 6491 6492 dcb->entry[i].connector = dcb->connector.entries++; 6493 if (i2c != 0xf) 6494 i2c_conn[i2c] = dcb->connector.entries; 6495 } 6496 6497 /* Fake the connector table as well as just connector indices */ 6498 for (i = 0; i < dcb->connector.entries; i++) { 6499 dcb->connector.entry[i].index = i; 6500 dcb->connector.entry[i].type = divine_connector_type(bios, i); 6501 dcb->connector.entry[i].gpio_tag = 0xff; 6502 } 6503} 6504 6505static void 6506fixup_legacy_i2c(struct nvbios *bios) 6507{ 6508 struct dcb_table *dcb = &bios->dcb; 6509 int i; 6510 6511 for (i = 0; i < dcb->entries; i++) { 6512 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT) 6513 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt; 6514 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL) 6515 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel; 6516 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV) 6517 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv; 6518 } 6519} 6520 6521static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) 6522{ 6523 /* 6524 * The header following the "HWSQ" signature has the number of entries, 6525 * and the entry size 6526 * 6527 * An entry consists of a dword to write to the sequencer control reg 6528 * (0x00001304), followed by the ucode bytes, written sequentially, 6529 * starting at reg 0x00001400 6530 */ 6531 6532 uint8_t bytes_to_write; 6533 uint16_t hwsq_entry_offset; 6534 int i; 6535 6536 if (bios->data[hwsq_offset] <= entry) { 6537 NV_ERROR(dev, "Too few entries in HW sequencer table for " 6538 "requested entry\n"); 6539 return -ENOENT; 6540 } 6541 6542 bytes_to_write = bios->data[hwsq_offset + 1]; 6543 6544 if (bytes_to_write != 36) { 6545 NV_ERROR(dev, "Unknown HW sequencer entry size\n"); 6546 return -EINVAL; 6547 } 6548 6549 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n"); 6550 6551 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; 6552 6553 /* set sequencer control */ 6554 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); 6555 bytes_to_write -= 4; 6556 6557 /* write ucode */ 6558 for (i = 0; i < bytes_to_write; i += 4) 6559 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); 6560 6561 /* twiddle NV_PBUS_DEBUG_4 */ 6562 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18); 6563 6564 return 0; 6565} 6566 6567static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, 6568 struct nvbios *bios) 6569{ 6570 /* 6571 * BMP based cards, from NV17, need a microcode loading to correctly 6572 * control the GPIO etc for LVDS panels 6573 * 6574 * BIT based cards seem to do this directly in the init scripts 6575 * 6576 * The microcode entries are found by the "HWSQ" signature. 6577 */ 6578 6579 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' }; 6580 const int sz = sizeof(hwsq_signature); 6581 int hwsq_offset; 6582 6583 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz); 6584 if (!hwsq_offset) 6585 return 0; 6586 6587 /* always use entry 0? */ 6588 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); 6589} 6590 6591uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) 6592{ 6593 struct drm_nouveau_private *dev_priv = dev->dev_private; 6594 struct nvbios *bios = &dev_priv->vbios; 6595 const uint8_t edid_sig[] = { 6596 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; 6597 uint16_t offset = 0; 6598 uint16_t newoffset; 6599 int searchlen = NV_PROM_SIZE; 6600 6601 if (bios->fp.edid) 6602 return bios->fp.edid; 6603 6604 while (searchlen) { 6605 newoffset = findstr(&bios->data[offset], searchlen, 6606 edid_sig, 8); 6607 if (!newoffset) 6608 return NULL; 6609 offset += newoffset; 6610 if (!nv_cksum(&bios->data[offset], EDID1_LEN)) 6611 break; 6612 6613 searchlen -= offset; 6614 offset++; 6615 } 6616 6617 NV_TRACE(dev, "Found EDID in BIOS\n"); 6618 6619 return bios->fp.edid = &bios->data[offset]; 6620} 6621 6622void 6623nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, 6624 struct dcb_entry *dcbent) 6625{ 6626 struct drm_nouveau_private *dev_priv = dev->dev_private; 6627 struct nvbios *bios = &dev_priv->vbios; 6628 struct init_exec iexec = { true, false }; 6629 6630 mutex_lock(&bios->lock); 6631 bios->display.output = dcbent; 6632 parse_init_table(bios, table, &iexec); 6633 bios->display.output = NULL; 6634 mutex_unlock(&bios->lock); 6635} 6636 6637static bool NVInitVBIOS(struct drm_device *dev) 6638{ 6639 struct drm_nouveau_private *dev_priv = dev->dev_private; 6640 struct nvbios *bios = &dev_priv->vbios; 6641 6642 memset(bios, 0, sizeof(struct nvbios)); 6643 mutex_init(&bios->lock); 6644 bios->dev = dev; 6645 6646 if (!NVShadowVBIOS(dev, bios->data)) 6647 return false; 6648 6649 bios->length = NV_PROM_SIZE; 6650 return true; 6651} 6652 6653static int nouveau_parse_vbios_struct(struct drm_device *dev) 6654{ 6655 struct drm_nouveau_private *dev_priv = dev->dev_private; 6656 struct nvbios *bios = &dev_priv->vbios; 6657 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; 6658 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; 6659 int offset; 6660 6661 offset = findstr(bios->data, bios->length, 6662 bit_signature, sizeof(bit_signature)); 6663 if (offset) { 6664 NV_TRACE(dev, "BIT BIOS found\n"); 6665 return parse_bit_structure(bios, offset + 6); 6666 } 6667 6668 offset = findstr(bios->data, bios->length, 6669 bmp_signature, sizeof(bmp_signature)); 6670 if (offset) { 6671 NV_TRACE(dev, "BMP BIOS found\n"); 6672 return parse_bmp_structure(dev, bios, offset); 6673 } 6674 6675 NV_ERROR(dev, "No known BIOS signature found\n"); 6676 return -ENODEV; 6677} 6678 6679int 6680nouveau_run_vbios_init(struct drm_device *dev) 6681{ 6682 struct drm_nouveau_private *dev_priv = dev->dev_private; 6683 struct nvbios *bios = &dev_priv->vbios; 6684 int i, ret = 0; 6685 6686 /* Reset the BIOS head to 0. */ 6687 bios->state.crtchead = 0; 6688 6689 if (bios->major_version < 5) /* BMP only */ 6690 load_nv17_hw_sequencer_ucode(dev, bios); 6691 6692 if (bios->execute) { 6693 bios->fp.last_script_invoc = 0; 6694 bios->fp.lvds_init_run = false; 6695 } 6696 6697 parse_init_tables(bios); 6698 6699 /* 6700 * Runs some additional script seen on G8x VBIOSen. The VBIOS' 6701 * parser will run this right after the init tables, the binary 6702 * driver appears to run it at some point later. 6703 */ 6704 if (bios->some_script_ptr) { 6705 struct init_exec iexec = {true, false}; 6706 6707 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n", 6708 bios->some_script_ptr); 6709 parse_init_table(bios, bios->some_script_ptr, &iexec); 6710 } 6711 6712 if (dev_priv->card_type >= NV_50) { 6713 for (i = 0; i < bios->dcb.entries; i++) { 6714 nouveau_bios_run_display_table(dev, 6715 &bios->dcb.entry[i], 6716 0, 0); 6717 } 6718 } 6719 6720 return ret; 6721} 6722 6723static void 6724nouveau_bios_i2c_devices_takedown(struct drm_device *dev) 6725{ 6726 struct drm_nouveau_private *dev_priv = dev->dev_private; 6727 struct nvbios *bios = &dev_priv->vbios; 6728 struct dcb_i2c_entry *entry; 6729 int i; 6730 6731 entry = &bios->dcb.i2c[0]; 6732 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++) 6733 nouveau_i2c_fini(dev, entry); 6734} 6735 6736static bool 6737nouveau_bios_posted(struct drm_device *dev) 6738{ 6739 struct drm_nouveau_private *dev_priv = dev->dev_private; 6740 unsigned htotal; 6741 6742 if (dev_priv->chipset >= NV_50) { 6743 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 && 6744 NVReadVgaCrtc(dev, 0, 0x1a) == 0) 6745 return false; 6746 return true; 6747 } 6748 6749 htotal = NVReadVgaCrtc(dev, 0, 0x06); 6750 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8; 6751 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4; 6752 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10; 6753 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11; 6754 6755 return (htotal != 0); 6756} 6757 6758int 6759nouveau_bios_init(struct drm_device *dev) 6760{ 6761 struct drm_nouveau_private *dev_priv = dev->dev_private; 6762 struct nvbios *bios = &dev_priv->vbios; 6763 int ret; 6764 6765 if (!NVInitVBIOS(dev)) 6766 return -ENODEV; 6767 6768 ret = nouveau_parse_vbios_struct(dev); 6769 if (ret) 6770 return ret; 6771 6772 ret = parse_dcb_table(dev, bios, nv_two_heads(dev)); 6773 if (ret) 6774 return ret; 6775 6776 fixup_legacy_i2c(bios); 6777 fixup_legacy_connector(bios); 6778 6779 if (!bios->major_version) /* we don't run version 0 bios */ 6780 return 0; 6781 6782 /* init script execution disabled */ 6783 bios->execute = false; 6784 6785 /* ... unless card isn't POSTed already */ 6786 if (!nouveau_bios_posted(dev)) { 6787 NV_INFO(dev, "Adaptor not initialised, " 6788 "running VBIOS init tables.\n"); 6789 bios->execute = true; 6790 } 6791 6792 ret = nouveau_run_vbios_init(dev); 6793 if (ret) 6794 return ret; 6795 6796 /* feature_byte on BMP is poor, but init always sets CR4B */ 6797 if (bios->major_version < 5) 6798 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; 6799 6800 /* all BIT systems need p_f_m_t for digital_min_front_porch */ 6801 if (bios->is_mobile || bios->major_version >= 5) 6802 ret = parse_fp_mode_table(dev, bios); 6803 6804 /* allow subsequent scripts to execute */ 6805 bios->execute = true; 6806 6807 return 0; 6808} 6809 6810void 6811nouveau_bios_takedown(struct drm_device *dev) 6812{ 6813 nouveau_bios_i2c_devices_takedown(dev); 6814} 6815