/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/ |
H A D | RegisterClassInfo.cpp | 79 unsigned NumRegs = RC->getNumRegs(); local 82 RCI.Order.reset(new unsigned[NumRegs]); 101 RCI.NumRegs = N + CSRAlias.size(); 102 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); 108 if (StressRA && RCI.NumRegs > StressRA) 109 RCI.NumRegs = StressRA; 113 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 118 for (unsigned I = 0; I != RCI.NumRegs; ++I)
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H A D | ExecutionDepsFix.cpp | 134 const unsigned NumRegs; member in class:__anon10140::ExeDepsFix 149 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} 251 assert(unsigned(rx) < NumRegs && "Invalid index"); 263 assert(unsigned(rx) < NumRegs && "Invalid index"); 274 assert(unsigned(rx) < NumRegs && "Invalid index"); 306 for (unsigned rx = 0; rx != NumRegs; ++rx) 330 for (unsigned rx = 0; rx != NumRegs; ++rx) 346 LiveRegs = new LiveReg[NumRegs]; 349 for (unsigned rx = 0; rx != NumRegs; ++rx) { 380 for (unsigned rx = 0; rx != NumRegs; [all...] |
H A D | VirtRegMap.cpp | 67 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); local 68 Virt2PhysMap.resize(NumRegs); 69 Virt2StackSlotMap.resize(NumRegs); 70 Virt2SplitMap.resize(NumRegs);
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H A D | LiveVariables.cpp | 426 for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) { 506 unsigned NumRegs = TRI->getNumRegs(); local 507 PhysRegDef = new MachineInstr*[NumRegs]; 508 PhysRegUse = new MachineInstr*[NumRegs]; 510 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0); 511 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0); 664 for (unsigned i = 0; i != NumRegs; ++i) 668 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0); 669 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInst [all...] |
H A D | MachineLICM.cpp | 496 unsigned NumRegs = TRI->getNumRegs(); local 497 BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop. 498 BitVector PhysRegClobbers(NumRegs); // Regs defined more than once. 533 BitVector TermRegs(NumRegs);
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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/ |
H A D | RegisterClassInfo.h | 30 unsigned NumRegs; member in struct:llvm::RegisterClassInfo::RCInfo 34 RCInfo() : Tag(0), NumRegs(0), ProperSubClass(false) {} 36 return makeArrayRef(Order.get(), NumRegs); 81 return get(RC).NumRegs;
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H A D | CallingConvLower.h | 232 /// NumRegs if they are all allocated. 233 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const { 234 for (unsigned i = 0; i != NumRegs; ++i) 237 return NumRegs; 260 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) { argument 261 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 262 if (FirstUnalloc == NumRegs) 273 unsigned NumRegs) { 274 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 275 if (FirstUnalloc == NumRegs) 272 AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs, unsigned NumRegs) argument [all...] |
H A D | FastISel.h | 341 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.h | 110 /// NumRegs if they are all allocated. 111 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { 112 for (unsigned i = 0; i != NumRegs; ++i) 115 return NumRegs; 138 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { argument 139 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 140 if (FirstUnalloc == NumRegs) 151 unsigned NumRegs) { 152 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 153 if (FirstUnalloc == NumRegs) 150 AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs, unsigned NumRegs) argument [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 149 unsigned NumRegs; // Number of entries in the array member in class:llvm::MCRegisterInfo 240 NumRegs = NR; 297 assert(RegNo < NumRegs && 333 return NumRegs; 380 assert(RegNo < NumRegs &&
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 107 uint8_t NumRegs; // D registers loaded or stored member in struct:__anon10323::NEONLdStTableEntry 381 unsigned NumRegs = TableEntry->NumRegs; local 392 if (NumRegs > 1 && TableEntry->copyAllListRegs) 394 if (NumRegs > 2 && TableEntry->copyAllListRegs) 396 if (NumRegs > 3 && TableEntry->copyAllListRegs) 446 unsigned NumRegs = TableEntry->NumRegs; local 467 if (NumRegs > 1 && TableEntry->copyAllListRegs) 469 if (NumRegs > 497 unsigned NumRegs = TableEntry->NumRegs; local [all...] |
H A D | Thumb1FrameLowering.cpp | 346 bool NumRegs = false; local 359 NumRegs = true; 363 if (NumRegs)
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H A D | ARMBaseRegisterInfo.cpp | 147 unsigned NumRegs = SubIndices.size(); local 148 if (NumRegs == 8) { 159 } else if (NumRegs == 4) { 196 } else if (NumRegs == 2) {
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H A D | ARMBaseInstrInfo.cpp | 2657 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); local 2658 return (NumRegs / 2) + (NumRegs % 2) + 1; 2693 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; local 2696 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st. 2731 if (NumRegs < 4) 2735 int A8UOps = (NumRegs / 2); 2736 if (NumRegs % 2) 2740 int A9UOps = (NumRegs / 2); 2743 if ((NumRegs [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 290 unsigned NumRegs = Regs.size(); local 291 if (NumRegs <= 1) 300 else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA) 302 else if (Offset == -4 * (int)NumRegs && isNotVFP) 313 if (NumRegs <= 2) 320 NewBase = Regs[NumRegs-1].first; 352 for (unsigned i = 0; i != NumRegs; ++i)
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H A D | ARMCodeEmitter.cpp | 1752 unsigned NumRegs = 1; 1757 ++NumRegs; 1762 Binary |= NumRegs * 2; 1764 Binary |= NumRegs;
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H A D | ARMISelDAGToDAG.cpp | 1532 unsigned NumRegs = NumVecs; local 1534 NumRegs *= 2; 1537 if (Alignment >= 32 && NumRegs == 4) 1539 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
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/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGBuilder.cpp | 232 unsigned NumRegs = local 235 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 236 NumParts = NumRegs; // Silence a compiler warning. 529 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, local 534 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 535 NumParts = NumRegs; // Silence a compiler warning. 612 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); local 614 for (unsigned i = 0; i != NumRegs; ++i) 617 Reg += NumRegs; 685 unsigned NumRegs local 766 unsigned NumRegs = Regs.size(); local 836 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); local 5849 unsigned NumRegs = 1; local 6562 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); local 6616 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT); local 6752 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); local [all...] |
H A D | FunctionLoweringInfo.cpp | 231 unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT); local 232 for (unsigned i = 0; i != NumRegs; ++i) {
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H A D | FastISel.cpp | 250 void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) { argument 262 for (unsigned i = 0; i < NumRegs; i++)
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H A D | LegalizeDAG.cpp | 330 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; local 344 for (unsigned i = 1; i < NumRegs; i++) { 453 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; local 464 for (unsigned i = 1; i < NumRegs; i++) {
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H A D | LegalizeIntegerTypes.cpp | 707 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT); local 708 // The argument is passed as NumRegs registers of type RegVT. 710 SmallVector<SDValue, 8> Parts(NumRegs); 711 for (unsigned i = 0; i < NumRegs; ++i) { 724 for (unsigned i = 1; i < NumRegs; ++i) {
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Transforms/Scalar/ |
H A D | LoopStrengthReduce.cpp | 771 unsigned NumRegs; member in class:__anon10592::Cost 780 : NumRegs(0), AddRecCost(0), NumIVMuls(0), NumBaseAdds(0), ImmCost(0), 790 return ((NumRegs | AddRecCost | NumIVMuls | NumBaseAdds 792 || ((NumRegs & AddRecCost & NumIVMuls & NumBaseAdds 799 return NumRegs == ~0u; 858 ++NumRegs; 941 NumRegs = ~0u; 951 if (NumRegs != Other.NumRegs) 952 return NumRegs < Othe [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 1373 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff; 1376 Binary |= NumRegs; 1378 Binary |= NumRegs * 2;
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
H A D | X86FastISel.cpp | 1909 unsigned NumRegs = TLI.getNumRegisters(I->getParent()->getContext(), VT); local 1910 for (unsigned j = 0; j != NumRegs; ++j) {
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