/linux-master/drivers/infiniband/hw/cxgb4/ |
H A D | t4fw_ri_api.h | 38 FW_RI_READ_REQ = 0x1, 162 #define FW_RI_TPTE_VALID_M 0x1 175 #define FW_RI_TPTE_STAGSTATE_M 0x1 200 #define FW_RI_TPTE_REMINVDIS_M 0x1 214 #define FW_RI_TPTE_MWBINDEN_M 0x1 233 #define FW_RI_TPTE_NOSNOOP_M 0x1 327 #define FW_RI_RES_WR_FETCHSZM_M 0x1 334 #define FW_RI_RES_WR_STATUSPGNS_M 0x1 341 #define FW_RI_RES_WR_STATUSPGRO_M 0x1 348 #define FW_RI_RES_WR_FETCHNS_M 0x1 [all...] |
/linux-master/drivers/iommu/intel/ |
H A D | iommu.h | 197 #define ecap_pms(e) (((e) >> 51) & 0x1) 198 #define ecap_rps(e) (((e) >> 49) & 0x1) 199 #define ecap_smpwc(e) (((e) >> 48) & 0x1) 200 #define ecap_flts(e) (((e) >> 47) & 0x1) 201 #define ecap_slts(e) (((e) >> 46) & 0x1) 202 #define ecap_slads(e) (((e) >> 45) & 0x1) 203 #define ecap_smts(e) (((e) >> 43) & 0x1) 204 #define ecap_dit(e) (((e) >> 41) & 0x1) 205 #define ecap_pds(e) (((e) >> 42) & 0x1) 206 #define ecap_pasid(e) (((e) >> 40) & 0x1) [all...] |
/linux-master/drivers/media/platform/samsung/s5p-mfc/ |
H A D | s5p_mfc_opr_v6.c | 893 reg |= (0x1 << 3); 897 reg |= (0x1 << 3); 901 reg &= ~(0x1 << 3); 911 reg &= ~(0x1 << 4); 913 reg |= (0x1 << 4); 918 reg &= ~(0x1 << 9); 925 reg &= ~(0x1 << 7); 932 reg &= ~(0x1 << 7); 935 writel(0x1, mfc_regs->pixel_format); 939 reg |= (0x1 << [all...] |
/linux-master/drivers/clk/ti/ |
H A D | dpll.c | 414 .idlest_mask = 0x1, 439 .idlest_mask = 0x1, 458 .idlest_mask = 0x1 << 1, 478 .idlest_mask = 0x1 << 1, 501 .idlest_mask = 0x1, 520 .idlest_mask = 0x1, 541 .idlest_mask = 0x1, 562 .idlest_mask = 0x1, 583 .idlest_mask = 0x1, 605 .idlest_mask = 0x1, [all...] |
/linux-master/arch/mips/include/asm/mach-au1x00/ |
H A D | au1xxx_dbdma.h | 116 #define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */ 118 #define DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */ 119 #define DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */ 120 #define DSCR_CMD0_SM (0x1 << 10) /* Stride mode */ 121 #define DSCR_CMD0_IE (0x1 << 8) /* Interrupt Enable */ 122 #define DSCR_CMD0_SP (0x1 << 4) /* Status pointer select */ 123 #define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
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/linux-master/drivers/tty/serial/ |
H A D | sunzilog.h | 63 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */ 81 #define RxENAB 0x1 /* Rx Enable */ 95 #define PAR_ENAB 0x1 /* Parity Enable */ 108 #define X1CLK 0x0 /* x1 clock mode */ 116 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */ 213 #define Rx_CH_AV 0x1 /* Rx Character Available */ 223 #define ALL_SNT 0x1 /* All sent */ 251 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
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H A D | ip22zilog.h | 71 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */ 89 #define RxENAB 0x1 /* Rx Enable */ 103 #define PAR_ENAB 0x1 /* Parity Enable */ 116 #define X1CLK 0x0 /* x1 clock mode */ 124 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */ 209 #define Rx_CH_AV 0x1 /* Rx Character Available */ 219 #define ALL_SNT 0x1 /* All sent */ 247 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
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H A D | pmac_zilog.h | 150 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */ 168 #define RxENABLE 0x1 /* Rx Enable */ 182 #define PAR_ENAB 0x1 /* Parity Enable */ 196 #define X1CLK 0x0 /* x1 clock mode */ 204 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */ 294 #define Rx_CH_AV 0x1 /* Rx Character Available */ 304 #define ALL_SNT 0x1 /* All sent */ 332 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
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/linux-master/drivers/gpu/drm/armada/ |
H A D | armada_hw.h | 163 CFG_DSCALE_HALF = 0x1 << 18, 167 CFG_ALPHAM_GRA = 0x1 << 16, 180 SRAM_GAMMA_UG = 0x1 << 8, 212 SCLK_510_EXTCLK0 = 0x1 << 30, 221 SCLK_16X_PCLK = 0x1 << 28, 231 DUMB16_RGB565_1 = 0x1 << 28, 263 CFG_IOPAD_DUMB18SPI = 0x1 << 0,
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/linux-master/drivers/gpu/drm/bridge/synopsys/ |
H A D | dw-hdmi.h | 578 HDMI_IH_PHY_STAT0_HPD = 0x1, 582 HDMI_IH_I2CM_STAT0_ERROR = 0x1, 586 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1, 611 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, 627 HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1, 628 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, 650 HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, 651 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, 672 HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1, 678 HDMI_VP_REMAP_YCC422_20bit = 0x1, [all...] |
/linux-master/drivers/net/ethernet/fungible/funcore/ |
H A D | fun_hci.h | 11 FUN_ADMIN_OP_BIND = 0x1, 24 FUN_REQ_COMMON_FLAG_RSP = 0x1, 122 FUN_ADMIN_BIND_TYPE_EPCQ = 0x1, 174 FUN_ADMIN_RES_CREATE_FLAG_ALLOCATOR = 0x1, 352 FUN_PORT_CAP_OFFLOADS = 0x1, 378 FUN_PORT_BRKMODE_NONE = 0x1, 385 FUN_PORT_SPEED_10M = 0x1, 398 FUN_PORT_HALF_DUPLEX = 0x1, 403 FUN_PORT_FEC_OFF = 0x1, 411 FUN_PORT_LINK_UP_WITH_ERR = 0x1, [all...] |
/linux-master/drivers/crypto/aspeed/ |
H A D | aspeed-hace.h | 54 #define HACE_CMD_CBC (0x1 << 4) 61 #define HACE_CMD_AES192 (0x1 << 2) 64 #define HACE_CMD_OP_INDEPENDENT (0x1) 79 #define HACE_CMD_CTR_IV_AES_96 (0x1 << 14) 80 #define HACE_CMD_CTR_IV_DES_32 (0x1 << 14) 96 #define HASH_CMD_SHA384 (0x1 << 10) 99 #define HASH_CMD_HMAC (0x1 << 7)
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/linux-master/arch/powerpc/platforms/85xx/ |
H A D | mpc85xx_mds.c | 167 #define BCSR_UCC1_GETH_EN (0x1 << 7) 168 #define BCSR_UCC2_GETH_EN (0x1 << 7) 184 #define BCSR7_UCC12_GETHnRST (0x1 << 2) 185 #define BCSR8_UEM_MARVELL_RST (0x1 << 1) 186 #define BCSR_UCC_RGMII (0x1 << 6) 187 #define BCSR_UCC_RTBI (0x1 << 5) 218 #define BCSR11_ENET_MICRST (0x1 << 5)
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/linux-master/drivers/net/ethernet/marvell/octeontx2/nic/ |
H A D | otx2_struct.h | 14 NIX_XQESZ_W16 = 0x1, 19 NIX_SQESZ_W8 = 0x1, 24 NIX_SEND_LDTYPE_LDT = 0x1, 46 NIX_XQE_TYPE_RX = 0x1, 56 NIX_SUBDC_EXT = 0x1, 69 NIX_SENDMEMALG_E_SETTSTMP = 0x1, 313 NIX_SND_STATUS_SQ_CTX_FAULT = 0x1,
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/linux-master/drivers/gpu/drm/imagination/ |
H A D | pvr_rogue_mips.h | 12 #define ROGUE_MIPSFW_PAGE_SIZE_4K (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K) 15 #define ROGUE_MIPSFW_PAGE_SIZE_64K (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_64K) 18 #define ROGUE_MIPSFW_PAGE_SIZE_256K (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_256K) 21 #define ROGUE_MIPSFW_PAGE_SIZE_1MB (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_1MB) 24 #define ROGUE_MIPSFW_PAGE_SIZE_4MB (0x1 << ROGUE_MIPSFW_LOG2_PAGE_SIZE_4MB) 178 #define ROGUE_MIPSFW_NMI_STATE_OFFSET (0x1) 179 #define ROGUE_MIPSFW_NMI_ERROR_STATE_SET (0x1)
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/linux-master/sound/soc/codecs/ |
H A D | rt722-sdca.h | 135 #define RT722_HIDDEN_REG_SW_RESET (0x1 << 14) 138 #define RT722_COMBOJACK_AUTO_DET_STATUS (0x1 << 11) 139 #define RT722_COMBOJACK_AUTO_DET_TRS (0x1 << 10) 140 #define RT722_COMBOJACK_AUTO_DET_CTIA (0x1 << 9) 141 #define RT722_COMBOJACK_AUTO_DET_OMTP (0x1 << 8) 144 #define RT722_DC_CALIB_CTRL (0x1 << 16) 146 #define RT722_PDM_DC_CALIB_STATUS (0x1 << 15)
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/linux-master/arch/x86/crypto/ |
H A D | camellia-aesni-avx2-asm_64.S | 62 #define roundsm32(x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2, t3, t4, t5, t6, \ 81 vpshufb t4, x1, x1; \ 96 filter_8bit(x1, t5, t6, t7, t4); \ 116 vextracti128 $1, x1, t3##_x; \ 126 vaesenclast t4##_x, x1##_x, x1##_x; \ 128 vinserti128 $1, t3##_x, x1, x1; \ 150 filter_8bit(x1, t [all...] |
H A D | aria-gfni-avx512-asm_64.S | 53 #define transpose_4x4(x0, x1, x2, x3, t1, t2) \ 54 vpunpckhdq x1, x0, t2; \ 55 vpunpckldq x1, x0, x0; \ 60 vpunpckhqdq t1, x0, x1; \ 171 #define inpack16_pre(x0, x1, x2, x3, \ 177 vmovdqu64 (1 * 64)(rio), x1; \ 194 #define inpack16_post(x0, x1, x2, x3, \ 199 byteslice_16x16b(x0, x1, x2, x3, \ 206 vmovdqu64 x1, 1 * 64(mem_ab); \ 222 #define write_output(x0, x1, x [all...] |
/linux-master/arch/arm64/crypto/ |
H A D | sm4-ce-ccm-core.S | 43 * x1: mac 49 ld1 {RMAC.16b}, [x1] 82 st1 {RMAC.16b}, [x1] 90 * x1: ctr0 (big endian, 128 bit) 96 ld1 {v0.16b}, [x1] 111 * x1: dst 152 st1 {v8.16b-v11.16b}, [x1], #64 172 st1 {v8.16b}, [x1], #16 194 strb w9, [x1], #1 /* store out byte */ 223 * x1 [all...] |
/linux-master/drivers/crypto/intel/qat/qat_common/ |
H A D | icp_qat_uclo.h | 35 #define ICP_QAT_SUOF_MINVER 0x1 41 #define ICP_QAT_MOF_MINVER 0x1 94 #define ICP_QAT_SHARED_USTORE_MODE(ae_mode) (((ae_mode) >> 0xb) & 0x1) 95 #define RELOADABLE_CTX_SHARED_MODE(ae_mode) (((ae_mode) >> 0xc) & 0x1) 97 #define ICP_QAT_LOC_MEM0_MODE(ae_mode) (((ae_mode) >> 0x8) & 0x1) 98 #define ICP_QAT_LOC_MEM1_MODE(ae_mode) (((ae_mode) >> 0x9) & 0x1) 99 #define ICP_QAT_LOC_MEM2_MODE(ae_mode) (((ae_mode) >> 0x6) & 0x1) 100 #define ICP_QAT_LOC_MEM3_MODE(ae_mode) (((ae_mode) >> 0x7) & 0x1) 101 #define ICP_QAT_LOC_TINDEX_MODE(ae_mode) (((ae_mode) >> 0xe) & 0x1)
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/athub/ |
H A D | athub_4_1_0_sh_mask.h | 72 #define XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1 85 #define XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1 98 #define XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1 111 #define XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1 124 #define XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1 137 #define XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1 150 #define XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1 163 #define XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1 176 #define XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1 189 #define XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1 [all...] |
/linux-master/drivers/gpu/drm/ |
H A D | drm_fbdev_generic.c | 146 size_t len = clip->x2 - clip->x1; 152 offset += clip->x1 / 8; 153 len = DIV_ROUND_UP(len + clip->x1 % 8, 8); 156 offset += clip->x1 / 4; 157 len = DIV_ROUND_UP(len + clip->x1 % 4, 4); 160 offset += clip->x1 / 2; 161 len = DIV_ROUND_UP(len + clip->x1 % 2, 2); 164 offset += clip->x1 * fb->format->cpp[0]; 221 if (!(clip->x1 < clip->x2 && clip->y1 < clip->y2))
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/linux-master/drivers/net/ethernet/sfc/siena/ |
H A D | mcdi_pcol.h | 380 #define MCDI_EVENT_LEVEL_WARN 0x1 405 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 440 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 451 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 475 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 486 #define MCDI_EVENT_AOE_NO_LOAD 0x1 539 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1 546 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1 567 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1 596 #define MCDI_EVENT_MUM_NO_LOAD 0x1 [all...] |
/linux-master/arch/powerpc/boot/dts/fsl/ |
H A D | mpc8568si-post.dtsi | 76 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 77 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 78 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 79 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
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H A D | mpc8569si-post.dtsi | 64 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 65 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 66 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 67 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
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