Searched refs:x1 (Results 401 - 425 of 5697) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h59 #define IH_RB_CNTL__RB_ENABLE_MASK 0x1
62 #define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
79 #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
87 #define IH_CNTL__ENABLE_INTR_MASK 0x1
90 #define IH_CNTL__MC_SWAP__SHIFT 0x1
105 #define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
115 #define IH_STATUS__IDLE_MASK 0x1
118 #define IH_STATUS__INPUT_IDLE__SHIFT 0x1
137 #define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
140 #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
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H A Doss_3_0_1_sh_mask.h59 #define IH_RB_CNTL__RB_ENABLE_MASK 0x1
62 #define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
79 #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
91 #define IH_CNTL__ENABLE_INTR_MASK 0x1
94 #define IH_CNTL__MC_SWAP__SHIFT 0x1
107 #define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
117 #define IH_STATUS__IDLE_MASK 0x1
120 #define IH_STATUS__INPUT_IDLE__SHIFT 0x1
139 #define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
142 #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
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H A Doss_3_0_sh_mask.h59 #define IH_RB_CNTL__RB_ENABLE_MASK 0x1
62 #define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
81 #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
103 #define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
113 #define IH_STATUS__IDLE_MASK 0x1
116 #define IH_STATUS__INPUT_IDLE__SHIFT 0x1
137 #define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
140 #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
153 #define IH_DEBUG__RB_FULL_DRAIN_ENABLE_MASK 0x1
156 #define IH_DEBUG__WPTR_OVERFLOW_ENABLE__SHIFT 0x1
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/linux-master/include/linux/mfd/
H A Dmax8997-private.h166 MAX8997_MUIC_REG_INT1 = 0x1,
189 #define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
190 #define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
199 #define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
200 #define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
201 #define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT)
202 #define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
206 #define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
232 #define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
233 #define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIF
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/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_top.c62 DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0);
65 DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
205 status->mdp = (value >> 0) & 0x1;
206 status->sspp[SSPP_VIG0] = (value >> 4) & 0x1;
207 status->sspp[SSPP_VIG1] = (value >> 6) & 0x1;
208 status->sspp[SSPP_VIG2] = (value >> 8) & 0x1;
209 status->sspp[SSPP_VIG3] = (value >> 10) & 0x1;
210 status->sspp[SSPP_RGB0] = (value >> 12) & 0x1;
211 status->sspp[SSPP_RGB1] = (value >> 14) & 0x1;
212 status->sspp[SSPP_RGB2] = (value >> 16) & 0x1;
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/linux-master/drivers/net/wireless/realtek/rtw89/
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
41 RTW89_DECL_RFK_WM(0x32b8, BIT(30), 0x1),
42 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
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/linux-master/drivers/crypto/
H A Datmel-aes-regs.h19 #define AES_MR_SMOD_AUTO (0x1 << 8)
23 #define AES_MR_KEYSIZE_192 (0x1 << 10)
27 #define AES_MR_OPMOD_CBC (0x1 << 12)
33 #define AES_MR_LOD (0x1 << 15)
36 #define AES_MR_CFBS_64b (0x1 << 16)
54 #define AES_ISR_URAT_ODR_RD_PROC (0x1 << 12)
/linux-master/drivers/media/usb/cx231xx/
H A Dcx231xx-pcb-cfg.h24 VRT_SET_I2C1 = 0x1,
47 ENABLE_ONE_BYTE = 0x1,
53 #define SPEED_MASK 0x1
56 HIGH_SPEED = 0x1 /* 1: high speed */
120 #define MOD_DIGITAL 0x1
129 #define SOURCE_DIGITAL 0x1
/linux-master/sound/soc/fsl/
H A Dimx-pcm-rpmsg.h257 * | 0x1 | S24_LE |
266 * | 0x1 | Right Channel |
284 #define TX_START 0x1
313 #define RX_PERIOD_DONE 0x1
320 #define MSG_TYPE_B 0x1
324 #define RESP_NOT_ALLOWED 0x1
329 #define RPMSG_S24_LE 0x1
336 #define RPMSG_CH_RIGHT 0x1
/linux-master/arch/arm64/mm/
H A Dtrans_pgd-asm.S24 msr vbar_el2, x1
31 mov x4, x1
32 mov x1, x3
/linux-master/sound/soc/codecs/
H A Dtas5720.h50 #define TAS5720_SAIF_RIGHTJ_20BIT (0x1)
68 #define TAS5720_PWM_RATE_8_4_FSYNC (0x1 << 4)
77 #define TAS5720_ANALOG_GAIN_20_7DBV (0x1 << 2)
89 #define TAS5720_OC_THRESH_75PCT (0x1 << 4)
105 #define TAS5722_HPF_7_4HZ (0x1 << 5)
114 #define TAS5722_AUTO_SLEEP_1024LR (0x1 << 3)
H A Dssm2602.c244 {18432000, 48000, SSM2602_COEFF_SRATE(0x0, 0x1, 0x0)},
245 {12000000, 48000, SSM2602_COEFF_SRATE(0x0, 0x0, 0x1)},
249 {18432000, 32000, SSM2602_COEFF_SRATE(0x6, 0x1, 0x0)},
250 {12000000, 32000, SSM2602_COEFF_SRATE(0x6, 0x0, 0x1)},
254 {18432000, 16000, SSM2602_COEFF_SRATE(0x5, 0x1, 0x0)},
255 {12000000, 16000, SSM2602_COEFF_SRATE(0xa, 0x0, 0x1)},
259 {18432000, 8000, SSM2602_COEFF_SRATE(0x3, 0x1, 0x0)},
261 {16934400, 8000, SSM2602_COEFF_SRATE(0xb, 0x1, 0x0)},
262 {12000000, 8000, SSM2602_COEFF_SRATE(0x3, 0x0, 0x1)},
266 {18432000, 96000, SSM2602_COEFF_SRATE(0x7, 0x1,
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_sh_mask.h35 #define THM_TCON_HTC__HTC_EN_MASK 0x1
38 #define THM_TCON_HTC__RSVD0__SHIFT 0x1
85 #define THM_TCON_THERM_TRIP__RSVD0_MASK 0x1
88 #define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1
101 #define THM_GPIO_PROCHOT_CTRL__TX12_EN_MASK 0x1
104 #define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1
121 #define THM_GPIO_THERMTRIP_CTRL__TX12_EN_MASK 0x1
124 #define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1
141 #define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
144 #define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
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/linux-master/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h26 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
27 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
30 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
31 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
876 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
877 #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
878 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
879 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<
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/linux-master/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Darc_farm_kdma_masks.h25 #define ARC_FARM_KDMA_CFG_0_EN_MASK 0x1
29 #define ARC_FARM_KDMA_CFG_1_HALT_MASK 0x1
35 #define ARC_FARM_KDMA_PROT_VAL_MASK 0x1
41 #define ARC_FARM_KDMA_CKG_HBW_RBUF_MASK 0x1
49 #define ARC_FARM_KDMA_RD_GLBL_LBW_VIA_HBW_MASK 0x1
165 #define ARC_FARM_KDMA_ERR_CFG_ERR_MSG_EN_MASK 0x1
171 #define ARC_FARM_KDMA_ERR_CAUSE_HBW_RD_ERR_MASK 0x1
209 #define ARC_FARM_KDMA_STS1_IS_HALT_MASK 0x1
297 #define ARC_FARM_KDMA_PWRLP_CFG_GLBL_EN_MASK 0x1
321 #define ARC_FARM_KDMA_DBG_STS_RD_CTX_FULL_MASK 0x1
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H A Ddcore0_edma0_core_masks.h25 #define DCORE0_EDMA0_CORE_CFG_0_EN_MASK 0x1
29 #define DCORE0_EDMA0_CORE_CFG_1_HALT_MASK 0x1
35 #define DCORE0_EDMA0_CORE_PROT_VAL_MASK 0x1
41 #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_MASK 0x1
49 #define DCORE0_EDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK 0x1
165 #define DCORE0_EDMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1
171 #define DCORE0_EDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1
209 #define DCORE0_EDMA0_CORE_STS1_IS_HALT_MASK 0x1
297 #define DCORE0_EDMA0_CORE_PWRLP_CFG_GLBL_EN_MASK 0x1
321 #define DCORE0_EDMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1
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H A Dpdma0_core_masks.h25 #define PDMA0_CORE_CFG_0_EN_MASK 0x1
29 #define PDMA0_CORE_CFG_1_HALT_MASK 0x1
35 #define PDMA0_CORE_PROT_VAL_MASK 0x1
41 #define PDMA0_CORE_CKG_HBW_RBUF_MASK 0x1
49 #define PDMA0_CORE_RD_GLBL_LBW_VIA_HBW_MASK 0x1
165 #define PDMA0_CORE_ERR_CFG_ERR_MSG_EN_MASK 0x1
171 #define PDMA0_CORE_ERR_CAUSE_HBW_RD_ERR_MASK 0x1
209 #define PDMA0_CORE_STS1_IS_HALT_MASK 0x1
297 #define PDMA0_CORE_PWRLP_CFG_GLBL_EN_MASK 0x1
321 #define PDMA0_CORE_DBG_STS_RD_CTX_FULL_MASK 0x1
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/linux-master/drivers/regulator/
H A Ds5m8767.c18 #define S5M8767_OPMODE_NORMAL_MODE 0x1
121 {0x0, 0x3, 0x2, 0x1}, /* LDO1 */
122 {0x0, 0x3, 0x2, 0x1},
123 {0x0, 0x3, 0x2, 0x1},
125 {0x0, 0x3, 0x2, 0x1}, /* LDO5 */
126 {0x0, 0x3, 0x2, 0x1},
127 {0x0, 0x3, 0x2, 0x1},
128 {0x0, 0x3, 0x2, 0x1},
129 {0x0, 0x3, 0x2, 0x1},
130 {0x0, 0x3, 0x2, 0x1}, /* LDO1
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/linux-master/include/linux/qed/
H A Dqed_rdma_if.h87 #define QED_RDMA_DEV_CAP_RNR_NAK_MASK 0x1
90 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK 0x1
93 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK 0x1
96 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK 0x1
99 #define QED_RDMA_DEV_CAP_SYS_IMAGE_MASK 0x1
102 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK 0x1
105 #define QED_RDMA_DEV_CAP_ATOMIC_OP_MASK 0x1
107 #define QED_RDMA_DEV_CAP_RESIZE_CQ_MASK 0x1
112 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK 0x1
115 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK 0x1
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/linux-master/drivers/s390/char/
H A Dsclp_sdias.h14 #define SDIAS_EQ_SIZE 0x1
17 #define SDIAS_ASA_SIZE_64 0x1
/linux-master/drivers/gpu/host1x/hw/
H A Dhw_host1x01_channel.h50 return (r >> 10) & 0x1;
92 return (r >> 0) & 0x1;
H A Dhw_host1x02_channel.h50 return (r >> 11) & 0x1;
92 return (r >> 0) & 0x1;
/linux-master/arch/arm/lib/
H A Dclear_user.S42 tst r1, #1 @ x1 x0 x1 x0 x1 x0 x1
/linux-master/include/dt-bindings/net/
H A Dti-dp83867.h21 #define DP83867_RGMIIDCTL_500_PS 0x1
39 #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1
/linux-master/scripts/dtc/include-prefixes/dt-bindings/net/
H A Dti-dp83867.h21 #define DP83867_RGMIIDCTL_500_PS 0x1
39 #define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1

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