59 #define IH_RB_CNTL__RB_ENABLE_MASK 0x1
62 #define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
81 #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
103 #define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
113 #define IH_STATUS__IDLE_MASK 0x1
116 #define IH_STATUS__INPUT_IDLE__SHIFT 0x1
137 #define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
140 #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
153 #define IH_DEBUG__RB_FULL_DRAIN_ENABLE_MASK 0x1
156 #define IH_DEBUG__WPTR_OVERFLOW_ENABLE__SHIFT 0x1
165 #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1
168 #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1
195 #define IH_VF_ENABLE__VALUE_MASK 0x1
207 #define IH_LEVEL_INTR_MASK__MASK_MASK 0x1
209 #define IH_RESET_INCOMPLETE_INT_CNTL__CG_MASK 0x1
212 #define IH_RESET_INCOMPLETE_INT_CNTL__DC__SHIFT 0x1
255 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__CG_MASK 0x1
258 #define IH_CLIENT_MAY_SEND_INCOMPLETE_INT__DC__SHIFT 0x1
319 #define SEM_VF_ENABLE__VALUE_MASK 0x1
333 #define SEM_STATUS__SEM_IDLE_MASK 0x1
336 #define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
366 #define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
399 #define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1
402 #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
427 #define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1
430 #define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1
470 #define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1
509 #define SRBM_STATUS3__MCC0_BUSY_MASK 0x1
512 #define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1
541 #define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1
544 #define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1
613 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_BIF_MASK 0x1
616 #define SRBM_CREDIT_RECOVER__CREDIT_RECOVER_SMU__SHIFT 0x1
677 #define SRBM_CREDIT_RESET__CREDIT_RESET_BIF_MASK 0x1
680 #define SRBM_CREDIT_RESET__CREDIT_RESET_SMU__SHIFT 0x1
785 #define SRBM_DEBUG__IGNORE_RDY_MASK 0x1
788 #define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1
807 #define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1
810 #define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT 0x1
871 #define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1
901 #define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1
904 #define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1
911 #define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1
914 #define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1
915 #define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1
918 #define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1
919 #define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1
922 #define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1
923 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1
926 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1
1165 #define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1
1167 #define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1
1181 #define DH_TEST__DH_TEST_MASK 0x1
1451 #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1
1454 #define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT 0x1
1477 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
1480 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
1513 #define SDMA0_STATUS_REG__IDLE_MASK 0x1
1516 #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
1571 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
1574 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
1599 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
1602 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
1615 #define SDMA0_F32_CNTL__HALT_MASK 0x1
1618 #define SDMA0_F32_CNTL__STEP__SHIFT 0x1
1639 #define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1
1642 #define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1
1678 #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
1699 #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x1
1707 #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x1
1729 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK 0x1
1732 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x1
1737 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x1
1740 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1
1801 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x1
1804 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1
1817 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x1
1820 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
1877 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK 0x1
1880 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT 0x1
1901 #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
1904 #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
1925 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1928 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1943 #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
1963 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
1989 #define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
1992 #define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1
2003 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1
2017 #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
2033 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1
2036 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
2041 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
2044 #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
2065 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
2068 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
2083 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
2103 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
2125 #define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
2128 #define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1
2139 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
2153 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
2169 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1
2172 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
2177 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
2180 #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
2201 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
2204 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
2219 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
2239 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
2261 #define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
2264 #define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1
2275 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
2289 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
2305 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1
2308 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
2347 #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1
2350 #define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT 0x1
2373 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
2376 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
2409 #define SDMA1_STATUS_REG__IDLE_MASK 0x1
2412 #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
2467 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
2470 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
2495 #define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
2498 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
2511 #define SDMA1_F32_CNTL__HALT_MASK 0x1
2514 #define SDMA1_F32_CNTL__STEP__SHIFT 0x1
2536 #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
2557 #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x1
2565 #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x1
2587 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK 0x1
2590 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x1
2595 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x1
2598 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1
2663 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x1
2666 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1
2679 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x1
2682 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1
2733 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK 0x1
2736 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT 0x1
2757 #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
2760 #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
2781 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
2784 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
2799 #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
2819 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
2845 #define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
2848 #define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1
2859 #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1
2873 #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
2889 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1
2892 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
2897 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
2900 #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
2921 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
2924 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
2939 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
2959 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
2981 #define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
2984 #define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1
2995 #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
3009 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
3025 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1
3028 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
3033 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
3036 #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
3057 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
3060 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
3075 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
3095 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
3117 #define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
3120 #define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1
3131 #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
3145 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
3161 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1
3164 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
3195 #define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1
3198 #define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1
3229 #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1
3232 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
3233 #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1
3236 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
3244 #define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1
3281 #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1
3284 #define HDP_MISC_CNTL__VM_ID__SHIFT 0x1
3307 #define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1
3310 #define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1
3323 #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1
3326 #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
3345 #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1
3348 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
3357 #define HDP_VF_ENABLE__VF_EN_MASK 0x1
3459 #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1
3462 #define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1
3465 #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1
3468 #define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1
3471 #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1
3474 #define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1
3477 #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1
3480 #define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1
3483 #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1
3486 #define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1
3489 #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1
3492 #define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1
3495 #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1
3498 #define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1
3501 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1
3504 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1
3509 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1
3512 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1
3531 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1
3534 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
3535 #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1
3538 #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1

Indexes created Thu Jun 20 12:38:36 MDT 2024