59 #define IH_RB_CNTL__RB_ENABLE_MASK 0x1
62 #define IH_RB_CNTL__RB_SIZE__SHIFT 0x1
79 #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x1
91 #define IH_CNTL__ENABLE_INTR_MASK 0x1
94 #define IH_CNTL__MC_SWAP__SHIFT 0x1
107 #define IH_LEVEL_STATUS__DC_STATUS_MASK 0x1
117 #define IH_STATUS__IDLE_MASK 0x1
120 #define IH_STATUS__INPUT_IDLE__SHIFT 0x1
139 #define IH_PERFMON_CNTL__ENABLE0_MASK 0x1
142 #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1
161 #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x1
181 #define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
184 #define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
197 #define SEM_VF_ENABLE__VALUE_MASK 0x1
207 #define SEM_STATUS__SEM_IDLE_MASK 0x1
210 #define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1
242 #define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1
275 #define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x1
278 #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1
313 #define SRBM_STATUS2__SDMA_RQ_PENDING_MASK 0x1
316 #define SRBM_STATUS2__TST_RQ_PENDING__SHIFT 0x1
354 #define SRBM_STATUS__UVD_RQ_PENDING__SHIFT 0x1
393 #define SRBM_STATUS3__MCC0_BUSY_MASK 0x1
396 #define SRBM_STATUS3__MCC1_BUSY__SHIFT 0x1
425 #define SRBM_SOFT_RESET__SOFT_RESET_ATCL2_MASK 0x1
428 #define SRBM_SOFT_RESET__SOFT_RESET_BIF__SHIFT 0x1
535 #define SRBM_DEBUG__IGNORE_RDY_MASK 0x1
538 #define SRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x1
557 #define SRBM_DEBUG_SNAPSHOT__MCB_RDY_MASK 0x1
560 #define SRBM_DEBUG_SNAPSHOT__GIONB_RDY__SHIFT 0x1
621 #define SRBM_DEBUG_SNAPSHOT2__VCE1_RDY_MASK 0x1
651 #define SRBM_READ_ERROR2__READ_REQUESTER_ACP_MASK 0x1
654 #define SRBM_READ_ERROR2__READ_REQUESTER_ISP__SHIFT 0x1
661 #define SRBM_INT_CNTL__RDERR_INT_MASK_MASK 0x1
664 #define SRBM_INT_CNTL__RAERR_INT_MASK__SHIFT 0x1
665 #define SRBM_INT_STATUS__RDERR_INT_STAT_MASK 0x1
668 #define SRBM_INT_STATUS__RAERR_INT_STAT__SHIFT 0x1
669 #define SRBM_INT_ACK__RDERR_INT_ACK_MASK 0x1
672 #define SRBM_INT_ACK__RAERR_INT_ACK__SHIFT 0x1
673 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_BIF_MASK 0x1
676 #define SRBM_FIREWALL_ERROR_SRC__ACCESS_REQUESTER_ACP__SHIFT 0x1
903 #define SRBM_VF_ENABLE__VF_ENABLE_MASK 0x1
905 #define SRBM_VIRT_CNTL__VF_WRITE_ENABLE_MASK 0x1
945 #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x1
948 #define SDMA0_CNTL__ATC_L1_ENABLE__SHIFT 0x1
971 #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
974 #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
1007 #define SDMA0_STATUS_REG__IDLE_MASK 0x1
1010 #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1
1065 #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
1068 #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
1093 #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
1096 #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
1109 #define SDMA0_F32_CNTL__HALT_MASK 0x1
1112 #define SDMA0_F32_CNTL__STEP__SHIFT 0x1
1133 #define SDMA_POWER_GATING__PG_CNTL_ENABLE_MASK 0x1
1136 #define SDMA_POWER_GATING__AUTOMATIC_STATUS_ENABLE__SHIFT 0x1
1172 #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1
1199 #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x1
1207 #define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x1
1217 #define SDMA0_ATCL1_CNTL__REDO_ENABLE_MASK 0x1
1220 #define SDMA0_ATCL1_CNTL__REDO_DELAY__SHIFT 0x1
1237 #define SDMA0_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1
1240 #define SDMA0_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
1287 #define SDMA0_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1
1290 #define SDMA0_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
1337 #define SDMA0_ATCL1_INV0__INV_MIDDLE_MASK 0x1
1340 #define SDMA0_ATCL1_INV0__RD_TIMEOUT__SHIFT 0x1
1395 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFMON_CNTL_MASK 0x1
1398 #define SDMA0_PERF_REG_TYPE0__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x1
1403 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x1
1406 #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1
1467 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x1
1470 #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1
1489 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x1
1492 #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
1549 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CNTL_MASK 0x1
1552 #define SDMA0_PUB_REG_TYPE1__SDMA0_VM_CTX_LO__SHIFT 0x1
1579 #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
1582 #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
1603 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1606 #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1621 #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
1641 #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
1667 #define SDMA0_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
1670 #define SDMA0_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1
1681 #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1
1695 #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
1717 #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1
1720 #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
1725 #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
1728 #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
1749 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1752 #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1767 #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
1787 #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
1809 #define SDMA0_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
1812 #define SDMA0_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1
1823 #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
1837 #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
1859 #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1
1862 #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
1867 #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
1870 #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
1891 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
1894 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
1909 #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
1929 #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
1951 #define SDMA0_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
1954 #define SDMA0_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1
1965 #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
1979 #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
2001 #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1
2004 #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
2043 #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x1
2046 #define SDMA1_CNTL__ATC_L1_ENABLE__SHIFT 0x1
2069 #define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x1
2072 #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1
2105 #define SDMA1_STATUS_REG__IDLE_MASK 0x1
2108 #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1
2163 #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x1
2166 #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
2191 #define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x1
2194 #define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1
2207 #define SDMA1_F32_CNTL__HALT_MASK 0x1
2210 #define SDMA1_F32_CNTL__STEP__SHIFT 0x1
2232 #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1
2259 #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x1
2267 #define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x1
2277 #define SDMA1_ATCL1_CNTL__REDO_ENABLE_MASK 0x1
2280 #define SDMA1_ATCL1_CNTL__REDO_DELAY__SHIFT 0x1
2297 #define SDMA1_ATCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1
2300 #define SDMA1_ATCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
2347 #define SDMA1_ATCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x1
2350 #define SDMA1_ATCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1
2397 #define SDMA1_ATCL1_INV0__INV_MIDDLE_MASK 0x1
2400 #define SDMA1_ATCL1_INV0__RD_TIMEOUT__SHIFT 0x1
2455 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFMON_CNTL_MASK 0x1
2458 #define SDMA1_PERF_REG_TYPE0__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x1
2463 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x1
2466 #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1
2531 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x1
2534 #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1
2553 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x1
2556 #define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1
2607 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CNTL_MASK 0x1
2610 #define SDMA1_PUB_REG_TYPE1__SDMA1_VM_CTX_LO__SHIFT 0x1
2637 #define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x1
2640 #define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1
2661 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
2664 #define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
2679 #define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x1
2699 #define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x1
2725 #define SDMA1_GFX_VIRTUAL_ADDR__ATC_MASK 0x1
2728 #define SDMA1_GFX_VIRTUAL_ADDR__INVAL__SHIFT 0x1
2739 #define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x1
2753 #define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x1
2775 #define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x1
2778 #define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
2783 #define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x1
2786 #define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1
2807 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
2810 #define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
2825 #define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x1
2845 #define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x1
2867 #define SDMA1_RLC0_VIRTUAL_ADDR__ATC_MASK 0x1
2870 #define SDMA1_RLC0_VIRTUAL_ADDR__INVAL__SHIFT 0x1
2881 #define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x1
2895 #define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x1
2917 #define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x1
2920 #define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
2925 #define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x1
2928 #define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1
2949 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x1
2952 #define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1
2967 #define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x1
2987 #define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x1
3009 #define SDMA1_RLC1_VIRTUAL_ADDR__ATC_MASK 0x1
3012 #define SDMA1_RLC1_VIRTUAL_ADDR__INVAL__SHIFT 0x1
3023 #define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x1
3037 #define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x1
3059 #define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x1
3062 #define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1
3093 #define HDP_NONSURFACE_INFO__NONSURF_ADDR_TYPE_MASK 0x1
3096 #define HDP_NONSURFACE_INFO__NONSURF_ARRAY_MODE__SHIFT 0x1
3127 #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x1
3130 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1
3131 #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x1
3134 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1
3142 #define HDP_TILING_CONFIG__PIPE_TILING__SHIFT 0x1
3179 #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x1
3182 #define HDP_MISC_CNTL__VM_ID__SHIFT 0x1
3205 #define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x1
3208 #define HDP_MEM_POWER_LS__LS_SETUP__SHIFT 0x1
3221 #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x1
3224 #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1
3243 #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x1
3246 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1
3255 #define HDP_VF_ENABLE__VF_EN_MASK 0x1
3357 #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x1
3360 #define HDP_XDP_P2P_MBX_ADDR0__ADDR__SHIFT 0x1
3363 #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x1
3366 #define HDP_XDP_P2P_MBX_ADDR1__ADDR__SHIFT 0x1
3369 #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x1
3372 #define HDP_XDP_P2P_MBX_ADDR2__ADDR__SHIFT 0x1
3375 #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x1
3378 #define HDP_XDP_P2P_MBX_ADDR3__ADDR__SHIFT 0x1
3381 #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x1
3384 #define HDP_XDP_P2P_MBX_ADDR4__ADDR__SHIFT 0x1
3387 #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x1
3390 #define HDP_XDP_P2P_MBX_ADDR5__ADDR__SHIFT 0x1
3393 #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x1
3396 #define HDP_XDP_P2P_MBX_ADDR6__ADDR__SHIFT 0x1
3399 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_PRIV_MASK 0x1
3402 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x1
3407 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_PRIV_MASK 0x1
3410 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_WRREQ_SWAP__SHIFT 0x1
3429 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x1
3432 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1
3433 #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_EN_MASK 0x1
3436 #define HDP_XDP_SID_CFG__SID_CFG_WR_COMBINE_TIMER__SHIFT 0x1

Indexes created Sun Jun 23 19:15:37 MDT 2024