Searched refs:writel_relaxed (Results 251 - 275 of 698) sorted by relevance

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/linux-master/drivers/memory/tegra/
H A Dtegra20-emc.c251 writel_relaxed(status, emc->regs + EMC_INTSTATUS);
290 writel_relaxed(timing->data[i],
308 writel_relaxed(EMC_TIMING_UPDATE,
548 writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS);
554 writel_relaxed(val, emc->regs + EMC_MRR);
620 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
623 writel_relaxed(intmask, emc->regs + EMC_INTMASK);
624 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
632 writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
1133 writel_relaxed(EMC_PWR_GATHER_DISABL
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/linux-master/drivers/mtd/nand/raw/
H A Dcadence-nand-controller.c599 writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0);
615 writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0);
650 writel_relaxed(reg, cdns_ctrl->reg + SKIP_BYTES_CONF);
679 writel_relaxed(reg, cdns_ctrl->reg + SKIP_BYTES_CONF);
680 writel_relaxed(skip_bytes_offset, cdns_ctrl->reg + SKIP_BYTES_OFFSET);
699 writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0);
700 writel_relaxed(bitflips_threshold, cdns_ctrl->reg + ECC_CONFIG_1);
719 writel_relaxed(reg, cdns_ctrl->reg + COMMON_SET);
728 writel_relaxed(irq_status->status, cdns_ctrl->reg + INTR_STATUS);
729 writel_relaxed(irq_statu
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H A Darasan-nand-controller.c247 writel_relaxed(event, nfc->base + INTR_STS_REG);
274 writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG);
275 writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG);
276 writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG);
277 writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG);
278 writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG);
345 writel_relaxed(anand->data_iface, nfc->base + DATA_INTERFACE_REG);
346 writel_relaxed(anand->timings, nfc->base + TIMING_REG);
429 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG);
430 writel_relaxed(upper_32_bit
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/linux-master/drivers/iommu/
H A Dmtk_iommu.c383 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0, base + data->plat_data->inv_sel_reg);
384 writel_relaxed(F_ALL_INVLD, base + REG_MMU_INVALIDATE);
428 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
431 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova), base + REG_MMU_INVLD_START_A);
432 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1),
434 writel_relaxed(F_MMU_INV_RANGE, base + REG_MMU_INVALIDATE);
441 writel_relaxed(0, base + REG_MMU_CPE_DONE);
519 writel_relaxed(regval, base + REG_MMU_INT_CONTROL0);
1052 writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);
1061 writel_relaxed(regva
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/linux-master/drivers/clk/ti/
H A Dfapll.c97 writel_relaxed(v, fd->base);
108 writel_relaxed(v, fd->base);
137 writel_relaxed(v, fd->base);
149 writel_relaxed(v, fd->base);
257 writel_relaxed(v, fd->base);
281 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
292 writel_relaxed(v, synth->fd->base + FAPLL_PWD_OFFSET);
397 writel_relaxed(v, synth->freq);
470 writel_relaxed(v, synth->div);
/linux-master/drivers/thermal/tegra/
H A Dtegra30-tsensor.c128 writel_relaxed(val, ts->regs + 0x40 + TSENSOR_SENSOR0_CONFIG0);
129 writel_relaxed(val, ts->regs + 0x80 + TSENSOR_SENSOR0_CONFIG0);
237 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);
255 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_STATUS0);
301 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
355 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
372 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);
378 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG2);
402 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
/linux-master/drivers/fsi/
H A Dfsi-master-aspeed.c106 * write does not matter, so use writel_relaxed.
108 writel_relaxed(CMD_WRITE, base + OPB0_RW);
109 writel_relaxed(transfer_size, base + OPB0_XFER_SIZE);
110 writel_relaxed(addr, base + OPB0_FSI_ADDR);
111 writel_relaxed(val, base + OPB0_FSI_DATA_W);
112 writel_relaxed(0x1, base + OPB_IRQ_CLEAR);
158 * write does not matter, so use writel_relaxed.
160 writel_relaxed(CMD_READ, base + OPB0_RW);
161 writel_relaxed(transfer_size, base + OPB0_XFER_SIZE);
162 writel_relaxed(add
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/linux-master/drivers/gpio/
H A Dgpio-rtd.c255 writel_relaxed(val, data->base + reg_offset);
294 writel_relaxed(val, data->base + dato_reg_offset);
345 writel_relaxed(val, data->base + reg_offset);
403 writel_relaxed(status, data->irq_base + reg_offset);
444 writel_relaxed(clr_mask, data->irq_base + gpa_reg_offset);
445 writel_relaxed(clr_mask, data->irq_base + gpda_reg_offset);
449 writel_relaxed(val, data->base + ie_reg_offset);
466 writel_relaxed(val, data->base + ie_reg_offset);
507 writel_relaxed(val, data->base + dp_reg_offset);
/linux-master/drivers/i2c/busses/
H A Di2c-qcom-geni.c174 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
177 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
182 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
271 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
302 writel_relaxed(val, base + SE_GENI_TX_FIFOn);
305 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
312 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
315 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
317 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
355 writel_relaxed(
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H A Di2c-stm32f7.c435 writel_relaxed(readl_relaxed(reg) | mask, reg);
440 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
762 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
825 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
848 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
966 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
967 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1133 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1134 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1219 writel_relaxed(cr
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/linux-master/drivers/bus/
H A Dhisi_lpc.c123 writel_relaxed(opcnt, lpcdev->membase + LPC_REG_OP_LEN);
124 writel_relaxed(cmd_word, lpcdev->membase + LPC_REG_CMD);
125 writel_relaxed(addr, lpcdev->membase + LPC_REG_ADDR);
176 writel_relaxed(opcnt, lpcdev->membase + LPC_REG_OP_LEN);
177 writel_relaxed(cmd_word, lpcdev->membase + LPC_REG_CMD);
178 writel_relaxed(addr, lpcdev->membase + LPC_REG_ADDR);
/linux-master/drivers/memory/
H A Dbrcmstb_dpfe.c16 * Throughout the driver, we use readl_relaxed() and writel_relaxed(), which
341 writel_relaxed(val, priv->regs + REG_DCPU_RESET);
354 writel_relaxed(0, regs + REG_TO_DCPU_MBOX);
355 writel_relaxed(0, regs + REG_TO_HOST_MBOX);
360 writel_relaxed(val, regs + REG_DCPU_RESET);
365 writel_relaxed(val, regs + REG_DCPU_RESET);
430 writel_relaxed(0, priv->regs + release_mbox);
468 writel_relaxed(chksum, regs + DCPU_MSG_RAM(i));
470 writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i));
474 writel_relaxed(
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/linux-master/drivers/memory/samsung/
H A Dexynos-srom.c92 writel_relaxed(bw, srom->reg_base + EXYNOS_SROM_BW);
94 writel_relaxed(pmc | (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |
/linux-master/arch/arm/mach-exynos/
H A Dpm.c129 writel_relaxed(__pa_symbol(exynos_cpu_resume),
131 writel_relaxed(flags, exynos_boot_vector_flag());
/linux-master/drivers/watchdog/
H A Drtd119x_wdt.c63 writel_relaxed(RTD119X_TCWTR_WDCLR, data->base + RTD119X_TCWTR);
125 writel_relaxed(RTD119X_TCWTR_WDCLR, data->base + RTD119X_TCWTR);
/linux-master/drivers/cpufreq/
H A Dkirkwood-cpufreq.c61 writel_relaxed(reg, priv.base);
78 writel_relaxed(reg, priv.base);
/linux-master/drivers/clocksource/
H A Dbcm2835_timer.c48 writel_relaxed(readl_relaxed(system_clock) + event,
58 writel_relaxed(timer->match_mask, timer->control);
H A Dtimer-imx-sysctr.c85 writel_relaxed(cmp_hi, base + CMPCV_HI);
86 writel_relaxed(cmp_lo, base + CMPCV_LO);
/linux-master/drivers/regulator/
H A Dstm32-pwr.c73 writel_relaxed(val, priv->base + REG_PWR_CR3);
92 writel_relaxed(val, priv->base + REG_PWR_CR3);
/linux-master/drivers/spi/
H A Dspi-sprd-adi.c242 writel_relaxed(reg, sadi->base + REG_ADI_RD_CMD);
315 writel_relaxed(val, (void __iomem *)(sadi->slave_vbase + reg));
467 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
468 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
473 writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
492 writel_relaxed(chn_config, sadi->base +
498 writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
502 writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
/linux-master/drivers/gpu/drm/msm/
H A Dmsm_mdss.c176 writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC);
192 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
203 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
206 writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
207 writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
210 writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2);
212 writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
213 writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
/linux-master/drivers/hsi/controllers/
H A Domap_ssi_core.c159 writel_relaxed(SSI_WAKE(0),
162 writel_relaxed(SSI_WAKE(0),
183 writel_relaxed(val, omap_ssi->sys + SSI_GDD_MPU_IRQ_ENABLE_REG);
213 writel_relaxed(val, omap_ssi->sys + SSI_MPU_ENABLE_REG(port->num, 0));
241 writel_relaxed(status_reg, sys + SSI_GDD_MPU_IRQ_STATUS_REG);
435 writel_relaxed(SSI_SWRESET, omap_ssi->gdd + SSI_GDD_GRST_REG);
440 writel_relaxed(SSI_CLK_AUTOGATING_ON, omap_ssi->sys + SSI_GDD_GCR_REG);
592 writel_relaxed(omap_ssi->gdd_gcr, omap_ssi->gdd + SSI_GDD_GCR_REG);
/linux-master/drivers/remoteproc/
H A Dmtk_scp_ipi.c97 writel_relaxed(val, ptr);
106 writel_relaxed(val, dst + len - remain);
/linux-master/drivers/clk/berlin/
H A Dberlin2-avpll.c135 writel_relaxed(reg, vco->base + VCO_CTRL0);
150 writel_relaxed(reg, vco->base + VCO_CTRL0);
233 writel_relaxed(reg, ch->base + VCO_CTRL10);
245 writel_relaxed(reg, ch->base + VCO_CTRL10);
/linux-master/arch/arm/mm/
H A Dpmsa-v7.c105 writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RNR);
115 writel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + PMSAv7_RASR);
123 writel_relaxed(v | racr, BASEADDR_V7M_SCB + PMSAv7_RASR);
129 writel_relaxed(v, BASEADDR_V7M_SCB + PMSAv7_RBAR);

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