1/*
2 * Copyright (C) 2017 Spreadtrum Communications Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <linux/delay.h>
8#include <linux/hwspinlock.h>
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/reboot.h>
16#include <linux/spi/spi.h>
17#include <linux/sizes.h>
18
19/* Registers definitions for ADI controller */
20#define REG_ADI_CTRL0			0x4
21#define REG_ADI_CHN_PRIL		0x8
22#define REG_ADI_CHN_PRIH		0xc
23#define REG_ADI_INT_EN			0x10
24#define REG_ADI_INT_RAW			0x14
25#define REG_ADI_INT_MASK		0x18
26#define REG_ADI_INT_CLR			0x1c
27#define REG_ADI_GSSI_CFG0		0x20
28#define REG_ADI_GSSI_CFG1		0x24
29#define REG_ADI_RD_CMD			0x28
30#define REG_ADI_RD_DATA			0x2c
31#define REG_ADI_ARM_FIFO_STS		0x30
32#define REG_ADI_STS			0x34
33#define REG_ADI_EVT_FIFO_STS		0x38
34#define REG_ADI_ARM_CMD_STS		0x3c
35#define REG_ADI_CHN_EN			0x40
36#define REG_ADI_CHN_ADDR(id)		(0x44 + (id - 2) * 4)
37#define REG_ADI_CHN_EN1			0x20c
38
39/* Bits definitions for register REG_ADI_GSSI_CFG0 */
40#define BIT_CLK_ALL_ON			BIT(30)
41
42/* Bits definitions for register REG_ADI_RD_DATA */
43#define BIT_RD_CMD_BUSY			BIT(31)
44#define RD_ADDR_SHIFT			16
45#define RD_VALUE_MASK			GENMASK(15, 0)
46#define RD_ADDR_MASK			GENMASK(30, 16)
47
48/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
49#define BIT_FIFO_FULL			BIT(11)
50#define BIT_FIFO_EMPTY			BIT(10)
51
52/*
53 * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
54 * ADI supports 12/14bit address for r2p0, and additional 17bit for r3p0 or
55 * later versions. Since bit[1:0] are zero, so the spec describe them as
56 * 10/12/15bit address mode.
57 * The 10bit mode supports sigle slave, 12/15bit mode supports 3 slave, the
58 * high two bits is slave_id.
59 * The slave devices address offset is 0x8000 for 10/12bit address mode,
60 * and 0x20000 for 15bit mode.
61 */
62#define ADI_10BIT_SLAVE_ADDR_SIZE	SZ_4K
63#define ADI_10BIT_SLAVE_OFFSET		0x8000
64#define ADI_12BIT_SLAVE_ADDR_SIZE	SZ_16K
65#define ADI_12BIT_SLAVE_OFFSET		0x8000
66#define ADI_15BIT_SLAVE_ADDR_SIZE	SZ_128K
67#define ADI_15BIT_SLAVE_OFFSET		0x20000
68
69/* Timeout (ms) for the trylock of hardware spinlocks */
70#define ADI_HWSPINLOCK_TIMEOUT		5000
71/*
72 * ADI controller has 50 channels including 2 software channels
73 * and 48 hardware channels.
74 */
75#define ADI_HW_CHNS			50
76
77#define ADI_FIFO_DRAIN_TIMEOUT		1000
78#define ADI_READ_TIMEOUT		2000
79
80/*
81 * Read back address from REG_ADI_RD_DATA bit[30:16] which maps to:
82 * REG_ADI_RD_CMD bit[14:0] for r2p0
83 * REG_ADI_RD_CMD bit[16:2] for r3p0
84 */
85#define RDBACK_ADDR_MASK_R2		GENMASK(14, 0)
86#define RDBACK_ADDR_MASK_R3		GENMASK(16, 2)
87#define RDBACK_ADDR_SHIFT_R3		2
88
89/* Registers definitions for PMIC watchdog controller */
90#define REG_WDG_LOAD_LOW		0x0
91#define REG_WDG_LOAD_HIGH		0x4
92#define REG_WDG_CTRL			0x8
93#define REG_WDG_LOCK			0x20
94
95/* Bits definitions for register REG_WDG_CTRL */
96#define BIT_WDG_RUN			BIT(1)
97#define BIT_WDG_NEW			BIT(2)
98#define BIT_WDG_RST			BIT(3)
99
100/* Bits definitions for register REG_MODULE_EN */
101#define BIT_WDG_EN			BIT(2)
102
103/* Registers definitions for PMIC */
104#define PMIC_RST_STATUS			0xee8
105#define PMIC_MODULE_EN			0xc08
106#define PMIC_CLK_EN			0xc18
107#define PMIC_WDG_BASE			0x80
108
109/* Definition of PMIC reset status register */
110#define HWRST_STATUS_SECURITY		0x02
111#define HWRST_STATUS_RECOVERY		0x20
112#define HWRST_STATUS_NORMAL		0x40
113#define HWRST_STATUS_ALARM		0x50
114#define HWRST_STATUS_SLEEP		0x60
115#define HWRST_STATUS_FASTBOOT		0x30
116#define HWRST_STATUS_SPECIAL		0x70
117#define HWRST_STATUS_PANIC		0x80
118#define HWRST_STATUS_CFTREBOOT		0x90
119#define HWRST_STATUS_AUTODLOADER	0xa0
120#define HWRST_STATUS_IQMODE		0xb0
121#define HWRST_STATUS_SPRDISK		0xc0
122#define HWRST_STATUS_FACTORYTEST	0xe0
123#define HWRST_STATUS_WATCHDOG		0xf0
124
125/* Use default timeout 50 ms that converts to watchdog values */
126#define WDG_LOAD_VAL			((50 * 32768) / 1000)
127#define WDG_LOAD_MASK			GENMASK(15, 0)
128#define WDG_UNLOCK_KEY			0xe551
129
130struct sprd_adi_wdg {
131	u32 base;
132	u32 rst_sts;
133	u32 wdg_en;
134	u32 wdg_clk;
135};
136
137struct sprd_adi_data {
138	u32 slave_offset;
139	u32 slave_addr_size;
140	int (*read_check)(u32 val, u32 reg);
141	int (*restart)(struct sys_off_data *data);
142	void (*wdg_rst)(void *p);
143};
144
145struct sprd_adi {
146	struct spi_controller	*ctlr;
147	struct device		*dev;
148	void __iomem		*base;
149	struct hwspinlock	*hwlock;
150	unsigned long		slave_vbase;
151	unsigned long		slave_pbase;
152	const struct sprd_adi_data *data;
153};
154
155static int sprd_adi_check_addr(struct sprd_adi *sadi, u32 reg)
156{
157	if (reg >= sadi->data->slave_addr_size) {
158		dev_err(sadi->dev,
159			"slave address offset is incorrect, reg = 0x%x\n",
160			reg);
161		return -EINVAL;
162	}
163
164	return 0;
165}
166
167static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
168{
169	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
170	u32 sts;
171
172	do {
173		sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
174		if (sts & BIT_FIFO_EMPTY)
175			break;
176
177		cpu_relax();
178	} while (--timeout);
179
180	if (timeout == 0) {
181		dev_err(sadi->dev, "drain write fifo timeout\n");
182		return -EBUSY;
183	}
184
185	return 0;
186}
187
188static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
189{
190	return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
191}
192
193static int sprd_adi_read_check(u32 val, u32 addr)
194{
195	u32 rd_addr;
196
197	rd_addr = (val & RD_ADDR_MASK) >> RD_ADDR_SHIFT;
198
199	if (rd_addr != addr) {
200		pr_err("ADI read error, addr = 0x%x, val = 0x%x\n", addr, val);
201		return -EIO;
202	}
203
204	return 0;
205}
206
207static int sprd_adi_read_check_r2(u32 val, u32 reg)
208{
209	return sprd_adi_read_check(val, reg & RDBACK_ADDR_MASK_R2);
210}
211
212static int sprd_adi_read_check_r3(u32 val, u32 reg)
213{
214	return sprd_adi_read_check(val, (reg & RDBACK_ADDR_MASK_R3) >> RDBACK_ADDR_SHIFT_R3);
215}
216
217static int sprd_adi_read(struct sprd_adi *sadi, u32 reg, u32 *read_val)
218{
219	int read_timeout = ADI_READ_TIMEOUT;
220	unsigned long flags;
221	u32 val;
222	int ret = 0;
223
224	if (sadi->hwlock) {
225		ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
226						  ADI_HWSPINLOCK_TIMEOUT,
227						  &flags);
228		if (ret) {
229			dev_err(sadi->dev, "get the hw lock failed\n");
230			return ret;
231		}
232	}
233
234	ret = sprd_adi_check_addr(sadi, reg);
235	if (ret)
236		goto out;
237
238	/*
239	 * Set the slave address offset need to read into RD_CMD register,
240	 * then ADI controller will start to transfer automatically.
241	 */
242	writel_relaxed(reg, sadi->base + REG_ADI_RD_CMD);
243
244	/*
245	 * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
246	 * simultaneously when writing read command to register, and the
247	 * BIT_RD_CMD_BUSY will be cleared after the read operation is
248	 * completed.
249	 */
250	do {
251		val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
252		if (!(val & BIT_RD_CMD_BUSY))
253			break;
254
255		cpu_relax();
256	} while (--read_timeout);
257
258	if (read_timeout == 0) {
259		dev_err(sadi->dev, "ADI read timeout\n");
260		ret = -EBUSY;
261		goto out;
262	}
263
264	/*
265	 * The return value before adi r5p0 includes data and read register
266	 * address, from bit 0to bit 15 are data, and from bit 16 to bit 30
267	 * are read register address. Then we can check the returned register
268	 * address to validate data.
269	 */
270	if (sadi->data->read_check) {
271		ret = sadi->data->read_check(val, reg);
272		if (ret < 0)
273			goto out;
274	}
275
276	*read_val = val & RD_VALUE_MASK;
277
278out:
279	if (sadi->hwlock)
280		hwspin_unlock_irqrestore(sadi->hwlock, &flags);
281	return ret;
282}
283
284static int sprd_adi_write(struct sprd_adi *sadi, u32 reg, u32 val)
285{
286	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
287	unsigned long flags;
288	int ret;
289
290	if (sadi->hwlock) {
291		ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
292						  ADI_HWSPINLOCK_TIMEOUT,
293						  &flags);
294		if (ret) {
295			dev_err(sadi->dev, "get the hw lock failed\n");
296			return ret;
297		}
298	}
299
300	ret = sprd_adi_check_addr(sadi, reg);
301	if (ret)
302		goto out;
303
304	ret = sprd_adi_drain_fifo(sadi);
305	if (ret < 0)
306		goto out;
307
308	/*
309	 * we should wait for write fifo is empty before writing data to PMIC
310	 * registers.
311	 */
312	do {
313		if (!sprd_adi_fifo_is_full(sadi)) {
314			/* we need virtual register address to write. */
315			writel_relaxed(val, (void __iomem *)(sadi->slave_vbase + reg));
316			break;
317		}
318
319		cpu_relax();
320	} while (--timeout);
321
322	if (timeout == 0) {
323		dev_err(sadi->dev, "write fifo is full\n");
324		ret = -EBUSY;
325	}
326
327out:
328	if (sadi->hwlock)
329		hwspin_unlock_irqrestore(sadi->hwlock, &flags);
330	return ret;
331}
332
333static int sprd_adi_transfer_one(struct spi_controller *ctlr,
334				 struct spi_device *spi_dev,
335				 struct spi_transfer *t)
336{
337	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
338	u32 reg, val;
339	int ret;
340
341	if (t->rx_buf) {
342		reg = *(u32 *)t->rx_buf;
343		ret = sprd_adi_read(sadi, reg, &val);
344		*(u32 *)t->rx_buf = val;
345	} else if (t->tx_buf) {
346		u32 *p = (u32 *)t->tx_buf;
347		reg = *p++;
348		val = *p;
349		ret = sprd_adi_write(sadi, reg, val);
350	} else {
351		dev_err(sadi->dev, "no buffer for transfer\n");
352		ret = -EINVAL;
353	}
354
355	return ret;
356}
357
358static void sprd_adi_set_wdt_rst_mode(void *p)
359{
360#if IS_ENABLED(CONFIG_SPRD_WATCHDOG)
361	u32 val;
362	struct sprd_adi *sadi = (struct sprd_adi *)p;
363
364	/* Init watchdog reset mode */
365	sprd_adi_read(sadi, PMIC_RST_STATUS, &val);
366	val |= HWRST_STATUS_WATCHDOG;
367	sprd_adi_write(sadi, PMIC_RST_STATUS, val);
368#endif
369}
370
371static int sprd_adi_restart(struct sprd_adi *sadi, unsigned long mode,
372			    const char *cmd, struct sprd_adi_wdg *wdg)
373{
374	u32 val, reboot_mode = 0;
375
376	if (!cmd)
377		reboot_mode = HWRST_STATUS_NORMAL;
378	else if (!strncmp(cmd, "recovery", 8))
379		reboot_mode = HWRST_STATUS_RECOVERY;
380	else if (!strncmp(cmd, "alarm", 5))
381		reboot_mode = HWRST_STATUS_ALARM;
382	else if (!strncmp(cmd, "fastsleep", 9))
383		reboot_mode = HWRST_STATUS_SLEEP;
384	else if (!strncmp(cmd, "bootloader", 10))
385		reboot_mode = HWRST_STATUS_FASTBOOT;
386	else if (!strncmp(cmd, "panic", 5))
387		reboot_mode = HWRST_STATUS_PANIC;
388	else if (!strncmp(cmd, "special", 7))
389		reboot_mode = HWRST_STATUS_SPECIAL;
390	else if (!strncmp(cmd, "cftreboot", 9))
391		reboot_mode = HWRST_STATUS_CFTREBOOT;
392	else if (!strncmp(cmd, "autodloader", 11))
393		reboot_mode = HWRST_STATUS_AUTODLOADER;
394	else if (!strncmp(cmd, "iqmode", 6))
395		reboot_mode = HWRST_STATUS_IQMODE;
396	else if (!strncmp(cmd, "sprdisk", 7))
397		reboot_mode = HWRST_STATUS_SPRDISK;
398	else if (!strncmp(cmd, "tospanic", 8))
399		reboot_mode = HWRST_STATUS_SECURITY;
400	else if (!strncmp(cmd, "factorytest", 11))
401		reboot_mode = HWRST_STATUS_FACTORYTEST;
402	else
403		reboot_mode = HWRST_STATUS_NORMAL;
404
405	/* Record the reboot mode */
406	sprd_adi_read(sadi, wdg->rst_sts, &val);
407	val &= ~HWRST_STATUS_WATCHDOG;
408	val |= reboot_mode;
409	sprd_adi_write(sadi, wdg->rst_sts, val);
410
411	/* Enable the interface clock of the watchdog */
412	sprd_adi_read(sadi, wdg->wdg_en, &val);
413	val |= BIT_WDG_EN;
414	sprd_adi_write(sadi, wdg->wdg_en, val);
415
416	/* Enable the work clock of the watchdog */
417	sprd_adi_read(sadi, wdg->wdg_clk, &val);
418	val |= BIT_WDG_EN;
419	sprd_adi_write(sadi, wdg->wdg_clk, val);
420
421	/* Unlock the watchdog */
422	sprd_adi_write(sadi, wdg->base + REG_WDG_LOCK, WDG_UNLOCK_KEY);
423
424	sprd_adi_read(sadi, wdg->base + REG_WDG_CTRL, &val);
425	val |= BIT_WDG_NEW;
426	sprd_adi_write(sadi, wdg->base + REG_WDG_CTRL, val);
427
428	/* Load the watchdog timeout value, 50ms is always enough. */
429	sprd_adi_write(sadi, wdg->base + REG_WDG_LOAD_HIGH, 0);
430	sprd_adi_write(sadi, wdg->base + REG_WDG_LOAD_LOW,
431		       WDG_LOAD_VAL & WDG_LOAD_MASK);
432
433	/* Start the watchdog to reset system */
434	sprd_adi_read(sadi, wdg->base + REG_WDG_CTRL, &val);
435	val |= BIT_WDG_RUN | BIT_WDG_RST;
436	sprd_adi_write(sadi, wdg->base + REG_WDG_CTRL, val);
437
438	/* Lock the watchdog */
439	sprd_adi_write(sadi, wdg->base + REG_WDG_LOCK, ~WDG_UNLOCK_KEY);
440
441	mdelay(1000);
442
443	dev_emerg(sadi->dev, "Unable to restart system\n");
444	return NOTIFY_DONE;
445}
446
447static int sprd_adi_restart_sc9860(struct sys_off_data *data)
448{
449	struct sprd_adi_wdg wdg = {
450		.base = PMIC_WDG_BASE,
451		.rst_sts = PMIC_RST_STATUS,
452		.wdg_en = PMIC_MODULE_EN,
453		.wdg_clk = PMIC_CLK_EN,
454	};
455
456	return sprd_adi_restart(data->cb_data, data->mode, data->cmd, &wdg);
457}
458
459static void sprd_adi_hw_init(struct sprd_adi *sadi)
460{
461	struct device_node *np = sadi->dev->of_node;
462	int i, size, chn_cnt;
463	const __be32 *list;
464	u32 tmp;
465
466	/* Set all channels as default priority */
467	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
468	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
469
470	/* Set clock auto gate mode */
471	tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
472	tmp &= ~BIT_CLK_ALL_ON;
473	writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
474
475	/* Set hardware channels setting */
476	list = of_get_property(np, "sprd,hw-channels", &size);
477	if (!list || !size) {
478		dev_info(sadi->dev, "no hw channels setting in node\n");
479		return;
480	}
481
482	chn_cnt = size / 8;
483	for (i = 0; i < chn_cnt; i++) {
484		u32 value;
485		u32 chn_id = be32_to_cpu(*list++);
486		u32 chn_config = be32_to_cpu(*list++);
487
488		/* Channel 0 and 1 are software channels */
489		if (chn_id < 2)
490			continue;
491
492		writel_relaxed(chn_config, sadi->base +
493			       REG_ADI_CHN_ADDR(chn_id));
494
495		if (chn_id < 32) {
496			value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
497			value |= BIT(chn_id);
498			writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
499		} else if (chn_id < ADI_HW_CHNS) {
500			value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
501			value |= BIT(chn_id - 32);
502			writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
503		}
504	}
505}
506
507static int sprd_adi_probe(struct platform_device *pdev)
508{
509	struct device_node *np = pdev->dev.of_node;
510	const struct sprd_adi_data *data;
511	struct spi_controller *ctlr;
512	struct sprd_adi *sadi;
513	struct resource *res;
514	u16 num_chipselect;
515	int ret;
516
517	if (!np) {
518		dev_err(&pdev->dev, "can not find the adi bus node\n");
519		return -ENODEV;
520	}
521
522	data = of_device_get_match_data(&pdev->dev);
523	if (!data) {
524		dev_err(&pdev->dev, "no matching driver data found\n");
525		return -EINVAL;
526	}
527
528	pdev->id = of_alias_get_id(np, "spi");
529	num_chipselect = of_get_child_count(np);
530
531	ctlr = spi_alloc_host(&pdev->dev, sizeof(struct sprd_adi));
532	if (!ctlr)
533		return -ENOMEM;
534
535	dev_set_drvdata(&pdev->dev, ctlr);
536	sadi = spi_controller_get_devdata(ctlr);
537
538	sadi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
539	if (IS_ERR(sadi->base)) {
540		ret = PTR_ERR(sadi->base);
541		goto put_ctlr;
542	}
543
544	sadi->slave_vbase = (unsigned long)sadi->base +
545			    data->slave_offset;
546	sadi->slave_pbase = res->start + data->slave_offset;
547	sadi->ctlr = ctlr;
548	sadi->dev = &pdev->dev;
549	sadi->data = data;
550	ret = of_hwspin_lock_get_id(np, 0);
551	if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
552		sadi->hwlock =
553			devm_hwspin_lock_request_specific(&pdev->dev, ret);
554		if (!sadi->hwlock) {
555			ret = -ENXIO;
556			goto put_ctlr;
557		}
558	} else {
559		switch (ret) {
560		case -ENOENT:
561			dev_info(&pdev->dev, "no hardware spinlock supplied\n");
562			break;
563		default:
564			dev_err_probe(&pdev->dev, ret, "failed to find hwlock id\n");
565			goto put_ctlr;
566		}
567	}
568
569	sprd_adi_hw_init(sadi);
570
571	if (sadi->data->wdg_rst)
572		sadi->data->wdg_rst(sadi);
573
574	ctlr->dev.of_node = pdev->dev.of_node;
575	ctlr->bus_num = pdev->id;
576	ctlr->num_chipselect = num_chipselect;
577	ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
578	ctlr->bits_per_word_mask = 0;
579	ctlr->transfer_one = sprd_adi_transfer_one;
580
581	ret = devm_spi_register_controller(&pdev->dev, ctlr);
582	if (ret) {
583		dev_err(&pdev->dev, "failed to register SPI controller\n");
584		goto put_ctlr;
585	}
586
587	if (sadi->data->restart) {
588		ret = devm_register_restart_handler(&pdev->dev,
589						    sadi->data->restart,
590						    sadi);
591		if (ret) {
592			dev_err(&pdev->dev, "can not register restart handler\n");
593			goto put_ctlr;
594		}
595	}
596
597	return 0;
598
599put_ctlr:
600	spi_controller_put(ctlr);
601	return ret;
602}
603
604static struct sprd_adi_data sc9860_data = {
605	.slave_offset = ADI_10BIT_SLAVE_OFFSET,
606	.slave_addr_size = ADI_10BIT_SLAVE_ADDR_SIZE,
607	.read_check = sprd_adi_read_check_r2,
608	.restart = sprd_adi_restart_sc9860,
609	.wdg_rst = sprd_adi_set_wdt_rst_mode,
610};
611
612static struct sprd_adi_data sc9863_data = {
613	.slave_offset = ADI_12BIT_SLAVE_OFFSET,
614	.slave_addr_size = ADI_12BIT_SLAVE_ADDR_SIZE,
615	.read_check = sprd_adi_read_check_r3,
616};
617
618static struct sprd_adi_data ums512_data = {
619	.slave_offset = ADI_15BIT_SLAVE_OFFSET,
620	.slave_addr_size = ADI_15BIT_SLAVE_ADDR_SIZE,
621	.read_check = sprd_adi_read_check_r3,
622};
623
624static const struct of_device_id sprd_adi_of_match[] = {
625	{
626		.compatible = "sprd,sc9860-adi",
627		.data = &sc9860_data,
628	},
629	{
630		.compatible = "sprd,sc9863-adi",
631		.data = &sc9863_data,
632	},
633	{
634		.compatible = "sprd,ums512-adi",
635		.data = &ums512_data,
636	},
637	{ },
638};
639MODULE_DEVICE_TABLE(of, sprd_adi_of_match);
640
641static struct platform_driver sprd_adi_driver = {
642	.driver = {
643		.name = "sprd-adi",
644		.of_match_table = sprd_adi_of_match,
645	},
646	.probe = sprd_adi_probe,
647};
648module_platform_driver(sprd_adi_driver);
649
650MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
651MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
652MODULE_LICENSE("GPL v2");
653