Searched refs:pll (Results 101 - 125 of 339) sorted by relevance

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/linux-master/drivers/media/pci/bt8xx/
H A Dbttv-cards.c86 static unsigned int pll[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET }; variable
107 module_param_array(pll, int, NULL, 0444);
118 MODULE_PARM_DESC(pll, "specify installed crystal (0=none, 28=28 MHz, 35=35 MHz, 14=14 MHz)");
391 .pll = PLL_28,
455 .pll = PLL_28,
467 .pll = PLL_28,
480 .pll = PLL_28,
518 .pll = PLL_28,
533 .pll = PLL_28,
561 .pll
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/linux-master/drivers/gpu/drm/omapdrm/dss/
H A Ddpi.c37 struct dss_pll *pll; member in struct:dpi_data
203 return dss_pll_hsdiv_calc_a(ctx->dpi->pll, clkdco,
228 clkin = clk_get_rate(dpi->pll->clkin);
230 if (dpi->pll->hw->type == DSS_PLL_TYPE_A) {
239 return dss_pll_calc_a(ctx->dpi->pll, clkin,
243 dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo);
298 r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo);
333 if (dpi->pll)
361 if (dpi->pll) {
381 static int dpi_verify_pll(struct dss_pll *pll) argument
398 struct dss_pll *pll; local
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H A Ddss.h144 int (*enable)(struct dss_pll *pll);
145 void (*disable)(struct dss_pll *pll);
146 int (*set_config)(struct dss_pll *pll,
173 /* DRA7 errata i932: retry pll lock on failure */
317 void dss_video_pll_uninit(struct dss_pll *pll);
319 void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable);
519 int dss_pll_register(struct dss_device *dss, struct dss_pll *pll);
520 void dss_pll_unregister(struct dss_pll *pll);
525 int dss_pll_enable(struct dss_pll *pll);
526 void dss_pll_disable(struct dss_pll *pll);
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/linux-master/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_7nm.c110 static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) argument
119 pll_freq = pll->vco_current_rate;
127 if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
129 else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
156 static void dsi_pll_calc_ssc(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) argument
190 static void dsi_pll_ssc_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) argument
192 void __iomem *base = pll->phy->pll_base;
214 static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll) argument
216 void __iomem *base = pll->phy->pll_base;
219 if (!(pll
278 dsi_pll_commit(struct dsi_pll_7nm *pll, struct dsi_pll_config *config) argument
328 dsi_pll_7nm_lock_status(struct dsi_pll_7nm *pll) argument
348 dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll) argument
357 dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll) argument
366 dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) argument
374 dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) argument
385 dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) argument
442 dsi_pll_disable_sub(struct dsi_pll_7nm *pll) argument
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H A Ddsi_phy_10nm.c114 static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll, struct dsi_pll_config *config) argument
123 pll_freq = pll->vco_current_rate;
149 static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll, struct dsi_pll_config *config) argument
183 static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *config) argument
185 void __iomem *base = pll->phy->pll_base;
207 static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll) argument
209 void __iomem *base = pll->phy->pll_base;
236 static void dsi_pll_commit(struct dsi_pll_10nm *pll, struct dsi_pll_config *config) argument
238 void __iomem *base = pll->phy->pll_base;
285 static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll) argument
306 dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll) argument
316 dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll) argument
326 dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll) argument
335 dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll) argument
393 dsi_pll_disable_sub(struct dsi_pll_10nm *pll) argument
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/linux-master/drivers/video/fbdev/matrox/
H A Dmatroxfb_misc.c129 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax, argument
133 unsigned int fxtal = pll->ref_freq;
142 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max);
143 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq);
145 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min);
146 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min);
147 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max);
148 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min);
149 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max);
152 for (p = 1; p <= pll
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/linux-master/drivers/clk/at91/
H A DMakefile7 obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o
10 obj-$(CONFIG_HAVE_AT91_AUDIO_PLL) += clk-audio-pll.o
17 obj-$(CONFIG_HAVE_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
/linux-master/drivers/phy/mediatek/
H A Dphy-mtk-hdmi.c30 ret = clk_prepare_enable(hdmi_phy->pll);
43 clk_disable_unprepare(hdmi_phy->pll);
118 hdmi_phy->pll = devm_clk_register(dev, &hdmi_phy->pll_hw);
119 if (IS_ERR(hdmi_phy->pll))
120 return dev_err_probe(dev, PTR_ERR(hdmi_phy->pll),
154 hdmi_phy->pll);
/linux-master/drivers/clk/
H A Dclk-qoriq.c52 int pll; /* CGx_PLLn */ member in struct:clockgen_sourceinfo
68 * cmux freq must be >= platform pll.
69 * If not set, cmux freq must be >= platform pll/2
92 struct clockgen_pll pll[6]; member in struct:clockgen
476 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
478 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
488 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
490 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
493 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
495 cg->fman[1] = cg->pll[PLATFORM_PL
898 int pll, div; local
1215 struct clockgen_pll *pll = &cg->pll[idx]; local
1313 struct clockgen_pll *pll; local
1391 struct clockgen_pll *pll; local
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H A Dclk-cdce706.c24 #define CDCE706_PLL_M_LOW(pll) (1 + 3 * (pll))
25 #define CDCE706_PLL_N_LOW(pll) (2 + 3 * (pll))
26 #define CDCE706_PLL_HI(pll) (3 + 3 * (pll))
37 #define CDCE706_PLL_MUX_MASK(pll) (0x80 >> (pll))
45 #define CDCE706_PLL_FVCO_MASK(pll) (0x80 >> (pll))
83 struct cdce706_hw_data pll[3]; member in struct:cdce706_dev_data
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/linux-master/sound/soc/fsl/
H A Dfsl_utils.c125 struct clk *p, *pll = NULL, *npll = NULL; local
138 pll = pp;
145 reparent = (pll && !clk_is_match(pll, npll));
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_display_reg_defs.h22 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b)
29 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgm20b.c160 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) argument
166 gk20a_pllg_read_mnp(&clk->base, &pll->base);
168 pll->sdm_din = (val >> GPCPLL_CFG2_SDM_DIN_SHIFT) &
173 gm20b_pllg_write_mnp(struct gm20b_clk *clk, const struct gm20b_pll *pll) argument
178 pll->sdm_din << GPCPLL_CFG2_SDM_DIN_SHIFT);
179 gk20a_pllg_write_mnp(&clk->base, &pll->base);
270 struct gm20b_pll pll; local
278 gm20b_pllg_read_mnp(clk, &pll);
280 if (n_int == pll.base.n && sdm_din == pll
360 gm20b_pllg_program_mnp(struct gm20b_clk *clk, const struct gk20a_pll *pll) argument
433 gm20b_pllg_program_mnp_slide(struct gm20b_clk *clk, const struct gk20a_pll *pll) argument
488 gm20b_dvfs_calc_safe_pll(struct gm20b_clk *clk, struct gk20a_pll *pll) argument
727 struct gk20a_pll pll; local
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H A Dgt215.c27 #include "pll.h"
31 #include <subdev/bios/pll.h>
108 read_pll(struct gt215_clk *clk, int idx, u32 pll) argument
111 u32 ctrl = nvkm_rd32(device, pll + 0);
117 u32 coef = nvkm_rd32(device, pll + 4);
125 if ((pll & 0x00ff00) == 0x00e800)
235 gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz, argument
244 info->pll = 0;
250 if (!pll || (diff >= -2000 && diff < 3000)) {
255 ret = nvbios_pll_parse(subdev->device->bios, pll,
274 calc_clk(struct gt215_clk *clk, struct nvkm_cstate *cstate, int idx, u32 pll, int dom) argument
363 prog_pll(struct gt215_clk *clk, int idx, u32 pll, int dom) argument
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/linux-master/sound/soc/codecs/
H A Dadav80x.c46 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00
47 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll))
48 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll))
56 #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll))
59 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4))
61 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIEL
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H A Dak4671.c472 u8 pll; local
474 pll = snd_soc_component_read(component, AK4671_PLL_MODE_SELECT0);
475 pll &= ~AK4671_PLL;
479 pll |= AK4671_PLL_11_2896MHZ;
482 pll |= AK4671_PLL_12MHZ;
485 pll |= AK4671_PLL_12_288MHZ;
488 pll |= AK4671_PLL_13MHZ;
491 pll |= AK4671_PLL_13_5MHZ;
494 pll |= AK4671_PLL_19_2MHZ;
497 pll |
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/linux-master/drivers/clk/qcom/
H A Dclk-pll.h76 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
78 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
/linux-master/drivers/video/fbdev/omap2/omapfb/dss/
H A DMakefile6 output.o dss-of.o pll.o video-pll.o
H A Ddss.h123 int (*enable)(struct dss_pll *pll);
124 void (*disable)(struct dss_pll *pll);
125 int (*set_config)(struct dss_pll *pll,
264 void dss_video_pll_uninit(struct dss_pll *pll);
462 int dss_pll_register(struct dss_pll *pll);
463 void dss_pll_unregister(struct dss_pll *pll);
465 int dss_pll_enable(struct dss_pll *pll);
466 void dss_pll_disable(struct dss_pll *pll);
467 int dss_pll_set_config(struct dss_pll *pll,
470 bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigne
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/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dgv100.c25 #include <subdev/bios/pll.h>
26 #include <subdev/clk/pll.h>
/linux-master/drivers/gpu/drm/omapdrm/
H A DMakefile23 dss/dispc_coefs.o dss/pll.o dss/video-pll.o
/linux-master/drivers/clk/sprd/
H A DMakefile9 clk-sprd-y += pll.o
/linux-master/drivers/clk/zynqmp/
H A Dpll.c317 struct zynqmp_pll *pll; local
330 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
331 if (!pll)
334 pll->hw.init = &init;
335 pll->clk_id = clk_id;
337 hw = &pll->hw;
340 kfree(pll);
/linux-master/drivers/clk/starfive/
H A DMakefile7 obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o
/linux-master/drivers/clk/mmp/
H A DMakefile11 obj-$(CONFIG_COMMON_CLK_MMP2) += clk-of-mmp2.o clk-pll.o pwr-island.o

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