subdev/clk/gm20b.c

160 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll)
166 	gk20a_pllg_read_mnp(&clk->base, &pll->base);
168 	pll->sdm_din = (val >> GPCPLL_CFG2_SDM_DIN_SHIFT) &
173 gm20b_pllg_write_mnp(struct gm20b_clk *clk, const struct gm20b_pll *pll)
178 		  pll->sdm_din << GPCPLL_CFG2_SDM_DIN_SHIFT);
179 	gk20a_pllg_write_mnp(&clk->base, &pll->base);
270 	struct gm20b_pll pll;
278 	gm20b_pllg_read_mnp(clk, &pll);
280 	if (n_int == pll.base.n && sdm_din == pll.sdm_din)
283 	/* pll slowdown mode */
292 	pll.base.n = n_int;
294 	gk20a_pllg_write_mnp(&clk->base, &pll.base);
360 gm20b_pllg_program_mnp(struct gm20b_clk *clk, const struct gk20a_pll *pll)
370 	gm20b_dvfs_calc_ndiv(clk, pll->n, &n_int, &sdm_din);
373 		    cur_pll.base.m == pll->m;
390 		u32 new = pll->pl;
410 		cur_pll.base = *pll;
433 gm20b_pllg_program_mnp_slide(struct gm20b_clk *clk, const struct gk20a_pll *pll)
442 		if (pll->m == cur_pll.m && pll->pl == cur_pll.pl)
443 			return gm20b_pllg_slide(clk, pll->n);
453 	cur_pll = *pll;
460 	return gm20b_pllg_slide(clk, pll->n);
488 gm20b_dvfs_calc_safe_pll(struct gm20b_clk *clk, struct gk20a_pll *pll)
490 	u32 rate = gk20a_pllg_calc_rate(&clk->base, pll) / KHZ;
501 	nmin = DIV_ROUND_UP(pll->m * clk->base.params->min_vco, parent_rate);
502 	nsafe = pll->m * rate / (clk->base.parent_rate);
505 		pll->pl = DIV_ROUND_UP(nmin * parent_rate, pll->m * rate);
509 	pll->n = nsafe;
607 			pll_safe = clk->base.pll;
632 	clk->base.pll = clk->new_pll;
634 	return gm20b_pllg_program_mnp_slide(clk, &clk->base.pll);
727 		struct gk20a_pll pll;
730 		gk20a_pllg_read_mnp(&clk->base, &pll);
731 		n_lo = gk20a_pllg_n_lo(&clk->base, &pll);