Searched refs:pipes (Results 76 - 100 of 103) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c755 struct pipe_ctx *pipes = NULL; local
761 pipes = &link->dc->current_state->res_ctx.pipe_ctx[i];
766 if (!pipes)
779 if (pipes->plane_res.xfm &&
780 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
781 pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
782 pipes->plane_res.xfm,
783 pipes->plane_res.scl_data.lb_params.depth,
787 pipes->stream_res.opp->funcs->
788 opp_program_bit_depth_reduction(pipes
795 struct pipe_ctx *pipes; local
814 struct pipe_ctx *pipes; local
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/linux-master/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-core.h288 struct mxc_isi_pipe *pipes; member in struct:mxc_isi_dev
H A Dimx8-isi-m2m.c737 m2m->pipe = &isi->pipes[0];
H A Dimx8-isi-pipe.c754 struct mxc_isi_pipe *pipe = &isi->pipes[id];
/linux-master/drivers/staging/media/ipu3/
H A Dipu3-css-params.c373 struct imgu_css_pipe *css_pipe = &css->pipes[pipe];
856 struct imgu_css_pipe *css_pipe = &css->pipes[pipe];
1636 struct imgu_css_pipe *css_pipe = &css->pipes[pipe];
1664 struct imgu_css_pipe *css_pipe = &css->pipes[pipe];
1690 struct imgu_css_pipe *css_pipe = &css->pipes[pipe];
1730 struct imgu_css_pipe *css_pipe = &css->pipes[pipe];
1904 struct imgu_css_pipe *css_pipe = &css->pipes[pipe];
1922 struct imgu_css_pipe *css_pipe = &css->pipes[pipe];
1949 struct imgu_css_pipe *css_pipe = &css->pipes[pipe];
2747 &css->fwp->binary_header[css->pipes[pip
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H A Dipu3-css-fw.c79 &css->fwp->binary_header[css->pipes[pipe].bindex];
H A Dipu3-v4l2.c66 struct imgu_css_pipe *css_pipe = &imgu->css.pipes[pipe];
679 struct imgu_css_pipe *css_pipe = &imgu->css.pipes[pipe];
1350 "failed to register pipes (%d)\n", r);
/linux-master/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_kms.c407 * Construct planes equaling the number of hw pipes, and CRTCs for the
578 const enum mdp5_pipe *pipes, const uint32_t *offsets,
587 hwpipe = mdp5_pipe_init(dev, pipes[i], offsets[i], caps);
591 pipe2name(pipes[i]), ret);
620 /* Construct RGB pipes: */
626 /* Construct video (VIG) pipes: */
632 /* Construct DMA pipes: */
638 /* Construct cursor pipes: */
577 construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, const enum mdp5_pipe *pipes, const uint32_t *offsets, uint32_t caps) argument
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c1555 /* make sure no pipes syncd to the pipe being enabled */
1968 /* TODO: If multiple pipes are to be supported, you need
1989 /* TODO: handle pipes > 1
2302 /* reset syncd pipes from disabled pipes */
2440 /* For now we are supporting only two pipes */
3118 struct pipe_ctx *pipes = local
3140 if (pipes[i].stream != NULL &&
3141 pipes[i].stream->link == link) {
3142 if (pipes[
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/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_pps.c166 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); local
182 pipes &= ~(1 << intel_dp->pps.pps_pipe);
188 pipes &= ~(1 << intel_dp->pps.active_pipe);
192 if (pipes == 0)
195 return ffs(pipes) - 1;
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h97 display_e2e_pipe_params_st *pipes,
107 display_e2e_pipe_params_st *pipes,
112 display_e2e_pipe_params_st *pipes,
164 display_e2e_pipe_params_st *pipes);
167 display_e2e_pipe_params_st *pipes);
185 void dcn32_update_dml_pipes_odm_policy_based_on_context(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
/linux-master/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c150 struct pipe_ctx *pipes[MAX_PIPES]; local
161 link_get_master_pipes_with_dpms_on(link, state, &count, pipes);
164 stream_update.stream = pipes[i]->stream;
166 pipes[i]->stream, &stream_update,
193 * This function finds all master pipes feeding to a given link with dpms set to
199 struct pipe_ctx *pipes[MAX_PIPES])
210 pipes[(*count)++] = pipe;
196 link_get_master_pipes_with_dpms_on(const struct dc_link *link, struct dc_state *state, uint8_t *count, struct pipe_ctx *pipes[MAX_PIPES]) argument
/linux-master/include/net/nfc/
H A Dnci_core.h185 struct nci_hci_pipe pipes[NCI_HCI_MAX_PIPES]; member in struct:nci_hci_dev
/linux-master/drivers/gpu/drm/gma500/
H A Dpsb_drv.c251 dev_priv->num_pipe = dev_priv->ops->pipes;
H A Doaktrail_device.c479 .pipes = 2,
H A Dcdv_device.c567 .pipes = 2,
H A Dpsb_drv.h252 /* Common status for pipes */
545 int pipes; /* Number of output pipes */ member in struct:psb_ops
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c409 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); local
410 int pipe_xor_bits = min(8, pipes +
461 AMD_FMT_MOD_SET(PIPE, pipes));
475 AMD_FMT_MOD_SET(PIPE, pipes));
600 * adev->gfx.config.gb_addr_config_fields.num_{pkrs,pipes}
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_dmub_srv.c392 uint8_t pipes = 0; local
399 pipes = i;
401 return pipes;
471 config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);
673 * @subvp_pipes: [in] Array of SubVP pipes (should always be length 2)
676 * microschedule for both SubVP pipes. In order for this to work correctly, the
677 * MALL REGION of both SubVP pipes must start at the same time. This function
825 * @enable: [in] if true enables the pipes population
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c1038 display_e2e_pipe_params_st *pipes)
1041 dcn201_populate_dml_writeback_from_context_fpu(dc, res_ctx, pipes);
1036 dcn201_populate_dml_writeback_from_context(struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) argument
/linux-master/drivers/nfc/microread/
H A Dmicroread.c64 /* Those pipes are created/opened by default in the chip */
551 u8 gate = hdev->pipes[pipe].gate;
/linux-master/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_crtc.c203 u32 events = evts->pipes[kcrtc->master->id];
/linux-master/drivers/staging/media/atomisp/pci/
H A Datomisp_fops.c284 asd->stream_env[stream_id].pipes[css_pipe_id]);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c926 /* RV1 support max 4 pipes */
1368 display_e2e_pipe_params_st *pipes,
1373 dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1366 dcn301_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
/linux-master/drivers/nfc/pn544/
H A Dpn544.c719 u8 gate = hdev->pipes[pipe].gate;

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