Searched refs:parents (Results 76 - 100 of 183) sorted by relevance

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/linux-master/drivers/pinctrl/
H A Dpinctrl-apple-gpio.c390 girq->parents = kmalloc_array(girq->num_parents,
391 sizeof(*girq->parents),
395 if (!girq->parents || !irq_data) {
405 girq->parents[i] = ret;
419 kfree(girq->parents);
H A Dpinctrl-microchip-sgpio.c880 girq->parents = devm_kcalloc(dev, 1,
881 sizeof(*girq->parents),
883 if (!girq->parents)
885 girq->parents[0] = irq;
/linux-master/drivers/rtc/
H A Drtc-ac100.c181 * The clock has two parents, one is a fixed clock which is
309 const char *parents[2] = {AC100_RTC_32K_NAME}; local
330 parents[1] = of_clk_get_parent_name(np, 0);
331 if (!parents[1]) {
341 .parent_names = parents,
342 .num_parents = ARRAY_SIZE(parents),
H A Drtc-sun6i.c233 const char *parents[2]; local
286 parents[0] = clk_hw_get_name(rtc->int_osc);
288 parents[1] = of_clk_get_parent_name(node, 0);
292 init.parent_names = parents;
293 /* ... number of clock parents will be 1. */
/linux-master/fs/xfs/scrub/
H A Dnlinks.c138 careful_add(&nl.parents, parents_delta);
182 * If we've already scanned @dp, update the number of parents that link
274 * number of parents of the root directory.
294 * number of parents linking into ino.
633 obs->parents = nl.parents;
690 * If we found so many parents that we'd overflow i_nlink, we must flag
745 if (obs.parents != 1) {
754 if (obs.parents == 0) {
H A Dparent_repair.c161 /* Number of parents we found after all other repairs */
162 unsigned long long parents; member in struct:xrep_parent
797 * directory tree, and there are no parents.
1335 * For this purpose, root directories are their own parents.
1400 rp->parents++;
1420 rp->parents = 0;
1425 if (rp->parents > 0 && xfs_inode_on_unlinked_list(ip)) {
1430 * The file is on the unlinked list but we found parents.
1443 } else if (rp->parents == 0 && !xfs_inode_on_unlinked_list(ip)) {
1449 * parents
[all...]
/linux-master/drivers/clk/bcm/
H A Dclk-bcm2835.c321 * Real names of cprman clock parents looked up through
485 const char *const *parents; member in struct:bcm2835_clock_data
488 /* Bitmap encoding which parents accept rate change propagation. */
1439 const char *parents[1 << CM_SRC_BITS]; local
1448 parents[i] = clock_data->parents[i];
1452 parents[i]);
1454 parents[i] = cprman->real_parent_names[ret];
1458 init.parent_names = parents;
1465 * rate changes on at least of the parents
[all...]
/linux-master/drivers/clk/imx/
H A Dclk-scu.c34 const char * const *parents; member in struct:imx_scu_clk_node
470 const char * const *parents, int num_parents,
493 init.parent_names = parents;
558 hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents,
688 const char * const *parents,
695 .parents = parents,
469 __imx_clk_scu(struct device *dev, const char *name, const char * const *parents, int num_parents, u32 rsrc_id, u8 clk_type) argument
687 imx_clk_scu_alloc_dev(const char *name, const char * const *parents, int num_parents, u32 rsrc_id, u8 clk_type) argument
H A Dclk-imx8mp-audiomix.c161 const struct clk_parent_data *parents; /* For mux */ member in struct:clk_imx8mp_audiomix_sel
276 sels[i].name, sels[i].parents,
H A Dclk-imx8-acm.c37 * @parents: clock parents
38 * @num_parents: clock parents number
46 const struct clk_parent_data *parents; /* For mux */ member in struct:clk_imx8_acm_sel
368 sels[i].name, sels[i].parents,
/linux-master/drivers/clk/pistachio/
H A Dclk.c81 clk = clk_register_mux(NULL, mux[i].name, mux[i].parents,
/linux-master/drivers/gpio/
H A Dgpio-xilinx.c678 girq->parents = devm_kcalloc(&pdev->dev, 1,
679 sizeof(*girq->parents),
681 if (!girq->parents) {
685 girq->parents[0] = chip->irq;
H A Dgpio-tangier.c446 girq->parents = devm_kcalloc(dev, girq->num_parents,
447 sizeof(*girq->parents), GFP_KERNEL);
448 if (!girq->parents)
451 girq->parents[0] = gpio->irq;
H A Dgpio-tegra186.c950 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
951 sizeof(*irq->parents), GFP_KERNEL);
952 if (!irq->parents)
956 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
961 irq->parents = gpio->irq;
989 irq->map[offset + j] = irq->parents[port->bank];
/linux-master/drivers/clk/zynq/
H A Dclkc.c105 const char **parents, int enable)
134 clk_register_mux(NULL, mux_name, parents, 4,
177 const char **parents, unsigned int two_gates)
191 clk_register_mux(NULL, mux_name, parents, 4,
103 zynq_clk_register_fclk(enum zynq_clk fclk, const char *clk_name, void __iomem *fclk_ctrl_reg, const char **parents, int enable) argument
174 zynq_clk_register_periph_clk(enum zynq_clk clk0, enum zynq_clk clk1, const char *clk_name0, const char *clk_name1, void __iomem *clk_ctrl, const char **parents, unsigned int two_gates) argument
/linux-master/drivers/clk/nxp/
H A Dclk-lpc32xx.c181 const u8 parents[LPC32XX_CLK_PARENTS_MAX]; member in struct:clk_proto_t
193 .parents = { __VA_ARGS__ }, \
1386 const char *parents[LPC32XX_CLK_PARENTS_MAX]; local
1391 parents[i] = clk_proto[lpc32xx_clk->parents[i]].name;
1394 parents[0], clk_hw->type);
1406 .parent_names = parents,
1455 parents, lpc32xx_clk->num_parents,
1465 parents[0], 0, fixed->fixed_rate);
/linux-master/drivers/clk/
H A Dclk-bm1880.c80 const char * const *parents; member in struct:bm1880_mux_clock
110 const char * const *parents; member in struct:bm1880_composite_clock
163 .parents = _parents, \
565 clks[i].parents,
780 parent_names = clks->parents;
H A Dclk-scmi.c461 sclk->parent_data[i].index = sclk->info->parents[i];
462 sclk->parent_data[i].hw = hws[sclk->info->parents[i]];
/linux-master/drivers/firmware/arm_scmi/
H A Dclock.c256 * num parents is not declared previously anywhere so we
261 p->clk->parents = devm_kcalloc(dev, p->clk->num_parents,
262 sizeof(*p->clk->parents),
264 if (!p->clk->parents) {
282 u32 *parent = &p->clk->parents[st->desc_index + st->loop_idx];
680 cfg->parent_id = cpu_to_le32(clk->parents[parent_id]);
/linux-master/drivers/pinctrl/bcm/
H A Dpinctrl-bcm2835.c448 if (chip->irq.parents[i] == irq) {
1362 girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1363 sizeof(*girq->parents),
1365 if (!girq->parents) {
1391 girq->parents[i] = irq_of_parse_and_map(np, i);
1393 if (!girq->parents[i]) {
/linux-master/drivers/clk/starfive/
H A Dclk-starfive-jh7110-pll.c472 struct clk_parent_data parents = { local
478 .parent_data = &parents,
/linux-master/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c121 const struct clk_parent_data *parents,
135 init.parent_data = parents;
119 meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, const char *name_suffix, const struct clk_parent_data *parents, int num_parents, const struct clk_ops *ops, struct clk_hw *hw) argument
/linux-master/drivers/phy/ti/
H A Dphy-j721e-wiz.c230 u32 parents[WIZ_MAX_INPUT_CLOCKS]; member in struct:wiz_clk_mux_sel
272 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
278 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
284 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
293 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
299 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
305 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
832 clk = wiz->input_clks[mux_sel->parents[i]];
888 dev_err(dev, "SERDES clock must have parents\n");
/linux-master/drivers/bcma/
H A Ddriver_gpio.c150 girq->parents = NULL;
/linux-master/drivers/clk/ti/
H A Dadpll.c272 const char *parents[2]; local
278 parents[0] = __clk_get_name(clk0);
279 parents[1] = __clk_get_name(clk1);
280 clock = clk_register_mux(d->dev, child_name, parents, 2, 0,

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