#
2029e714 |
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21-Dec-2023 |
Chintan Vankar <c-vankar@ti.com> |
phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J784S4 Enable full rate divider configuration support for J784S4_WIZ_10G for SGMII. Signed-off-by: Chintan Vankar <c-vankar@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20231221102956.754617-2-c-vankar@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
2230aa25 |
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05-May-2023 |
Maxime Ripard <mripard@kernel.org> |
phy: ti: j721e-wiz: Add a determine_rate hook The TI J721e Wiz clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the flag CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook to __clk_mux_determine_rate(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Since the CLK_SET_RATE_NO_REPARENT flag was already set though, it seems unlikely. Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-phy@lists.infradead.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-44-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
ec318c51 |
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09-Mar-2023 |
Siddharth Vadapalli <s-vadapalli@ti.com> |
phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J721E Enable full rate divider configuration support for J721E_WIZ_16G for SGMII. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230309092434.443550-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
57c0e136 |
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03-Apr-2023 |
Siddharth Vadapalli <s-vadapalli@ti.com> |
phy: ti: j721e-wiz: Fix unreachable code in wiz_mode_select() In the wiz_mode_select() function, the configuration performed for PHY_TYPE_USXGMII is unreachable. Fix it. Fixes: b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230403094552.929108-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
db850ea9 |
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06-Mar-2023 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
phy: ti: phy-j721e-wiz: Convert to platform remove callback returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230307115900.2293120-29-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
494de1dd |
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13-Jan-2023 |
Sinthu Raja <sinthu.raja@ti.com> |
phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the USB PHY that is integrated into the SerDes IP. The WIZ control register has to be configured to support this lane swap feature. The support for swapping lanes 2 and 3 is missing and therefore add support to configure the control register to swap between lanes 2 and 3 if PHY type is USB. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230113150615.19375-3-sinthu.raja@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
9a8a54b9 |
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13-Jan-2023 |
Sinthu Raja <sinthu.raja@ti.com> |
phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified It's possible that the Type-C plug orientation on the DIR line will be implemented through hardware design. In that situation, there won't be an external GPIO line available, but the driver still needs to address this since the DT won't use the typec-dir-gpios property. Add code to handle LN10 Type-C swap if typec-dir-gpios property is not specified in DT. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230113150615.19375-2-sinthu.raja@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
bea3ce75 |
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22-Nov-2022 |
Matt Ranostay <mranostay@ti.com> |
phy: ti: phy-j721e-wiz: add j721s2-wiz-10g module support Add support for j721s2-wiz-10g device which is similar to j721e-wiz-10g but uses clock-names interface versus explicitly defining clock nodes within device tree node. Signed-off-by: Matt Ranostay <mranostay@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20221123032413.1193961-3-mranostay@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
e27ecef8 |
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15-Oct-2022 |
Matt Ranostay <mranostay@ti.com> |
phy: ti: phy-j721e-wiz: add j784s4-wiz-10g module support Add support for j784s4-wiz-10g device which has two core reference clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional mux selection option. Acked-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Matt Ranostay <mranostay@ti.com> Link: https://lore.kernel.org/r/20221015201123.195477-3-mranostay@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
a270cc13 |
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22-Sep-2022 |
Dan Carpenter <dan.carpenter@oracle.com> |
phy: ti: phy-j721e-wiz: fix reference leaks in wiz_probe() These two error paths need to call of_node_put(child_node) before returning. Fixes: edd473d4293a ("phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g") Fixes: 7ae14cf581f2 ("phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/YyxFI8aW23IC/21U@kili Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
1fbef61b |
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09-Sep-2022 |
Matt Ranostay <mranostay@ti.com> |
phy: ti: phy-j721e-wiz: stop name conflict if multiple serdes are initialized When multiple serdes instances are initialized the first will succeed but additional will conflict over clocks names and probing fails. Signed-off-by: Matt Ranostay <mranostay@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20220909200026.3422-1-mranostay@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
86d11e22 |
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28-Jun-2022 |
Roger Quadros <rogerq@kernel.org> |
phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate For J7200-SR2.0 and AM64 we don't model Common refclock divider as a clock divider as the divisor rate is fixed based on operating reference clock frequency. We just program the recommended value into the register. This simplifies the device tree and implementation a lot. Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20220628122255.24265-8-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
edd473d4 |
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28-Jun-2022 |
Roger Quadros <rogerq@kernel.org> |
phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g j7200-wiz-10g supports 2 reference clocks. However, the control bits for these clocks is in a separate register that sits in the System Control register space. Handle that register. Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20220628122255.24265-7-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
b64a85fb |
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28-Jun-2022 |
Tanmay Patil <t-patil@ti.com> |
phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver Changes the wiz_p_mac_div_sel() and wiz_mode_select() to configure serdes for USXGMII. Adds the support to configure mac_src_sel, refclk_sel and rxfclk_sel in the LANECTL register and configures the serdes for usxgmii. [rogerq] Fix MAC_SRC_SEL to 0x3 for USXGMII as per CSL code. Signed-off-by: Tanmay Patil <t-patil@ti.com> Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20220628122255.24265-4-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
27ecdd07 |
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28-Jun-2022 |
Siddharth Vadapalli <s-vadapalli@ti.com> |
phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200 Select the same mac divider for SGMII too as the one being used for QSGMII. Enable full rate divider configuration support for J721E_WIZ_10G for SGMII. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20220628122255.24265-2-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
4daa43e9 |
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26-May-2022 |
Roger Quadros <rogerq@kernel.org> |
phy: ti: phy-j721e-wiz: use OF data for device specific data Move device specific data into OF data structure so it is easier to maintain and we can get rid of if statements. Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Matt Ranostay <mranostay@ti.com> Link: https://lore.kernel.org/r/20220526064121.27625-1-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
6d1e6bcb |
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17-Jan-2022 |
Kishon Vijay Abraham I <kishon@ti.com> |
phy: ti: Fix missing sentinel for clk_div_table _get_table_maxdiv() tries to access "clk_div_table" array out of bound defined in phy-j721e-wiz.c. Add a sentinel entry to prevent the following global-out-of-bounds error reported by enabling KASAN. [ 9.552392] BUG: KASAN: global-out-of-bounds in _get_maxdiv+0xc0/0x148 [ 9.558948] Read of size 4 at addr ffff8000095b25a4 by task kworker/u4:1/38 [ 9.565926] [ 9.567441] CPU: 1 PID: 38 Comm: kworker/u4:1 Not tainted 5.16.0-116492-gdaadb3bd0e8d-dirty #360 [ 9.576242] Hardware name: Texas Instruments J721e EVM (DT) [ 9.581832] Workqueue: events_unbound deferred_probe_work_func [ 9.587708] Call trace: [ 9.590174] dump_backtrace+0x20c/0x218 [ 9.594038] show_stack+0x18/0x68 [ 9.597375] dump_stack_lvl+0x9c/0xd8 [ 9.601062] print_address_description.constprop.0+0x78/0x334 [ 9.606830] kasan_report+0x1f0/0x260 [ 9.610517] __asan_load4+0x9c/0xd8 [ 9.614030] _get_maxdiv+0xc0/0x148 [ 9.617540] divider_determine_rate+0x88/0x488 [ 9.622005] divider_round_rate_parent+0xc8/0x124 [ 9.626729] wiz_clk_div_round_rate+0x54/0x68 [ 9.631113] clk_core_determine_round_nolock+0x124/0x158 [ 9.636448] clk_core_round_rate_nolock+0x68/0x138 [ 9.641260] clk_core_set_rate_nolock+0x268/0x3a8 [ 9.645987] clk_set_rate+0x50/0xa8 [ 9.649499] cdns_sierra_phy_init+0x88/0x248 [ 9.653794] phy_init+0x98/0x108 [ 9.657046] cdns_pcie_enable_phy+0xa0/0x170 [ 9.661340] cdns_pcie_init_phy+0x250/0x2b0 [ 9.665546] j721e_pcie_probe+0x4b8/0x798 [ 9.669579] platform_probe+0x8c/0x108 [ 9.673350] really_probe+0x114/0x630 [ 9.677037] __driver_probe_device+0x18c/0x220 [ 9.681505] driver_probe_device+0xac/0x150 [ 9.685712] __device_attach_driver+0xec/0x170 [ 9.690178] bus_for_each_drv+0xf0/0x158 [ 9.694124] __device_attach+0x184/0x210 [ 9.698070] device_initial_probe+0x14/0x20 [ 9.702277] bus_probe_device+0xec/0x100 [ 9.706223] deferred_probe_work_func+0x124/0x180 [ 9.710951] process_one_work+0x4b0/0xbc0 [ 9.714983] worker_thread+0x74/0x5d0 [ 9.718668] kthread+0x214/0x230 [ 9.721919] ret_from_fork+0x10/0x20 [ 9.725520] [ 9.727032] The buggy address belongs to the variable: [ 9.732183] clk_div_table+0x24/0x440 Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Cc: stable@vger.kernel.org # v5.10+ Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20220117110108.4117-1-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
7adaf921 |
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14-Nov-2021 |
Randy Dunlap <rdunlap@infradead.org> |
phy: ti: report 2 non-kernel-doc comments Do not use "/**" to begin a non-kernel-doc comment. Fixes these build warnings: drivers/phy/ti/phy-am654-serdes.c:3: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * PCIe SERDES driver for AM654x SoC drivers/phy/ti/phy-j721e-wiz.c:3: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Wrapper driver for SERDES used in J721E Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-phy@lists.infradead.org Link: https://lore.kernel.org/r/20211115030559.13994-1-rdunlap@infradead.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
b8203ec7 |
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25-May-2021 |
Yang Li <yang.lee@linux.alibaba.com> |
phy: ti: Fix an error code in wiz_probe() When the code execute this if statement, the value of ret is 0. However, we can see from the dev_err() log that the value of ret should be -EINVAL. Clean up smatch warning: drivers/phy/ti/phy-j721e-wiz.c:1216 wiz_probe() warn: missing error code 'ret' Reported-by: Abaci Robot <abaci@linux.alibaba.com> Fixes: c9f9eba06629 ("phy: ti: j721e-wiz: Manage typec-gpio-dir") Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1621939832-65535-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
ed917b02 |
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08-Apr-2021 |
Vinod Koul <vkoul@kernel.org> |
phy: Revert "phy: ti: j721e-wiz: add missing of_node_put" This reverts commit 00f2e6f668b0 ("phy: ti: j721e-wiz: add missing of_node_put") as it erroneously adds the of_node_put() as incorrect place. Reported-by: Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210408062914.3813102-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
76b45387 |
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07-Apr-2021 |
Shixin Liu <liushixin2@huawei.com> |
phy: ti: j721e-wiz: Add missing include linux/slab.h When compiling with CONFIG_PHY_J721E_WIZ, Hulk Robot reported: drivers/phy/ti/phy-j721e-wiz.c: In function ‘wiz_mux_clk_register’: drivers/phy/ti/phy-j721e-wiz.c:659:17: error: implicit declaration of function ‘kzalloc’; did you mean ‘vzalloc’? [-Werror=implicit-function-declaration] 659 | parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); | ^~~~~~~ | vzalloc drivers/phy/ti/phy-j721e-wiz.c:659:15: warning: assignment to ‘const char **’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion] 659 | parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); | ^ drivers/phy/ti/phy-j721e-wiz.c:697:2: error: implicit declaration of function ‘kfree’; did you mean ‘vfree’? [-Werror=implicit-function-declaration] 697 | kfree(parent_names); | ^~~~~ | vfre Fixes: 040cbe768731 ("phy: ti: j721e-wiz: Model the internal clocks without device tree input") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Shixin Liu <liushixin2@huawei.com> Link: https://lore.kernel.org/r/20210408012829.432938-1-liushixin2@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
36a81383 |
|
31-Mar-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
phy: ti: j721e-wiz: Configure 'p_standard_mode' only for DP/QSGMII Configure 'p_standard_mode' only for DP/QSGMII as for other modes it's not used as per the programming sequence. Add "continue" in the else to prevent random value from being written to p_standard_mode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210331131417.15596-1-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
725c7b8d |
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30-Mar-2021 |
Faiz Abbas <faiz_abbas@ti.com> |
phy: ti: j721e-wiz: Do not configure wiz if its already configured Serdes lanes might be shared between multiple cores in some usecases and its not possible to lock PLLs for both the lanes independently by the two cores. This requires a bootloader to configure both the lanes at early boot time. To handle this case, skip all configuration if any of the lanes has already been enabled. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210330110138.24356-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
3fb95456 |
|
19-Mar-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode "serdes" node (child node of WIZ) can have sub-nodes for representing links or it can have sub-nodes for representing the various clocks within the serdes. Instead of trying to read "reg" from every child node used for assigning "lane_phy_type", read only if the child node's name is "phy" or "link" subnode. Ideally all PHY dt nodes should have node name as "phy", however existing devicetree used "link" as subnode. So in order to maintain old DT compatibility get PHY properties for "phy" or "link" subnode. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210319124128.13308-5-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
f7eb147d |
|
19-Mar-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() Invoke wiz_init() before configuring anything else in Sierra/Torrent (invoked as part of of_platform_device_create()). wiz_init() resets the SERDES device and any configuration done in the probe() of Sierra/Torrent will be lost. In order to prevent SERDES configuration from getting reset, invoke wiz_init() immediately before invoking of_platform_device_create(). Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Cc: <stable@vger.kernel.org> # v5.10 Link: https://lore.kernel.org/r/20210319124128.13308-3-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
f26fde36 |
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25-Feb-2021 |
Yang Li <yang.lee@linux.alibaba.com> |
phy: ti: j721e-wiz: add missing call to of_node_put() In one of the error paths of the for_each_child_of_node() loop in of_property_read_u32, add missing call to of_node_put(). Fix the following coccicheck warning: ./drivers/phy/ti/phy-j721e-wiz.c:786:1-23: WARNING: Function "for_each_child_of_node" should have of_node_put() before return around line 795. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1614244674-66556-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
48820990 |
|
03-Mar-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
phy: ti: j721e-wiz: Add support for configuring QSGMII Configure MAC clock dividers required for QSGMII to be functional. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1614838096-32291-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
9e405f87 |
|
10-Mar-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m> cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. In order to drive the refclk out from the SERDES (Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM can enable it. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-6-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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#
040cbe76 |
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10-Mar-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
phy: ti: j721e-wiz: Model the internal clocks without device tree input commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled the internal clocks depending on the subnodes that are populated in device tree. However recent discussions in the mailing list [1] suggested to just add #clock cells in the parent DT node and model the clocks within the driver. Model the mux clocks without device tree input for AM64x SoC. Don't remove the earlier design since DT nodes for J7200 and J721e are already upstreamed. [1] -> http://lore.kernel.org/r/20210108025943.GA1790601@robh.at.kernel.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-5-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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6ecac2f8 |
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10-Mar-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
phy: ti: j721e-wiz: Configure full rate divider for AM64 The frequency of the txmclk between PCIe and SERDES has changed to 250MHz from 500MHz. Configure full rate divider for AM64 accordingly. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-4-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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7e52a39f |
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10-Mar-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanup commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled both MUX clocks and DIVIDER clocks in wiz. However during cleanup, it removed only the MUX clock provider. Remove the DIVIDER clock provider here. Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-3-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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549cb1ae |
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10-Mar-2021 |
Kishon Vijay Abraham I <kishon@ti.com> |
phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_sel Both "struct wiz_clk_div_sel" and "struct wiz_clk_mux_sel" are static data that is common for all wiz instances. Including "struct regmap_field" for each of the wiz instances can yield undesirable results. Move "struct regmap_field" out of "struct wiz_clk_div_sel" and "struct wiz_clk_mux_sel" and make them point to constant data. So far no issues are observed since both these structures are not accessed outside the probe. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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00f2e6f6 |
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16-Feb-2021 |
Junlin Yang <yangjunlin@yulong.com> |
phy: ti: j721e-wiz: add missing of_node_put Fix OF node leaks by calling of_node_put in for_each_child_of_node when the cycle returns. Generated by: scripts/coccinelle/iterators/for_each_child.cocci Signed-off-by: Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210216082739.1414-1-angkery@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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c42dcb19 |
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18-Aug-2020 |
YueHaibing <yuehaibing@huawei.com> |
phy: ti: j721e-wiz: Remove duplicate include Remove duplicate include file Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20200818114721.55464-1-yuehaibing@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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5a72122d |
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24-May-2020 |
Rikard Falkeborn <rikard.falkeborn@gmail.com> |
phy: ti: j721e-wiz: Constify structs clk_div_table and wiz_regmap_config are not modified and can therefore be made const to allow the compiler to put them in read-only memory. Before: text data bss dec hex filename 20265 7044 64 27373 6aed drivers/phy/ti/phy-j721e-wiz.o After: text data bss dec hex filename 20649 6660 64 27373 6aed drivers/phy/ti/phy-j721e-wiz.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200524095516.25227-3-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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e2ae8bca |
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06-May-2020 |
Wei Yongjun <weiyongjun1@huawei.com> |
phy: ti: j721e-wiz: Fix some error return code in wiz_probe() Fix to return negative error code from some error handling cases instead of 0, as done elsewhere in this function. Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Roger Quadros <rogerq@ti.com> Link: https://lore.kernel.org/r/20200507054109.110849-1-weiyongjun1@huawei.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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7ae14cf5 |
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08-Jan-2020 |
Jyri Sarha <jsarha@ti.com> |
phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver For DisplayPort use we need to set WIZ_CONFIG_LANECTL register's P_STANDARD_MODE bits to "mode 3". In the DisplayPort use also the P_ENABLE bits of the same register are set to P_ENABLE instead of P_ENABLE_FORCE, so that the DisplayPort driver can enable and disable the lane as needed. The DisplayPort mode is selected according to "cdns,phy-type"-properties found in link subnodes under the managed serdes (see "ti,sierra-phy-t0" and "ti,j721e-serdes-10g" devicetree bindings for details). All other values of "cdns,phy-type"-property but PHY_TYPE_DP will set P_STANDARD_MODE bits to 0 and P_ENABLE bits to force enable. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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0d5677ec |
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09-Jan-2020 |
Wei Yongjun <weiyongjun1@huawei.com> |
phy: ti: j721e-wiz: Fix return value check in wiz_probe() In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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c9f9eba0 |
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06-Jan-2020 |
Roger Quadros <rogerq@ti.com> |
phy: ti: j721e-wiz: Manage typec-gpio-dir Based on this GPIO state we need to configure LN10 bit to swap lane0 and lane1 if required (flipped connector). Type-C companions typically need some time after the cable is plugged before and before they reflect the correct status of Type-C plug orientation on the DIR line. Type-C Spec specifies CC attachment debounce time (tCCDebounce) of 100 ms (min) to 200 ms (max). Use the DT property to figure out if we need to add delay or not before sampling the Type-C DIR line. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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091876cc |
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16-Dec-2019 |
Kishon Vijay Abraham I <kishon@ti.com> |
phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig), two divider clocks and supports resets for each of the lanes. [jsarha@ti.com: Add support for Torrent(10G) SERDES wrapper] Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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