/linux-master/arch/arm/mm/ |
H A D | proc-fa526.S | 41 mcr p15, 0, r0, c1, c0, 0 @ disable caches 61 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 62 mcr p15, 0, ip, c7, c10, 4 @ drain WB 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 70 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 86 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 90 mcr p15, 0, r0, c7, c10, 4 @ drain WB 108 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 110 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 112 mcr p1 [all...] |
H A D | proc-mohawk.S | 46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 66 mcr p15, 0, ip, c7, c10, 4 @ drain WB 67 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 71 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 84 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 96 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 117 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 142 mcr p1 [all...] |
H A D | proc-arm946.S | 51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 63 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 64 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 65 mcr p15, 0, ip, c7, c10, 4 @ drain WB 69 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 79 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 90 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 109 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 113 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 144 mcr p1 [all...] |
H A D | proc-arm940.S | 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 56 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 57 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 58 mcr p15, 0, ip, c7, c10, 4 @ drain WB 62 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 72 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 115 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 119 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 174 2: mcr p1 [all...] |
H A D | cache-v6.S | 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 143 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 150 mcr p1 [all...] |
H A D | tlb-fa.S | 41 mcr p15, 0, r3, c7, c10, 4 @ drain WB 44 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 48 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 55 mcr p15, 0, r3, c7, c10, 4 @ drain WB 58 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 62 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 63 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)
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H A D | proc-arm920.S | 63 mcr p15, 0, r0, c1, c0, 0 @ disable caches 80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 81 mcr p15, 0, ip, c7, c10, 4 @ drain WB 83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 88 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 98 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 111 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 161 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 200 1: mcr p1 [all...] |
H A D | proc-sa1100.S | 42 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 43 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 55 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 59 mcr p15, 0, r0, c1, c0, 0 @ disable caches 76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 77 mcr p15, 0, ip, c7, c10, 4 @ drain WB 79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching 113 mcr p1 [all...] |
H A D | proc-arm922.S | 65 mcr p15, 0, r0, c1, c0, 0 @ disable caches 82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 83 mcr p15, 0, ip, c7, c10, 4 @ drain WB 85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 90 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 136 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 163 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 202 1: mcr p1 [all...] |
H A D | proc-sa110.S | 38 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 47 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching 51 mcr p15, 0, r0, c1, c0, 0 @ disable caches 68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 69 mcr p15, 0, ip, c7, c10, 4 @ drain WB 71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 76 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 95 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching 101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned 105 mcr p1 [all...] |
H A D | proc-arm1020e.S | 71 mcr p15, 0, r0, c1, c0, 0 @ disable caches 88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 89 mcr p15, 0, ip, c7, c10, 4 @ drain WB 91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 145 mcr p15, 0, ip, c7, c10, 4 @ drain WB 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 179 1: mcr p1 [all...] |
H A D | proc-arm926.S | 55 mcr p15, 0, r0, c1, c0, 0 @ disable caches 72 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 73 mcr p15, 0, ip, c7, c10, 4 @ drain WB 75 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 80 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 94 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 99 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 101 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 113 mcr p1 [all...] |
H A D | proc-xsc3.S | 69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 94 mcr p15, 0, r0, c1, c0, 0 @ disable caches 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 140 mcr p14, 0, r0, c7, c0, 0 @ go to idle 153 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 201 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 233 1: mcr p1 [all...] |
H A D | proc-arm1020.S | 71 mcr p15, 0, r0, c1, c0, 0 @ disable caches 88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 89 mcr p15, 0, ip, c7, c10, 4 @ drain WB 91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 145 mcr p15, 0, ip, c7, c10, 4 @ drain WB 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 149 mcr p1 [all...] |
H A D | proc-v6.S | 46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 64 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 66 mcr p15, 0, r1, c7, c5, 4 @ ISB 80 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 81 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 86 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 110 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 111 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 118 mcr p1 [all...] |
H A D | proc-arm925.S | 86 mcr p15, 0, r0, c1, c0, 0 @ disable caches 112 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 113 mcr p15, 0, ip, c7, c10, 4 @ drain WB 115 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 120 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 132 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 134 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 135 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 136 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 147 mcr p1 [all...] |
H A D | cache-fa.S | 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 93 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 132 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 133 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 138 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 139 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 140 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush 155 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 160 mcr p1 [all...] |
H A D | proc-arm1026.S | 71 mcr p15, 0, r0, c1, c0, 0 @ disable caches 88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 89 mcr p15, 0, ip, c7, c10, 4 @ drain WB 91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 217 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 220 mcr p1 [all...] |
H A D | proc-arm1022.S | 71 mcr p15, 0, r0, c1, c0, 0 @ disable caches 88 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 89 mcr p15, 0, ip, c7, c10, 4 @ drain WB 91 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 96 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 222 mcr p1 [all...] |
H A D | tlb-v6.S | 40 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1) 58 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier 72 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 79 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 80 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 82 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA 87 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier 88 mcr p1 [all...] |
/linux-master/drivers/w1/masters/ |
H A D | sgi_w1.c | 23 u32 __iomem *mcr; member in struct:sgi_w1_device 28 static u8 sgi_w1_wait(u32 __iomem *mcr) argument 33 mcr_val = readl(mcr); 49 writel(MCR_PACK(520, 65), dev->mcr); 50 ret = sgi_w1_wait(dev->mcr); 66 writel(MCR_PACK(6, 13), dev->mcr); 68 writel(MCR_PACK(80, 30), dev->mcr); 70 ret = sgi_w1_wait(dev->mcr); 86 sdev->mcr = devm_platform_ioremap_resource(pdev, 0); 87 if (IS_ERR(sdev->mcr)) [all...] |
/linux-master/arch/sh/drivers/pci/ |
H A D | fixups-rts7751r2d.c | 41 unsigned long bcr1, mcr; local 54 mcr = __raw_readl(SH7751_MCR); 55 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 56 pci_write_reg(chan, mcr, SH4_PCIMCR);
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H A D | fixups-landisk.c | 41 unsigned long bcr1, mcr; local 47 mcr = __raw_readl(SH7751_MCR); 48 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 49 pci_write_reg(chan, mcr, SH4_PCIMCR);
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/linux-master/arch/arm/boot/compressed/ |
H A D | big-endian.S | 13 mcr p15, 0, r0, c1, c0, 0 @ write control reg
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/linux-master/arch/arm/common/ |
H A D | secure_cntvoff.S | 23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */ 28 mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
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