/linux-master/drivers/clk/bcm/ |
H A D | clk-bcm281xx.c | 18 .div = FRAC_DIVIDER(0x0e00, 0, 22, 16), 48 .div = DIVIDER(0x0a04, 3, 4), 56 .div = DIVIDER(0x0a00, 4, 5), 102 .div = DIVIDER(0x0a28, 4, 14), 114 .div = DIVIDER(0x0a2c, 4, 14), 126 .div = DIVIDER(0x0a34, 4, 14), 138 .div = DIVIDER(0x0a30, 4, 14), 147 .div = FIXED_DIVIDER(2), 159 .div = FIXED_DIVIDER(2), 166 .div [all...] |
/linux-master/drivers/clk/ingenic/ |
H A D | jz4760-cgu.c | 150 .div = { 158 .div = { 166 .div = { 174 .div = { 187 .div = { 195 .div = { 206 .div = { 218 .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 }, 225 .div = { CGU_REG_GPUCDR, 0, 1, 3, -1, -1, -1 }, 232 .div [all...] |
H A D | jz4755-cgu.c | 79 .div = { 88 .div = { 97 .div = { 106 .div = { 115 .div = { 124 .div = { 133 .div = { 143 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, 150 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, 157 .div [all...] |
/linux-master/drivers/clk/mvebu/ |
H A D | clk-cpu.c | 52 u32 reg, div; local 55 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; 56 return parent_rate / div; 63 u32 div; local 65 div = *parent_rate / rate; 66 if (div == 0) 67 div = 1; 68 else if (div > 3) 69 div = 3; 71 return *parent_rate / div; 79 u32 reg, div; local [all...] |
H A D | armada-39x.c | 92 void __iomem *sar, int id, int *mult, int *div) 97 *div = 2; 101 *div = 4; 105 *div = 2; 91 armada_39x_get_clk_ratio( void __iomem *sar, int id, int *mult, int *div) argument
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/linux-master/drivers/clk/imx/ |
H A D | clk-busy.c | 28 struct clk_divider div; member in struct:clk_busy_divider 36 struct clk_divider *div = to_clk_divider(hw); local 38 return container_of(div, struct clk_busy_divider, div); 46 return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate); 54 return busy->div_ops->round_rate(&busy->div.hw, rate, prate); 63 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); 92 busy->div.reg = reg; 93 busy->div.shift = shift; 94 busy->div [all...] |
/linux-master/drivers/clk/at91/ |
H A D | clk-sam9x60-pll.c | 50 u8 div; member in struct:sam9x60_div 337 static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div, argument 346 (div << core->layout->div_shift) | ena_val); 358 struct sam9x60_div *div = to_sam9x60_div(core); local 370 if (!!(val & core->layout->endiv_mask) && cdiv == div->div) 373 sam9x60_div_pll_set_div(core, div->div, 1); 431 struct sam9x60_div *div = to_sam9x60_div(core); local 433 return DIV_ROUND_CLOSEST_ULL(parent_rate, (div 491 struct sam9x60_div *div = to_sam9x60_div(core); local 502 struct sam9x60_div *div = to_sam9x60_div(core); local 530 struct sam9x60_div *div = to_sam9x60_div(core); local 540 struct sam9x60_div *div = to_sam9x60_div(core); local 549 struct sam9x60_div *div = notifier_div; local 704 struct sam9x60_div *div; local [all...] |
H A D | clk-audio-pll.c | 29 * clk->rate = parent->rate / (qdaudio * div)) 47 #define AUDIO_PLL_QDPAD(qd, div) ((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \ 49 (AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \ 69 u8 div; member in struct:clk_audio_pad 113 AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div)); 193 if (apad_ck->qdaudio && apad_ck->div) 194 apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div); 196 pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n", 197 __func__, apad_rate, apad_ck->div, apad_ck->qdaudio); 280 u32 div; local 330 u32 tmp_qd = 0, div; local [all...] |
/linux-master/drivers/pwm/ |
H A D | pwm-keembay.c | 124 unsigned long long div; local 154 div = clk_rate * state->duty_cycle; 155 div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC); 156 if (div > KMB_PWM_COUNT_MAX) 159 high = div; 160 div = clk_rate * state->period; 161 div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC); 162 div [all...] |
/linux-master/drivers/clk/xilinx/ |
H A D | clk-xlnx-clock-wizard.c | 155 * @table: array of value/divider pairs, last entry should have div = 0 196 u32 div, p5en, edge, prediv2, all; local 209 div = 2 * all + prediv2 * p5en; 211 div = all; 213 return DIV_ROUND_UP_ULL((u64)parent_rate, div); 323 u8 div; local 329 div = DIV_ROUND_CLOSEST(*prate, rate); 331 return *prate / div; 568 u32 m, d, o, div, reg, f; local 577 div 587 u32 div, reg; local 653 u32 m, d, o, div, f; local 703 u32 div, frac; local 778 struct clk_wzrd_divider *div; local 822 struct clk_wzrd_divider *div; local 868 struct clk_wzrd_divider *div; local 969 u32 regl, regh, edge, regld, reghd, edged, div; local [all...] |
/linux-master/drivers/clk/mxs/ |
H A D | Makefile | 6 obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o clk-ssp.o
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/linux-master/drivers/clk/uniphier/ |
H A D | clk-uniphier-fixed-factor.c | 31 fix->div = data->div;
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/linux-master/drivers/clk/pistachio/ |
H A D | clk.c | 92 struct pistachio_div *div, 99 clk = clk_register_divider(NULL, div[i].name, div[i].parent, 100 0, p->base + div[i].reg, 0, 101 div[i].width, div[i].div_flags, 103 p->clk_data.clks[div[i].id] = clk; 116 0, 1, ff[i].div); 91 pistachio_clk_register_div(struct pistachio_clk_provider *p, struct pistachio_div *div, unsigned int num) argument
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/linux-master/arch/nios2/ |
H A D | Makefile | 30 KBUILD_CFLAGS += $(if $(CONFIG_NIOS2_HW_DIV_SUPPORT),-mhw-div,-mno-hw-div)
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/linux-master/lib/crypto/mpi/ |
H A D | Makefile | 22 mpi-div.o \ 27 mpih-div.o \
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/linux-master/drivers/clk/x86/ |
H A D | clk-lgm.c | 125 { .val = 0, .div = 1 }, 126 { .val = 1, .div = 2 }, 127 { .val = 2, .div = 3 }, 128 { .val = 3, .div = 4 }, 129 { .val = 4, .div = 5 }, 130 { .val = 5, .div = 6 }, 131 { .val = 6, .div = 8 }, 132 { .val = 7, .div = 10 }, 133 { .val = 8, .div = 12 }, 134 { .val = 9, .div [all...] |
/linux-master/drivers/clk/renesas/ |
H A D | clk-div6.c | 30 * @div: divisor value (1-64) 38 unsigned int div; member in struct:div6_clock 52 | CPG_DIV6_DIV(clock->div - 1); 88 return parent_rate / clock->div; 94 unsigned int div; local 99 div = DIV_ROUND_CLOSEST(parent_rate, rate); 100 return clamp(div, 1U, 64U); 109 unsigned int i, min_div, max_div, div; local 126 div = cpg_div6_clock_calc_div(req->rate, prate); 127 div 152 unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate); local [all...] |
/linux-master/drivers/clk/ |
H A D | clk-apple-nco.c | 125 static bool applnco_div_out_of_range(unsigned int div) argument 127 unsigned int coarse = div / 4; 133 static u32 applnco_div_translate(struct applnco_tables *tbl, unsigned int div) argument 135 unsigned int coarse = div / 4; 137 if (WARN_ON(applnco_div_out_of_range(div))) 141 FIELD_PREP(DIV_FINE, div % 4); 159 u32 div, inc1, inc2; local 162 div = 2 * parent_rate / rate; 163 inc1 = 2 * parent_rate - div * rate; 166 if (applnco_div_out_of_range(div)) 193 u32 div, inc1, inc2, incbase; local [all...] |
H A D | clk-bm1880.c | 99 struct bm1880_div_clock div; member in struct:bm1880_div_hw_clock 185 .div.id = _id, \ 186 .div.name = _name, \ 187 .div.reg = _reg, \ 188 .div.shift = _shift, \ 189 .div.width = _width, \ 190 .div.initval = _initval, \ 191 .div.table = _table, \ 593 struct bm1880_div_clock *div = &div_hw->div; local 615 struct bm1880_div_clock *div = &div_hw->div; local 637 struct bm1880_div_clock *div = &div_hw->div; local [all...] |
/linux-master/arch/x86/include/asm/ |
H A D | div64.h | 87 static inline u64 mul_u64_u64_div_u64(u64 a, u64 mul, u64 div) argument 92 : "a" (a), "rm" (mul), "rm" (div) 99 static inline u64 mul_u64_u32_div(u64 a, u32 mul, u32 div) argument 101 return mul_u64_u64_div_u64(a, mul, div);
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/linux-master/drivers/clk/sprd/ |
H A D | div.h | 36 struct sprd_div_internal div; member in struct:sprd_div 43 .div = _SPRD_DIV_CLK(_offset, _shift, _width), \ 75 const struct sprd_div_internal *div, 79 const struct sprd_div_internal *div,
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H A D | composite.c | 17 return divider_determine_rate(hw, req, NULL, cc->div.width, 0); 25 return sprd_div_helper_recalc_rate(&cc->common, &cc->div, parent_rate); 33 return sprd_div_helper_set_rate(&cc->common, &cc->div,
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/linux-master/drivers/clk/rockchip/ |
H A D | clk.c | 51 struct clk_divider *div = NULL; local 86 div = kzalloc(sizeof(*div), GFP_KERNEL); 87 if (!div) { 92 div->flags = div_flags; 94 div->reg = base + div_offset; 96 div->reg = base + muxdiv_offset; 97 div->shift = div_shift; 98 div->width = div_width; 99 div 127 struct clk_fractional_divider div; member in struct:rockchip_clk_frac 217 struct clk_fractional_divider *div = NULL; local 314 rockchip_clk_register_factor_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, unsigned int mult, unsigned int div, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) argument [all...] |
/linux-master/drivers/media/test-drivers/vicodec/ |
H A D | codec-fwht.h | 64 #define vic_round_dim(dim, div) (round_up((dim) / (div), 8) * (div))
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/linux-master/drivers/gpu/ipu-v3/ |
H A D | ipu-di.c | 266 struct ipu_di_signal_cfg *sig, int div) 281 .offset_count = div * sig->v_to_h_sync, 337 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ 363 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */ 422 unsigned div; local 427 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); 428 div = clamp(div, 1U, 255U); 430 clkgen0 = div << 4; 441 unsigned div, erro local 265 ipu_di_sync_config_noninterlaced(struct ipu_di *di, struct ipu_di_signal_cfg *sig, int div) argument 461 unsigned div; local 565 u32 div; local [all...] |