1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Marvell Armada 39x SoC clocks
4 *
5 * Copyright (C) 2015 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
9 * Andrew Lunn <andrew@lunn.ch>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/clk-provider.h>
16#include <linux/io.h>
17#include <linux/of.h>
18#include "common.h"
19
20/*
21 * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
22 *
23 * SARL[15]    : TCLK frequency
24 *		 0 = 250 MHz
25 *		 1 = 200 MHz
26 *
27 * SARH[0]     : Reference clock frequency
28 *               0 = 25 Mhz
29 *               1 = 40 Mhz
30 */
31
32#define SARL 					0
33#define  SARL_A390_TCLK_FREQ_OPT		15
34#define  SARL_A390_TCLK_FREQ_OPT_MASK		0x1
35#define  SARL_A390_CPU_DDR_L2_FREQ_OPT		10
36#define  SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK	0x1F
37#define SARH					4
38#define  SARH_A390_REFCLK_FREQ			BIT(0)
39
40static const u32 armada_39x_tclk_frequencies[] __initconst = {
41	250000000,
42	200000000,
43};
44
45static u32 __init armada_39x_get_tclk_freq(void __iomem *sar)
46{
47	u8 tclk_freq_select;
48
49	tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) &
50			    SARL_A390_TCLK_FREQ_OPT_MASK);
51	return armada_39x_tclk_frequencies[tclk_freq_select];
52}
53
54static const u32 armada_39x_cpu_frequencies[] __initconst = {
55	[0x0] = 666 * 1000 * 1000,
56	[0x2] = 800 * 1000 * 1000,
57	[0x3] = 800 * 1000 * 1000,
58	[0x4] = 1066 * 1000 * 1000,
59	[0x5] = 1066 * 1000 * 1000,
60	[0x6] = 1200 * 1000 * 1000,
61	[0x8] = 1332 * 1000 * 1000,
62	[0xB] = 1600 * 1000 * 1000,
63	[0xC] = 1600 * 1000 * 1000,
64	[0x12] = 1800 * 1000 * 1000,
65	[0x1E] = 1800 * 1000 * 1000,
66};
67
68static u32 __init armada_39x_get_cpu_freq(void __iomem *sar)
69{
70	u8 cpu_freq_select;
71
72	cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
73			   SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK);
74	if (cpu_freq_select >= ARRAY_SIZE(armada_39x_cpu_frequencies)) {
75		pr_err("Selected CPU frequency (%d) unsupported\n",
76			cpu_freq_select);
77		return 0;
78	}
79
80	return armada_39x_cpu_frequencies[cpu_freq_select];
81}
82
83enum { A390_CPU_TO_NBCLK, A390_CPU_TO_HCLK, A390_CPU_TO_DCLK };
84
85static const struct coreclk_ratio armada_39x_coreclk_ratios[] __initconst = {
86	{ .id = A390_CPU_TO_NBCLK, .name = "nbclk" },
87	{ .id = A390_CPU_TO_HCLK, .name = "hclk" },
88	{ .id = A390_CPU_TO_DCLK, .name = "dclk" },
89};
90
91static void __init armada_39x_get_clk_ratio(
92	void __iomem *sar, int id, int *mult, int *div)
93{
94	switch (id) {
95	case A390_CPU_TO_NBCLK:
96		*mult = 1;
97		*div = 2;
98		break;
99	case A390_CPU_TO_HCLK:
100		*mult = 1;
101		*div = 4;
102		break;
103	case A390_CPU_TO_DCLK:
104		*mult = 1;
105		*div = 2;
106		break;
107	}
108}
109
110static u32 __init armada_39x_refclk_ratio(void __iomem *sar)
111{
112	if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ)
113		return 40 * 1000 * 1000;
114	else
115		return 25 * 1000 * 1000;
116}
117
118static const struct coreclk_soc_desc armada_39x_coreclks = {
119	.get_tclk_freq = armada_39x_get_tclk_freq,
120	.get_cpu_freq = armada_39x_get_cpu_freq,
121	.get_clk_ratio = armada_39x_get_clk_ratio,
122	.get_refclk_freq = armada_39x_refclk_ratio,
123	.ratios = armada_39x_coreclk_ratios,
124	.num_ratios = ARRAY_SIZE(armada_39x_coreclk_ratios),
125};
126
127static void __init armada_39x_coreclk_init(struct device_node *np)
128{
129	mvebu_coreclk_setup(np, &armada_39x_coreclks);
130}
131CLK_OF_DECLARE(armada_39x_core_clk, "marvell,armada-390-core-clock",
132	       armada_39x_coreclk_init);
133
134/*
135 * Clock Gating Control
136 */
137static const struct clk_gating_soc_desc armada_39x_gating_desc[] __initconst = {
138	{ "pex1", NULL, 5 },
139	{ "pex2", NULL, 6 },
140	{ "pex3", NULL, 7 },
141	{ "pex0", NULL, 8 },
142	{ "usb3h0", NULL, 9 },
143	{ "usb3h1", NULL, 10 },
144	{ "sata0", NULL, 15 },
145	{ "sdio", NULL, 17 },
146	{ "xor0", NULL, 22 },
147	{ "xor1", NULL, 28 },
148	{ }
149};
150
151static void __init armada_39x_clk_gating_init(struct device_node *np)
152{
153	mvebu_clk_gating_setup(np, armada_39x_gating_desc);
154}
155CLK_OF_DECLARE(armada_39x_clk_gating, "marvell,armada-390-gating-clock",
156	       armada_39x_clk_gating_init);
157