Searched refs:dc (Results 176 - 200 of 549) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c30 #include "dc.h"
533 ctx->dc->caps.extended_aux_timeout_support);
748 if (pool->base.abm->ctx->dc->config.disable_dmcu)
767 bool dcn21_fast_validate_bw(struct dc *dc, argument
783 dcn20_merge_pipes_for_validate(dc, context);
786 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
819 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
821 for (i = 0, pipe_idx = 0; i < dc
926 dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate) argument
1383 dcn21_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dcn21_resource_pool *pool) argument
1697 dcn21_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_pg_cntl.c52 if (pg_cntl->ctx->dc->debug.ignore_pg)
85 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on)
86 pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc(
87 pg_cntl->ctx->dc->res_pool->dccg, dsc_inst);
89 if (pg_cntl->ctx->dc->debug.ignore_pg ||
90 pg_cntl->ctx->dc->debug.disable_dsc_power_gate ||
91 pg_cntl->ctx->dc->idle_optimizations_allowed)
148 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) {
150 pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc(
151 pg_cntl->ctx->dc
[all...]
H A DMakefile18 AMD_DAL_DCN35 = $(addprefix $(AMDDALPATH)/dc/dcn35/,$(DCN35))
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c28 #include "dc.h"
799 ctx->dc->caps.extended_aux_timeout_support);
1191 struct dc *dc = pool->base.oem_device->ctx->dc; local
1193 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1225 struct dc *dc = pipe_ctx->stream->ctx->dc; local
1226 struct dce_hwseq *hws = dc
1301 dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) argument
1316 dcn20_acquire_dsc(const struct dc *dc, struct resource_context *res_ctx, struct display_stream_compressor **dsc, int pipe_idx) argument
1367 dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream) argument
1401 remove_dsc_from_stream_resource(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
1424 dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
1444 dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
1469 dcn20_split_stream_for_odm( const struct dc *dc, struct resource_context *res_ctx, struct pipe_ctx *prev_odm_pipe, struct pipe_ctx *next_odm_pipe) argument
1613 dcn20_set_mcif_arb_params( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
1665 dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) argument
1700 dcn20_find_secondary_pipe(struct dc *dc, struct resource_context *res_ctx, const struct resource_pool *pool, const struct pipe_ctx *primary_pipe) argument
1778 dcn20_merge_pipes_for_validate( struct dc *dc, struct dc_state *context) argument
1837 dcn20_validate_apply_pipe_split_flags( struct dc *dc, struct dc_state *context, int vlevel, int *split, bool *merge) argument
2025 dcn20_fast_validate_bw( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *pipe_cnt_out, int *pipe_split_from, int *vlevel_out, bool fast_validate) argument
2147 dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate) argument
2192 dcn20_get_dcc_compression_cap(const struct dc *dc, const struct dc_dcc_surface_param *input, struct dc_surface_dcc_cap *output) argument
2356 init_soc_bounding_box(struct dc *dc, struct dcn20_resource_pool *pool) argument
2410 dcn20_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dcn20_resource_pool *pool) argument
2780 dcn20_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc) argument
[all...]
/linux-master/drivers/infiniband/hw/qib/
H A Dqib_diag.c80 struct qib_diag_client *dc; local
82 dc = client_pool;
83 if (dc)
85 client_pool = dc->next;
88 dc = kmalloc(sizeof(*dc), GFP_KERNEL);
90 if (dc) {
91 dc->next = NULL;
92 dc->dd = dd;
93 dc
102 return_client(struct qib_diag_client *dc) argument
185 struct qib_diag_client *dc; local
512 struct qib_diag_client *dc; local
762 struct qib_diag_client *dc = fp->private_data; local
836 struct qib_diag_client *dc = fp->private_data; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_link_enc_cfg.c29 #define DC_LOGGER dc->ctx->logger
40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) {
41 link_enc = stream->ctx->dc->res_pool->link_encoders[i];
51 stream->ctx->dc->link_srv->dp_decide_link_settings(stream, &link_settings);
67 static struct link_enc_assignment get_assignment(struct dc *dc, int i) argument
71 if (dc->current_state->res_ctx.link_enc_cfg_ctx.mode == LINK_ENC_CFG_TRANSIENT)
72 assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.transient_assignments[i];
74 assignment = dc->current_state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
159 stream->link_enc = stream->ctx->dc
259 clear_enc_assignments(const struct dc *dc, struct dc_state *state) argument
280 link_enc_cfg_init( const struct dc *dc, struct dc_state *state) argument
296 link_enc_cfg_link_encs_assign( struct dc *dc, struct dc_state *state, struct dc_stream_state *streams[], uint8_t stream_count) argument
458 link_enc_cfg_is_transmitter_mappable( struct dc *dc, struct link_encoder *link_enc) argument
472 link_enc_cfg_get_stream_using_link_enc( struct dc *dc, enum engine_id eng_id) argument
491 link_enc_cfg_get_link_using_link_enc( struct dc *dc, enum engine_id eng_id) argument
506 link_enc_cfg_get_link_enc_used_by_link( struct dc *dc, const struct dc_link *link) argument
530 link_enc_cfg_get_next_avail_link_enc(struct dc *dc) argument
558 link_enc_cfg_get_link_enc_used_by_stream( struct dc *dc, const struct dc_stream_state *stream) argument
589 link_enc_cfg_get_link_enc_used_by_stream_current( struct dc *dc, const struct dc_stream_state *stream) argument
614 link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link) argument
635 link_enc_cfg_validate(struct dc *dc, struct dc_state *state) argument
746 link_enc_cfg_set_transient_mode(struct dc *dc, struct dc_state *current_state, struct dc_state *new_state) argument
[all...]
H A Ddc_debug.c32 #include "dc.h"
40 dc->ctx->logger
45 if (dc->debug.surface_trace) \
50 if (dc->debug.timing_trace) \
55 if (dc->debug.clock_trace) \
60 struct dc *dc,
65 DC_LOGGER_INIT(dc->ctx->logger);
180 struct dc *dc,
59 pre_surface_trace( struct dc *dc, const struct dc_plane_state *const *plane_states, int surface_count) argument
179 update_surface_trace( struct dc *dc, const struct dc_surface_update *updates, int surface_count) argument
301 post_surface_trace(struct dc *dc) argument
309 context_timing_trace( struct dc *dc, struct resource_context *res_ctx) argument
346 context_clock_trace( struct dc *dc, struct dc_state *context) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c258 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
267 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
294 if (dc->dml.ip.writeback_max_hscl_taps > 1) {
334 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size);
365 void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) argument
370 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
373 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
374 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc
257 dcn30_fpu_populate_dml_writeback_from_context( struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) argument
379 dcn30_fpu_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
593 dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc) argument
639 dcn30_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params, struct dc_bounding_box_max_clk *dcn30_bb_max_clk, unsigned int *dcfclk_mhz, unsigned int *dram_speed_mts) argument
691 dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
791 patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/
H A Dclk_mgr.c53 struct dc *dc,
82 struct dc *dc,
100 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) argument
107 dc_get_edp_links(dc, edp_links, &edp_num);
108 if (dc->hwss.exit_optimized_pwr_state)
109 dc->hwss.exit_optimized_pwr_state(dc, d
52 clk_mgr_helper_get_active_display_cnt( struct dc *dc, struct dc_state *context) argument
81 clk_mgr_helper_get_active_plane_cnt( struct dc *dc, struct dc_state *context) argument
126 clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c27 #include "dc.h"
691 ctx->dc->caps.extended_aux_timeout_support);
1026 static bool dcn201_get_dcc_compression_cap(const struct dc *dc, argument
1030 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
1031 dc->res_pool->hubbub,
1036 static void dcn201_populate_dml_writeback_from_context(struct dc *dc, argument
1041 dcn201_populate_dml_writeback_from_context_fpu(dc, res_ctx, pipes);
1084 struct dc *d
1082 dcn201_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dcn201_resource_pool *pool) argument
1295 dcn201_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c183 static bool dcn32_apply_merge_split_flags_helper(struct dc *dc, struct dc_state *context,
189 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
190 double fclk_change_latency_us = clk_mgr->base.ctx->dc->dml.soc.fclk_change_latency_us;
191 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
192 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
197 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
235 if (clk_mgr->base.ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
275 int dcn32_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, argument
333 dcn32_helper_populate_phantom_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
466 dcn32_set_phantom_stream_timing(struct dc *dc, struct dc_state *context, struct pipe_ctx *ref_pipe, struct dc_stream_state *phantom_stream, display_e2e_pipe_params_st *pipes, unsigned int pipe_cnt, unsigned int dc_pipe_idx) argument
558 dcn32_get_num_free_pipes(struct dc *dc, struct dc_state *context) argument
599 dcn32_assign_subvp_pipe(struct dc *dc, struct dc_state *context, unsigned int *index) argument
678 dcn32_enough_pipes_for_subvp(struct dc *dc, struct dc_state *context) argument
724 subvp_subvp_schedulable(struct dc *dc, struct dc_state *context) argument
795 subvp_drr_schedulable(struct dc *dc, struct dc_state *context) argument
895 subvp_vblank_schedulable(struct dc *dc, struct dc_state *context) argument
982 subvp_subvp_admissable(struct dc *dc, struct dc_state *context) argument
1034 subvp_validate_static_schedulability(struct dc *dc, struct dc_state *context, int vlevel) argument
1090 assign_subvp_index(struct dc *dc, struct dc_state *context) argument
1192 update_pipe_slice_table_with_split_flags( struct pipe_slice_table *table, struct dc *dc, struct dc_state *context, struct vba_vars_st *vba, int split[MAX_PIPES], bool merge[MAX_PIPES]) argument
1261 update_pipes_with_slice_table(struct dc *dc, struct dc_state *context, struct pipe_slice_table *table) argument
1279 update_pipes_with_split_flags(struct dc *dc, struct dc_state *context, struct vba_vars_st *vba, int split[MAX_PIPES], bool merge[MAX_PIPES]) argument
1294 should_apply_odm_power_optimization(struct dc *dc, struct dc_state *context, struct vba_vars_st *v, int *split, bool *merge) argument
1387 try_odm_power_optimization_and_revalidate( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *split, bool *merge, unsigned int *vlevel, int pipe_cnt) argument
1431 dcn32_full_validate_bw_helper(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *vlevel, int *split, bool *merge, int *pipe_cnt, bool *repopulate_pipes) argument
1592 is_dtbclk_required(struct dc *dc, struct dc_state *context) argument
1637 dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
1801 dcn32_find_split_pipe( struct dc *dc, struct dc_state *context, int old_index) argument
1843 dcn32_split_stream_for_mpc_or_odm( const struct dc *dc, struct resource_context *res_ctx, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm) argument
1929 dcn32_apply_merge_split_flags_helper( struct dc *dc, struct dc_state *context, bool *repopulate_pipes, int *split, bool *merge) argument
2130 dcn32_internal_validate_bw(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *pipe_cnt_out, int *vlevel_out, bool fast_validate) argument
2292 dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
3030 dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) argument
3402 dcn32_allow_subvp_high_refresh_rate(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe) argument
3458 dcn32_determine_max_vratio_prefetch(struct dc *dc, struct dc_state *context) argument
3492 dcn32_assign_fpo_vactive_candidate(struct dc *dc, const struct dc_state *context, struct dc_stream_state **fpo_candidate_stream) argument
3528 dcn32_find_vactive_pipe(struct dc *dc, const struct dc_state *context, uint32_t vactive_margin_req_us) argument
3559 dcn32_override_min_req_memclk(struct dc *dc, struct dc_state *context) argument
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c28 #include "dc.h"
95 dc->ctx->logger
799 ctx->dc->caps.extended_aux_timeout_support);
1191 struct dc *dc = pool->base.oem_device->ctx->dc; local
1193 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1281 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
1284 return dcn20_add_stream_to_ctx(dc, new_ct
1320 dcn30_populate_dml_pipes_from_context( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) argument
1343 dcn30_populate_dml_writeback_from_context( struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) argument
1374 dcn30_set_mcif_arb_params( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
1490 is_soc_bounding_box_valid(struct dc *dc) argument
1500 init_soc_bounding_box(struct dc *dc, struct dcn30_resource_pool *pool) argument
1524 dcn30_split_stream_for_mpc_or_odm( const struct dc *dc, struct resource_context *res_ctx, struct pipe_ctx *pri_pipe, struct pipe_ctx *sec_pipe, bool odm) argument
1586 dcn30_find_split_pipe( struct dc *dc, struct dc_state *context, int old_index) argument
1628 dcn30_internal_validate_bw( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int *pipe_cnt_out, int *vlevel_out, bool fast_validate, bool allow_self_refresh_only) argument
1965 dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context) argument
2010 dcn30_setup_mclk_switch_using_fw_based_vblank_stretch(struct dc *dc, struct dc_state *context) argument
2020 dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) argument
2027 dcn30_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
2038 dcn30_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate) argument
2097 dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) argument
2266 dcn30_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dcn30_resource_pool *pool) argument
2611 dcn30_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc) argument
[all...]
/linux-master/drivers/gpu/drm/loongson/
H A Dloongson_device.c29 .dc = {
61 .dc = {
93 [CHIP_LS7A1000] = &ls7a1000_gfx.dc,
94 [CHIP_LS7A2000] = &ls7a2000_gfx.dc,
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_dsc.h64 bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
96 /* TODO - Hardware/specs limitation should be owned by dc dsc and returned to DM,
111 void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_options *options);
/linux-master/drivers/gpu/drm/amd/display/dc/link/
H A DMakefile29 AMD_DAL_LINK = $(addprefix $(AMDDALPATH)/dc/link/, \
38 AMD_DAL_LINK_ACCESSORIES = $(addprefix $(AMDDALPATH)/dc/link/accessories/, \
48 AMD_DAL_LINK_HWSS = $(addprefix $(AMDDALPATH)/dc/link/hwss/, \
61 AMD_DAL_LINK_PROTOCOLS = $(addprefix $(AMDDALPATH)/dc/link/protocols/, \
/linux-master/drivers/gpu/drm/amd/display/dc/basics/
H A DMakefile36 AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A DMakefile18 AMD_DAL_DCN31 = $(addprefix $(AMDDALPATH)/dc/dcn31/,$(DCN31))
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A DMakefile8 AMD_DAL_DCN201 = $(addprefix $(AMDDALPATH)/dc/dcn201/,$(DCN201))
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A DMakefile18 AMD_DAL_DCN32 = $(addprefix $(AMDDALPATH)/dc/dcn32/,$(DCN32))
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A DMakefile32 AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10))
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A DMakefile10 AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
/linux-master/drivers/staging/media/av7110/
H A Dav7110_hw.c1043 int av7110_osd_cmd(struct av7110 *av7110, osd_cmd_t *dc) argument
1050 switch (dc->cmd) {
1055 av7110->osdbpp[av7110->osdwin] = (dc->color - 1) & 7;
1058 dc->x1 - dc->x0 + 1, dc->y1 - dc->y0 + 1);
1061 if (!dc->data) {
1062 ret = MoveWindowAbs(av7110, av7110->osdwin, dc->x0, dc
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c63 dc->ctx->logger
709 ctx->dc->caps.extended_aux_timeout_support);
870 const struct dc *dc,
887 struct dc *dc,
898 dc->ctx,
899 dc->bw_dceip,
900 dc->bw_vbios,
902 dc
869 build_mapped_resource( const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) argument
886 dce112_validate_bandwidth( struct dc *dc, struct dc_state *context, bool fast_validate) argument
958 resource_map_phy_clock_resources( const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) argument
1013 dce112_add_stream_to_ctx( struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) argument
1032 dce112_validate_global( struct dc *dc, struct dc_state *context) argument
1062 bw_calcs_data_update_from_pplib(struct dc *dc) argument
1220 dce112_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dce110_resource_pool *pool) argument
1413 dce112_create_resource_pool( uint8_t num_virtual_links, struct dc *dc) argument
[all...]
/linux-master/drivers/md/bcache/
H A Drequest.c30 static unsigned int cache_mode(struct cached_dev *dc) argument
32 return BDEV_CACHE_MODE(&dc->sb);
35 static bool verify(struct cached_dev *dc) argument
37 return dc->verify;
358 static struct hlist_head *iohash(struct cached_dev *dc, uint64_t k) argument
360 return &dc->io_hash[hash_64(k, RECENT_IO_BITS)];
363 static bool check_should_bypass(struct cached_dev *dc, struct bio *bio) argument
365 struct cache_set *c = dc->disk.c;
366 unsigned int mode = cache_mode(dc);
371 if (test_bit(BCACHE_DEV_DETACHING, &dc
596 struct cached_dev *dc; local
657 struct cached_dev *dc = container_of(s->d, local
769 struct cached_dev *dc = container_of(s->d, struct cached_dev, disk); local
836 struct cached_dev *dc = container_of(s->d, struct cached_dev, disk); local
878 struct cached_dev *dc = container_of(s->d, struct cached_dev, disk); local
896 struct cached_dev *dc = container_of(s->d, struct cached_dev, disk); local
962 cached_dev_read(struct cached_dev *dc, struct search *s) argument
975 struct cached_dev *dc = container_of(s->d, struct cached_dev, disk); local
981 cached_dev_write(struct cached_dev *dc, struct search *s) argument
1100 struct cached_dev *dc = container_of(ddip->d, local
1114 struct cached_dev *dc = container_of(d, struct cached_dev, disk); local
1149 struct cached_dev *dc; local
1189 struct cached_dev *dc = container_of(d, struct cached_dev, disk); local
1248 struct cached_dev *dc = container_of(d, struct cached_dev, disk); local
1257 bch_cached_dev_request_init(struct cached_dev *dc) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c454 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) argument
458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
459 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
460 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
461 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
465 void dcn315_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) argument
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
474 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc
482 dcn31_calculate_wm_and_dlg_fp( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
590 dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) argument
668 dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) argument
729 dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) argument
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