Searched refs:controller (Results 451 - 475 of 629) sorted by relevance

<<11121314151617181920>>

/linux-master/drivers/usb/host/
H A Dohci-hcd.c16 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
56 /* For initializing controller (mask in an HCFS mode too) */
427 /* Software reset, after which the controller goes into SUSPEND */
521 ohci->hcca = dma_alloc_coherent(hcd->self.controller,
539 /* Start an OHCI controller, set the BUS operational
540 * resets USB and controller
570 device_set_wakeup_capable(hcd->self.controller, 1);
627 /* Tell the controller where the control and bulk lists are
658 /* start controller operations */
709 /* ohci_setup routine for generic controller initializatio
[all...]
H A Docteon-hcd.c931 * If the controller is getting port events right after the reset, it
932 * means the initialization failed. Try resetting the controller again
944 dev_info(dev, "controller reset failed (gintsts=0x%x) - retrying\n",
1353 struct device *dev = hcd->self.controller;
1965 struct device *dev = hcd->self.controller;
2598 struct device *dev = hcd->self.controller;
2932 * handler for the USB controller. It can also be called
3072 struct device *dev = hcd->self.controller;
3273 struct device *dev = hcd->self.controller;
3307 struct device *dev = hcd->self.controller;
[all...]
H A Duhci-hcd.h108 * the host controller implementation.
189 * subject to asynchronous updates by the controller.
276 * subject to asynchronous updates by the controller.
348 * The UHCI controller and root hub
381 * The full UHCI controller information:
449 /* Reset host controller */
470 #define uhci_dev(u) (uhci_to_hcd(u)->self.controller)
503 * Functions used to access controller registers. The UCHI spec says that host
504 * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts
683 * The GRLIB GRUSBHC controller ca
[all...]
/linux-master/drivers/spi/
H A Dspi-tegra114.c721 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
775 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
868 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
945 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
996 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
H A Dspi-tegra210-quad.c277 * Tegra QSPI controller supports packed or unpacked mode transfers.
812 struct tegra_qspi *tqspi = spi_controller_get_devdata(spi->controller);
873 struct tegra_qspi *tqspi = spi_controller_get_devdata(spi->controller);
928 struct tegra_qspi *tqspi = spi_controller_get_devdata(spi->controller);
944 struct tegra_qspi *tqspi = spi_controller_get_devdata(spi->controller);
1008 struct tegra_qspi *tqspi = spi_controller_get_devdata(spi->controller);
1151 /* Reset controller if timeout happens */
H A Dspi-amlogic-spifc-a1.c3 * Driver for Amlogic A1 SPI flash controller (SPIFC)
258 spi_controller_get_devdata(mem->spi->controller);
367 "failed to register spi controller\n");
H A Dspi-sifive.c5 // SiFive SPI controller driver (master mode only)
155 struct sifive_spi *spi = spi_controller_get_devdata(device->controller);
H A Dspi-mpc52xx.c7 * This is the driver for the MPC5200's dedicated SPI controller.
167 /* Setup the controller parameters */
178 /* Setup the controller speed */
222 /* The SPI controller is stoopid. At slower speeds, it may
370 struct mpc52xx_spi *ms = spi_controller_get_devdata(spi->controller);
/linux-master/drivers/mtd/nand/raw/
H A Dmeson_nand.c98 /* nand flash controller delay 3 ns */
164 struct nand_controller controller; member in struct:meson_nfc
332 * The Nand flash controller is designed as two stages pipleline -
335 * but the Nand flash controller still has two commands buffered,
1411 nand->controller = &nfc->controller;
1412 nand->controller->ops = &meson_nand_controller_ops;
1531 nand_controller_init(&nfc->controller);
H A Dmtk_nand.c3 * MTK NAND Flash controller driver.
21 /* NAND controller register definition */
143 struct nand_controller controller; member in struct:mtk_nfc
1249 * this controller only supports 512 and 1024 sizes
1386 nand->controller = &nfc->controller;
1502 nand_controller_init(&nfc->controller);
1504 nfc->controller.ops = &mtk_nfc_controller_ops;
H A Dgpio.c353 chip->controller = &gpiomtd->base;
H A Dams-delta.c356 /* Initialize the NAND controller object embedded in gpio_nand. */
359 this->controller = &priv->base;
/linux-master/drivers/bluetooth/
H A Dbtrtl.c958 if (coredump_info->rtl_dump.controller)
960 coredump_info->rtl_dump.controller);
1146 /* Ensure the above vendor command is sent to controller and
1219 coredump_info->rtl_dump.controller = btrtl_dev->ic_info->hw_info;
1274 /* Enable controller to do both LE scan and BR/EDR inquiry
1475 rtl_dev_dbg(hdev, "controller baudrate = %u", *controller_baudrate);
/linux-master/arch/mips/include/asm/
H A Dsgiarcs.h53 system, processor, cache, adapter, controller, peripheral, memory enumerator in enum:linux_devclass
/linux-master/drivers/scsi/isci/
H A Dport_config.c106 * @ihost: The controller object used for the port search.
149 * @ihost: This is the controller object that contains the port agent
150 * @port_agent: This is the port configuration agent for the controller.
377 * @ihost: This is the controller object that receives the link down
379 * @port_agent: This is the port configuration agent for the controller.
446 /* Get the assigned SAS Address for the first PHY on the controller. */
594 * @ihost: This is the controller object that receives the link up
596 * @port_agent: This is the port configuration agent for the controller.
626 * @ihost: This is the controller object that receives the link down
628 * @port_agent: This is the port configuration agent for the controller
[all...]
/linux-master/drivers/usb/common/
H A Dusb-otg-fsm.c134 dev_err(fsm->otg->host->controller,
191 * controller driver, otherwise, hnp polling is not started.
/linux-master/arch/powerpc/kernel/
H A Dpci_dn.c141 edev->controller = pdn->phb;
/linux-master/arch/arm/mach-tegra/
H A Dsleep-tegra20.S104 * puts the specified CPU in wait-for-event mode on the flow controller
119 str r2, [r3, r1] @ put flow controller in wait event mode
322 * uses flow controller to enter sleep state
/linux-master/drivers/usb/musb/
H A Dmusb_core.h323 struct device *controller; member in struct:musb
/linux-master/drivers/clk/baikal-t1/
H A Dclk-ccu-div.c19 #include <linux/reset-controller.h>
127 * the later is clocking the AXI-bus between DDR controller and the Main
439 pr_err("Couldn't register divider '%s' reset controller\n",
/linux-master/drivers/reset/
H A Dreset-imx7.c14 #include <linux/reset-controller.h>
H A Dreset-uniphier.c12 #include <linux/reset-controller.h>
/linux-master/drivers/soc/dove/
H A Dpmu.c14 #include <linux/reset-controller.h>
43 * SoC. Export this as a reset controller.
225 /* PMU IRQ controller */
357 * interrupt-controller;
432 * We parse the reset controller property directly here
433 * to ensure that we can operate when the reset controller
447 /* Loss of the interrupt controller is not a fatal error. */
/linux-master/drivers/watchdog/
H A Dmtk_wdt.c29 #include <linux/reset-controller.h>
219 "couldn't register wdt reset controller: %d\n", ret);
/linux-master/drivers/soc/mediatek/
H A Dmtk-mmsys.c13 #include <linux/reset-controller.h>
416 dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);

Completed in 435 milliseconds

<<11121314151617181920>>