Searched refs:clock (Results 551 - 575 of 1872) sorted by relevance

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/linux-master/drivers/media/platform/samsung/exynos4-is/
H A Dmedia-dev.c187 * and the sensor clock
199 /* Enable PXLASYNC clock if this pipeline includes FIMC-IS */
218 * of all pipeline subdevs and the sensor clock
252 * __fimc_pipeline_close - disable the sensor clock and pipeline power
255 * Disable power of all subdevs and turn the external sensor clock off.
273 /* Disable PXLASYNC clock if this pipeline includes FIMC-IS */
437 * the sensor's clock frequency is needed.
1067 if (IS_ERR(fmd->camclk[i].clock))
1069 clk_put(fmd->camclk[i].clock);
1070 fmd->camclk[i].clock
1086 struct clk *clock; local
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/linux-master/drivers/gpu/drm/vc4/
H A Dvc4_hdmi_phy.c179 phy_get_vco_freq(unsigned long long clock, u8 *vco_sel, u8 *vco_div) argument
181 unsigned long long vco_freq = clock;
187 vco_freq = clock * _vco_div * 10;
255 struct phy_lane_settings clock; member in struct:phy_settings
337 * If the pixel clock exceeds our max setting, try the max
350 return &settings->clock;
H A Dvc4_vec.c87 * 0x80000000 seems to be equivalent to the pixel clock
88 * (which itself is the VEC clock divided by 8).
90 * Reference values (with the default pixel clock of 13.5 MHz):
145 * Db center frequency for SECAM; the clock for this is the same as for
203 struct clk *clock; member in struct:vc4_vec
528 clk_disable_unprepare(vec->clock);
571 * We need to set the clock rate each time we enable the encoder
573 * clock, and both drivers are requesting different rates.
577 ret = clk_set_rate(vec->clock, 108000000);
579 DRM_ERROR("Failed to set clock rat
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/linux-master/fs/bcachefs/
H A Dsb-clean.c259 struct jset_entry_clock *clock = local
260 container_of(jset_entry_init(end, sizeof(*clock)),
263 clock->entry.type = BCH_JSET_ENTRY_clock;
264 clock->rw = i;
265 clock->time = cpu_to_le64(atomic64_read(&c->io_clock[i].now));
H A Dmovinggc.c15 #include "clock.h"
314 struct io_clock *clock = &c->io_clock[WRITE]; local
354 last = atomic64_read(&clock->now);
357 if (wait > clock->max_slop) {
362 bch2_kthread_io_clock_wait(clock, last + wait,
382 bch2_kthread_io_clock_wait(clock, last + (min_member_capacity >> 6),
/linux-master/arch/s390/kernel/
H A Dvtime.c119 u64 timer, clock, user, guest, system, hardirq, softirq; local
122 clock = S390_lowcore.last_update_clock;
125 " stckf %1" /* Store current tod clock value */
129 clock = S390_lowcore.last_update_clock - clock;
154 clock - user - guest - system - hardirq - softirq;
/linux-master/drivers/gpu/drm/nouveau/dispnv04/
H A Ddfp.c198 adjusted_mode->clock = nv_connector->native_mode->clock;
343 output_mode->clock > 165000)
351 nouveau_bios_parse_lvds_table(dev, output_mode->clock,
358 if (output_mode->clock > 165000)
458 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
460 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
541 LVDS_PANEL_ON, nv_encoder->mode.clock);
601 connector->native_mode->clock);
604 int clock local
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/linux-master/drivers/mmc/host/
H A Dowl-mmc.c106 u32 clock; member in struct:owl_mmc_host
398 /* Set RDELAY and WDELAY based on the clock */
417 dev_err(owl_host->dev, "SD clock rate not supported\n");
429 if (!ios->clock)
432 owl_host->clock = ios->clock;
433 owl_mmc_set_clk_rate(owl_host, ios->clock);
518 if (ios->clock != owl_host->clock)
590 dev_err(&pdev->dev, "No clock define
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H A Dsdhci-msm.c263 struct clk *bus_clk; /* SDHC bus voter clock */
341 * The SDHC requires internal clock frequency to be double the
342 * actual clock that will be set for DDR mode. The controller
343 * uses the faster clock(100/400MHz) for some of its parts and
344 * send the actual required clock (50/200MHz) to the card.
355 unsigned int clock)
367 desired_rate = clock * mult;
370 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
376 * Qualcomm clock drivers by default round clock _up
354 msm_set_clock_rate_for_bus_mode(struct sdhci_host *host, unsigned int clock) argument
1766 __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) argument
1785 sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) argument
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/linux-master/drivers/gpu/drm/panel/
H A Dpanel-ilitek-ili9322.c218 * @dclk_active_high: data/pixel clock active high, data will be clocked
537 .clock = 24535,
550 .clock = 27000,
564 .clock = 64000,
578 .clock = 24540,
591 .clock = 27000,
605 .clock = 24540,
619 .clock = 27000,
/linux-master/drivers/ptp/
H A Dptp_clock.c3 * PTP 1588 clock support
12 #include <linux/posix-clock.h>
85 /* posix clock implementation */
96 struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
99 pr_err("ptp: physical clock is free running\n");
108 struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
120 struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
125 pr_err("ptp: physical clock is free running\n");
246 /* Initialize a clock structure. */
258 ptp->clock
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H A Dptp_qoriq.c3 * PTP 1588 clock for Freescale QorIQ 1588 timer
143 ptp_clock_event(ptp_qoriq->clock, &event);
187 ptp_clock_event(ptp_qoriq->clock, &event);
199 * PTP clock operations
351 .name = "qoriq ptp clock",
367 * reference clock frequency
369 * @clk_src: reference clock frequency
371 * The nominal frequency is the desired clock frequency.
372 * It should be less than the reference clock frequency.
433 pr_err("error reference clock valu
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/linux-master/arch/powerpc/kernel/
H A Dtime.c11 * to make clock more stable (2.4.0-test5). The only thing
33 #include <linux/sched/clock.h>
112 * This always puts next_tb beyond now, so the clock event will never fire
631 * Scheduler clock - returns current time in nanosec units.
646 * Running clock - attempts to give a view of time passing for a virtualised
680 /* The cpu node should have timebase and clock frequency properties */
728 if (!get_freq("ibm,extended-clock-frequency", 2, &ppc_proc_freq) &&
729 !get_freq("clock-frequency", 1, &ppc_proc_freq)) {
779 /* Sanitize it in case real time clock is set below EPOCH */
795 struct clocksource *clock local
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/linux-master/drivers/gpu/drm/nouveau/
H A Dnouveau_dp.c545 unsigned int max_rate, mode_rate, ds_max_dotclock, clock = mode->clock; local
556 clock *= 2;
559 mode_rate = DIV_ROUND_UP(clock * bpp, 8);
564 if (ds_max_dotclock && clock > ds_max_dotclock)
567 if (clock < min_clock)
571 *out_clock = clock;
/linux-master/drivers/net/wireless/rsi/
H A Drsi_91x_sdio.c168 u32 clock, resp, i; local
199 host->ios.clock = host->f_min;
204 * This delay must be at least 74 clock sizes, or 1 ms, or the
302 /* Set clock */
304 clock = 50000000;
306 clock = card->cis.max_dtr;
308 if (clock > host->f_max)
309 clock = host->f_max;
311 host->ios.clock = clock;
341 u32 clock; local
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/linux-master/drivers/video/fbdev/via/
H A Dhw.c131 [5] divide memory address clock by 4
134 [2] divide scan line clock by 2
135 [3] divide memory address clock by 2
449 /* structure with function pointers to support clock control */
450 static struct via_clock clock; variable in typeref:struct:via_clock
1447 clock.set_primary_pll(config);
1449 clock.set_secondary_pll(config);
1452 via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */
1497 via_clock_init(&clock, chip_type);
1966 clock
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/linux-master/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c526 (cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp)
531 if (cdv_intel_dp_link_required(mode->clock, 24)
536 if (mode->clock < 10000)
581 /* The clock divider is based off the hrawclk,
885 adjusted_mode->clock = fixed_mode->clock;
897 int lane_count, clock; local
901 int refclock = mode->clock;
906 refclock = intel_dp->panel_fixed_mode->clock;
911 for (clock
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H A Doaktrail_hdmi.c172 new_crtc_htotal = (mode->crtc_htotal - 1) * 200 * 1000 / mode->clock;
284 struct oaktrail_hdmi_clock clock; local
308 oaktrail_hdmi_find_dpll(crtc, adjusted_mode->clock, refclk, &clock);
315 REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr));
316 REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1));
317 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN));
519 if (mode->clock > 165000)
521 if (mode->clock < 2000
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c602 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
610 /* clock - voltage dependency table is empty table */
616 if (dep_table->entries[i].clk >= clock) {
720 uint32_t clock, SMU_SclkSetting *sclk_setting)
731 sclk_setting->SclkFrequency = clock;
732 /* get the engine clock dividers for this clock value */
733 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);
752 if (clock > smu_data->range_table[i].trans_lower_frequency
753 && clock <
600 vegam_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, struct phm_ppt_v1_clock_voltage_dependency_table *dep_table, uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) argument
719 vegam_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t clock, SMU_SclkSetting *sclk_setting) argument
790 vegam_get_sleep_divider_id_from_clock(uint32_t clock, uint32_t clock_insr) argument
809 vegam_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU75_Discrete_GraphicsLevel *level) argument
963 vegam_calculate_mclk_params(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level) argument
981 vegam_populate_single_memory_level(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level) argument
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/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_atombios.c1120 rdev->clock.vco_freq =
1132 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1133 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1134 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1135 struct radeon_pll *spll = &rdev->clock.spll;
1136 struct radeon_pll *mpll = &rdev->clock.mpll;
1186 /* system clock */
1213 /* memory clock */
1240 rdev->clock.default_sclk =
1242 rdev->clock
1505 radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, struct radeon_atom_ss *ss, int id, u32 clock) argument
2837 radeon_atom_get_clock_dividers(struct radeon_device *rdev, u8 clock_type, u32 clock, bool strobe_mode, struct atom_clock_dividers *dividers) argument
2954 radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, u32 clock, bool strobe_mode, struct atom_mpll_param *mpll_param) argument
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/linux-master/drivers/hid/
H A Dhid-ft260.c41 * With a 100 kHz I2C clock, one 240 bytes read takes about 1/27 second,
170 __le16 clock; /* I2C bus clock in range 60-3400 KHz */ member in struct:ft260_get_i2c_status_report
203 __le16 clock; /* I2C bus clock in range 60-3400 KHz */ member in struct:ft260_set_i2c_speed_report
246 u16 clock; member in struct:ft260_device
333 dev->clock = le16_to_cpu(report.clock);
334 ft260_dbg("bus_status %#02x, clock %u\n", report.bus_status,
335 dev->clock);
926 FT260_I2CST_ATTR_SHOW(clock); variable
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/linux-master/drivers/net/dsa/microchip/
H A Dksz_ptp.c30 #define KSZ_PTP_INC_NS 40ULL /* HW clock is incremented every 40 ns (by 40) */
196 pin = ptp_find_pin(ptp_data->clock, PTP_PF_PEROUT, request->index);
280 ret = ptp_schedule_worker(ptp_data->clock, 0);
284 ptp_cancel_worker_sync(ptp_data->clock);
303 if (!ptp_data->clock)
320 ts->phc_index = ptp_clock_index(ptp_data->clock);
602 /* Copy current PTP clock into shadow registers and read */
692 /* Write to shadow registers and Load PTP clock */
953 ptp_data->clock = ptp_clock_register(&ptp_data->caps, dev->dev);
954 if (IS_ERR_OR_NULL(ptp_data->clock))
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/linux-master/sound/firewire/bebob/
H A Dbebob_maudio.c23 * and Ozonic. The single stream is OK for the other devices even if the clock
193 buf[6] = 0xff & clk_src; /* clock source */
279 "fail to initialize clock params: %d\n", err);
639 /* omit last 4 bytes because it's clock info. */
657 /* last 4 bytes are omitted because it's clock info. */
674 /* no clock info */
730 .clock = &special_clk_spec,
746 .clock = NULL,
758 .clock = NULL,
770 .clock
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/linux-master/drivers/gpu/drm/i2c/
H A Dch7006_mode.c111 .clock = f, \
179 for (mode = ch7006_modes; mode->mode.clock; mode++) {
188 mode->mode.clock != drm_mode->clock)
268 if (abs(freq - mode->mode.clock) <
269 abs(best_freq - mode->mode.clock)) {
/linux-master/drivers/net/can/peak_canfd/
H A Dpeak_pciefd_main.c56 #define PCIEFD_SYS_CTL_TS_RST 0x00000001 /* timestamp clock */
57 #define PCIEFD_SYS_CTL_CLK_EN 0x00000002 /* system clock */
634 /* CAN clock in RST mode */
637 /* read current clock value */
641 priv->ucan.can.clock.freq = 20 * 1000 * 1000;
644 priv->ucan.can.clock.freq = 24 * 1000 * 1000;
647 priv->ucan.can.clock.freq = 30 * 1000 * 1000;
650 priv->ucan.can.clock.freq = 40 * 1000 * 1000;
653 priv->ucan.can.clock.freq = 60 * 1000 * 1000;
661 priv->ucan.can.clock
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