| /linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_opp.c | 31 #define REG(reg) \ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_smu.c | 64 #define REG(reg_name) \ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_smu.c | 36 #define REG(reg_name) \ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr_smu_msg.c | 39 #define REG(reg_name) \ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 42 #define REG(reg) \ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_dio_link_encoder.c | 49 #define REG(reg)\ macro
|
| H A D | dcn32_dio_stream_encoder.c | 38 #define REG(reg)\ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn321/ |
| H A D | dcn321_dio_link_encoder.c | 47 #define REG(reg)\ macro
|
| /linux-master/drivers/pinctrl/cirrus/ |
| H A D | pinctrl-lochnagar.c | 52 #define LN_PIN_GPIO(REV, ID, NAME, REG, SHIFT, INVERT) \
54 .name = NAME, .type = LN_PTYPE_GPIO, .reg = LOCHNAGAR##REV##_##REG, \
68 #define LN1_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
69 LN_PIN_GPIO(1, ID, NAME, REG, SHIFT, INVERT)
77 #define LN2_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
78 LN_PIN_GPIO(2, ID, NAME, REG, SHIFT, INVERT)
|
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/ |
| H A D | dcn20_hwseq.c | 67 #define REG(reg)\ macro
317 if (REG(DOMAIN8_PG_CONFIG))
319 if (REG(DOMAIN10_PG_CONFIG))
327 if (REG(DOMAIN9_PG_CONFIG))
329 if (REG(DOMAIN11_PG_CONFIG))
336 if (REG(DOMAIN19_PG_CONFIG))
338 if (REG(DOMAIN20_PG_CONFIG))
340 if (REG(DOMAIN21_PG_CONFIG))
477 if (REG(DOMAIN16_PG_CONFIG) == 0)
552 if (REG(DOMAIN1_PG_CONFI
[all...] |
| /linux-master/sound/isa/wss/ |
| H A D | wss_lib.c | 181 wss_outb(chip, CS4231P(REG), value);
194 wss_outb(chip, CS4231P(REG), value);
212 return wss_inb(chip, CS4231P(REG));
220 wss_outb(chip, CS4231P(REG),
222 wss_outb(chip, CS4231P(REG), val);
233 wss_outb(chip, CS4231P(REG),
236 return wss_inb(chip, CS4231P(REG));
240 res = wss_inb(chip, CS4231P(REG));
|
| /linux-master/arch/sparc/kernel/ |
| H A D | prom_irqtrans.c | 103 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
106 ((unsigned long)(REG)))
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_link_encoder.c | 43 #define REG(reg)\ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_link_encoder.c | 61 #define REG(reg)\ macro
305 ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
446 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
498 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
|
| H A D | dmub_abm_lcd.c | 42 #define REG(reg) \ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_dio_stream_encoder.c | 39 #define REG(reg)\ macro
|
| H A D | dcn314_dccg.c | 36 #define REG(reg) \ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
| H A D | dcn35_dio_stream_encoder.c | 39 #define REG(reg)\ macro
|
| /linux-master/arch/powerpc/include/asm/ |
| H A D | reg.h | 1263 #define MTFSF_L(REG) \
1264 .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1266 #define MTFSF_L(REG) mtfsf 0xff, (REG)
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| H A D | dce_clk_mgr.c | 46 #define REG(reg) \ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn35/ |
| H A D | dcn35_optc.c | 37 #define REG(reg)\ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| H A D | dcn20_dpp.c | 41 #define REG(reg)\ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 44 #define REG(reg)\ macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_smu.c | 53 #define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) macro
|
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dwb.c | 33 #define REG(reg)\ macro
|