| /freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 148 /// Check if DstReg can be replaced with SrcReg depending on the register
150 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
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| H A D | CombinerHelper.h | 644 bool tryReassocBinOp(unsigned Opc, Register DstReg, Register Op0,
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| H A D | IRTranslator.h | 246 void getStackGuard(Register DstReg, MachineIRBuilder &MIRBuilder);
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| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveDebugVariables.cpp | 1037 Register DstReg = MI->getOperand(0).getReg(); local
1043 if (!DstReg.isVirtual())
1053 if (!LIS.hasInterval(DstReg))
1055 LiveInterval *DstLI = &LIS.getInterval(DstReg);
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| H A D | MachineVerifier.cpp | 1944 const Register DstReg = DstOp.getReg(); local
1946 LLT DstTy = MRI->getType(DstReg);
1964 TypeSize DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
1972 if (DstReg.isPhysical() && SrcTy.isValid()) {
1974 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
1986 if (SrcReg.isPhysical() && DstReg.isVirtual() && DstSize.isScalable() &&
1989 if (SrcReg.isVirtual() && DstReg.isPhysical() && SrcSize.isScalable() &&
2080 Register DstReg = MI->getOperand(0).getReg(); local
2081 if (DstReg.isPhysical())
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| H A D | InlineSpiller.cpp | 525 if (Register DstReg = isCopyOfBundle(MI, Reg, TII)) {
526 if (isSibling(DstReg)) {
527 LiveInterval &DstLI = LIS.getInterval(DstReg);
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| H A D | TargetInstrInfo.cpp | 787 Register DstReg = MI->getOperand(0).getReg(); local
795 if (MO.isKill() && TRI->regsOverlap(DstReg, MO.getReg()))
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| H A D | MachineScheduler.cpp | 2051 Register DstReg = DstOp.getReg(); local
2052 if (!DstReg.isVirtual() || DstOp.isDead())
2062 unsigned GlobalReg = DstReg;
2065 LocalReg = DstReg;
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.cpp | 1060 unsigned DstReg = MI->getOperand(0).getReg();
1061 if (any_of(MRI.use_nodbg_instructions(DstReg), IsCoalescerBarrier))
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | AMDGPUMCCodeEmitter.cpp | 586 auto DstReg = MI.getOperand(VDstMOIdx).getReg();
587 if (AMDGPU::isHi(DstReg, MRI))
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 1077 Register DstReg = DstSrcPair->Destination->getReg(); local
1097 if (DstReg != Reg)
5133 unsigned DstReg, SrcReg, DReg; local
5152 DstReg = MI.getOperand(0).getReg();
5160 MIB.addReg(DstReg, RegState::Define)
5171 DstReg = MI.getOperand(0).getReg();
5183 MIB.addReg(DstReg, RegState::Define)
5198 DstReg = MI.getOperand(0).getReg();
5201 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
5221 MIB.addReg(DstReg, RegStat
[all...] |
| H A D | ARMFastISel.cpp | 2145 Register DstReg = VA.getLocReg(); local
2148 if (!SrcRC->contains(DstReg))
2151 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
3066 Register DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC); local
3073 ResultReg).addReg(DstReg, getKillRegState(true));
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 2012 Register DstReg = I->getOperand(0).getReg();
2014 if (DstReg.isPhysical())
2016 if (TRI->isAGPR(*MRI, DstReg))
2018 MoveRegs.push_back(DstReg);
2019 for (const MachineInstr &U : MRI->use_nodbg_instructions(DstReg))
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| H A D | SIInstrInfo.h | 366 ArrayRef<MachineOperand> Cond, Register DstReg,
372 Register DstReg, ArrayRef<MachineOperand> Cond,
377 Register DstReg, ArrayRef<MachineOperand> Cond,
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| H A D | AMDGPUCallLowering.cpp | 400 void AMDGPUCallLowering::lowerParameterPtr(Register DstReg, MachineIRBuilder &B, argument
411 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg);
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1459 Register DstReg = MI.getOperand(0).getReg(); local
1462 BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)
1497 Register DstReg = MI.getOperand(0).getReg(); local
1537 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVModuleAnalysis.cpp | 1029 Register DstReg = I.getOperand(0).getReg();
1030 buildOpDecorate(DstReg, I, TII, SPIRV::Decoration::FPFastMathMode, {FMFlags});
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 1218 Register SrcReg, DstReg; local
1220 DstReg = MI.getOperand(1).getReg();
1222 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(DstReg);
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| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 513 Register SrcReg, DstReg;
516 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
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| /freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 554 Register DstReg = DstRegs.front(); local
555 B.buildPadVectorWithUndefElements(DstReg, SrcReg);
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FloatingPoint.cpp | 291 Register DstReg = MI.getOperand(0).getReg(); local
294 return X86::RFP80RegClass.contains(DstReg) ||
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| H A D | X86InstrInfo.cpp | 124 Register &SrcReg, Register &DstReg,
147 DstReg = MI.getOperand(0).getReg();
3995 Register DstReg, Register TrueReg,
4032 const DebugLoc &DL, Register DstReg,
4037 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
4041 BuildMI(MBB, I, DL, get(Opc), DstReg)
7398 Register DstReg = NewMI->getOperand(0).getReg();
7399 if (DstReg.isPhysical())
7400 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
10697 Register DstReg
123 isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const argument
[all...] |
| H A D | X86FastISel.cpp | 1269 Register DstReg = VA.getLocReg(); local
1272 if (!SrcRC->contains(DstReg))
1275 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
3172 Register DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC); local
3179 .addReg(DstReg, getKillRegState(true));
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 682 unsigned Size, unsigned DstReg,
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| /freebsd-current/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2193 Register DstReg; local
2195 DstReg = MI.getOperand(0).getReg();
2196 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
2278 BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII->get(VE::PHI), DstReg)
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