Searched refs:BitVector (Results 226 - 250 of 285) sorted by relevance

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/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRDFGraph.h908 BitVector ReservedRegs;
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegAllocPBQP.cpp34 #include "llvm/ADT/BitVector.h"
620 BitVector RegMaskOverlaps;
H A DEarlyIfConversion.cpp18 #include "llvm/ADT/BitVector.h"
131 BitVector ClobberedRegUnits;
H A DModuloSchedule.cpp1739 BitVector LS(Schedule.getNumStages(), true);
1740 BitVector AS(Schedule.getNumStages(), true);
H A DRDFGraph.cpp11 #include "llvm/ADT/BitVector.h"
1285 BitVector DoneDefs(TRI.getNumRegs());
1314 BitVector DoneClobbers(TRI.getNumRegs());
H A DMachineFunction.cpp16 #include "llvm/ADT/BitVector.h"
138 for (BitVector::size_type I = 0; I < Properties.size(); ++I) {
H A DMachineVerifier.cpp23 #include "llvm/ADT/BitVector.h"
129 BitVector regsReserved;
825 BitVector PR = MFI.getPristineRegs(*MF);
2757 // SmallVector, which is a lot cheaper compared to DenseSet or BitVector).
2782 BitVector Sparse;
/freebsd-current/contrib/llvm-project/clang/lib/CodeGen/
H A DCGStmt.cpp2355 const llvm::BitVector &ResultTypeRequiresCast,
2356 const llvm::BitVector &ResultRegIsFlagReg) {
2504 llvm::BitVector ResultTypeRequiresCast;
2505 llvm::BitVector ResultRegIsFlagReg;
/freebsd-current/contrib/llvm-project/clang/include/clang/Serialization/
H A DASTWriter.h460 llvm::BitVector IsSLocAffecting;
/freebsd-current/contrib/llvm-project/clang/lib/Tooling/DependencyScanning/
H A DModuleDepCollector.cpp39 llvm::BitVector SearchPathUsage(Entries.size());
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DomainReassignment.cpp18 #include "llvm/ADT/BitVector.h"
377 BitVector EnclosedEdges{8, false};
H A DX86FrameLowering.cpp559 void X86FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
588 BitVector GPRsToZero(TRI->getNumRegs());
3084 BitVector &SavedRegs,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp469 BitVector OtherUsedRegs;
H A DAMDGPULowerModuleLDSPass.cpp183 #include "llvm/ADT/BitVector.h"
1401 BitVector IsPaddingField;
H A DSIRegisterInfo.cpp383 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved,
563 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
564 BitVector Reserved(getNumRegs());
H A DR600InstrInfo.cpp1063 void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/LiveDebugValues/
H A DInstrRefBasedImpl.h1123 BitVector CalleeSavedRegs;
/freebsd-current/contrib/llvm-project/llvm/tools/llvm-lto/
H A Dllvm-lto.cpp270 BitVector CanBeHidden;
/freebsd-current/contrib/llvm-project/llvm/lib/Transforms/Coroutines/
H A DCoroFrame.cpp18 #include "llvm/ADT/BitVector.h"
96 BitVector Consumes;
97 BitVector Kills;
124 void dump(StringRef Label, BitVector const &BV) const;
208 BitVector const &BV) const {
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLoadStoreOpt.cpp942 BitVector LegalSizes(MaxStoreSizeToForm * 2);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp20 #include "llvm/ADT/BitVector.h"
354 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
355 BitVector Reserved(getNumRegs());
/freebsd-current/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopRerollPass.cpp14 #include "llvm/ADT/BitVector.h"
388 using UsesTy = MapVector<Instruction *, BitVector>;
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp940 void AArch64FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
954 BitVector GPRsToZero(TRI.getNumRegs());
955 BitVector FPRsToZero(TRI.getNumRegs());
3227 BitVector &SavedRegs,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp119 #include "llvm/ADT/BitVector.h"
2172 checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs) {
2263 BitVector &SavedRegs,
2815 BitVector &SavedRegs) const {
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp24 #include "llvm/ADT/BitVector.h"
1216 BitVector DeadDefs(Hexagon::NUM_TARGET_REGS);

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