Searched refs:XOR (Results 26 - 50 of 94) sorted by relevance

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/freebsd-9.3-release/contrib/gcc/
H A Dsched-vis.c179 case XOR:
H A Doptabs.c4815 then add 2**(N-1). Do the addition using XOR since this
5244 xor_optab = init_optab (XOR);
6020 case XOR:
6116 case XOR:
6169 && (code == PLUS || code == MINUS || code == XOR))
H A Dgenattrtab.c3179 case AND: case IOR: case XOR:
3241 case XOR:
H A Drtlanal.c3616 case XOR: case IOR:
4126 case IOR: case AND: case XOR:
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.h705 void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
H A DSelectionDAGDumper.cpp168 case ISD::XOR: return "xor";
H A DLegalizeIntegerTypes.cpp104 case ISD::XOR:
1147 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1414 // shift if x is zero. We can use XOR here because x is known to be smaller
1416 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
2541 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2542 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
H A DLegalizeVectorTypes.cpp114 case ISD::XOR:
575 case ISD::XOR:
1481 case ISD::XOR:
H A DLegalizeDAG.cpp2275 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
3005 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3369 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3371 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3959 case ISD::XOR: {
H A DSelectionDAG.cpp950 /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
956 return getNode(ISD::XOR, DL, VT, Val, NegOne);
1799 case ISD::XOR: {
2262 case ISD::XOR: // NOT is handled here.
2846 case ISD::XOR:
2920 case ISD::XOR:
3275 case ISD::XOR:
/freebsd-9.3-release/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.h52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds
293 INC, DEC, OR, XOR, AND, enumerator in enum:llvm::X86ISD::NodeType
/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp380 setOperationAction(ISD::XOR , VT, Promote);
381 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
446 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
1569 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
5041 DAG.getNode(ISD::XOR, dl, MVT::i32,
5047 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5292 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5683 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6452 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6454 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
[all...]
/freebsd-9.3-release/usr.bin/xlint/lint1/
H A Dcgram.y1482 $$ = build(XOR, $1, $3);
/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp820 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
822 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
824 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
1864 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1902 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
/freebsd-9.3-release/contrib/gcc/config/arm/
H A Darm.c1652 case XOR:
1666 IOR, AND, XOR, MINUS;
1849 case XOR:
2087 case XOR:
2088 /* If we have IOR or XOR, and the constant can be loaded in a
2113 if (code == XOR)
4365 case XOR:
4509 case AND: case XOR: case IOR:
4751 case AND: case XOR: case IOR:
6804 || GET_CODE (x) == XOR || GET_COD
[all...]
/freebsd-9.3-release/contrib/gcc/config/s390/
H A Ds390.c1252 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
2131 case XOR:
3854 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
3926 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4263 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4296 case XOR:
4301 new = expand_simple_binop (SImode, XOR, new, ac.modemask,
/freebsd-9.3-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp174 setOperationAction(ISD::XOR, VT, Expand);
/freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp280 // Try to use RISBG or Opcode to implement OR or XOR node N.
1044 case ISD::XOR:
/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h557 /// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
1002 case ISD::XOR:
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1271 case Xor: return ISD::XOR;
/freebsd-9.3-release/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp979 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
/freebsd-9.3-release/contrib/gcc/config/rs6000/
H A Drs6000.c10630 else if (code == XOR)
12284 case XOR:
12337 /* Depending on the value of 'op', the XOR or the operation might
18815 || ((outer_code == IOR || outer_code == XOR)
18854 || outer_code == XOR)
18866 if ((outer_code == IOR || outer_code == XOR)
18877 || outer_code == XOR)
19015 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
19024 case XOR:
/freebsd-9.3-release/contrib/gcc/config/mips/
H A Dmips.c2518 if ((outer_code) == XOR
2610 case XOR:
3132 mips_emit_binary (XOR, target, inv_target, const1_rtx);
/freebsd-9.3-release/contrib/gcc/config/sparc/
H A Dsparc.c1378 /* If we are XOR'ing with -1, then we should emit a one's complement
1807 /* NOTE: The trailing bits get XOR'd so we need the
1833 /* If we are XOR'ing with -1, then we should emit a one's complement
6807 case XOR: fputs ("xor", file); break;
6817 case XOR: fputs ("xnor", file); break;
7497 case XOR:
/freebsd-9.3-release/contrib/nvi/build/
H A Dconfigure1873 #define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
1875 if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);

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