1/* Subroutines for insn-output.c for SPARC. 2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 4 Free Software Foundation, Inc. 5 Contributed by Michael Tiemann (tiemann@cygnus.com) 6 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 7 at Cygnus Support. 8 9This file is part of GCC. 10 11GCC is free software; you can redistribute it and/or modify 12it under the terms of the GNU General Public License as published by 13the Free Software Foundation; either version 2, or (at your option) 14any later version. 15 16GCC is distributed in the hope that it will be useful, 17but WITHOUT ANY WARRANTY; without even the implied warranty of 18MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19GNU General Public License for more details. 20 21You should have received a copy of the GNU General Public License 22along with GCC; see the file COPYING. If not, write to 23the Free Software Foundation, 51 Franklin Street, Fifth Floor, 24Boston, MA 02110-1301, USA. */ 25 26#include "config.h" 27#include "system.h" 28#include "coretypes.h" 29#include "tm.h" 30#include "tree.h" 31#include "rtl.h" 32#include "regs.h" 33#include "hard-reg-set.h" 34#include "real.h" 35#include "insn-config.h" 36#include "insn-codes.h" 37#include "conditions.h" 38#include "output.h" 39#include "insn-attr.h" 40#include "flags.h" 41#include "function.h" 42#include "expr.h" 43#include "optabs.h" 44#include "recog.h" 45#include "toplev.h" 46#include "ggc.h" 47#include "tm_p.h" 48#include "debug.h" 49#include "target.h" 50#include "target-def.h" 51#include "cfglayout.h" 52#include "tree-gimple.h" 53#include "langhooks.h" 54 55/* Processor costs */ 56static const 57struct processor_costs cypress_costs = { 58 COSTS_N_INSNS (2), /* int load */ 59 COSTS_N_INSNS (2), /* int signed load */ 60 COSTS_N_INSNS (2), /* int zeroed load */ 61 COSTS_N_INSNS (2), /* float load */ 62 COSTS_N_INSNS (5), /* fmov, fneg, fabs */ 63 COSTS_N_INSNS (5), /* fadd, fsub */ 64 COSTS_N_INSNS (1), /* fcmp */ 65 COSTS_N_INSNS (1), /* fmov, fmovr */ 66 COSTS_N_INSNS (7), /* fmul */ 67 COSTS_N_INSNS (37), /* fdivs */ 68 COSTS_N_INSNS (37), /* fdivd */ 69 COSTS_N_INSNS (63), /* fsqrts */ 70 COSTS_N_INSNS (63), /* fsqrtd */ 71 COSTS_N_INSNS (1), /* imul */ 72 COSTS_N_INSNS (1), /* imulX */ 73 0, /* imul bit factor */ 74 COSTS_N_INSNS (1), /* idiv */ 75 COSTS_N_INSNS (1), /* idivX */ 76 COSTS_N_INSNS (1), /* movcc/movr */ 77 0, /* shift penalty */ 78}; 79 80static const 81struct processor_costs supersparc_costs = { 82 COSTS_N_INSNS (1), /* int load */ 83 COSTS_N_INSNS (1), /* int signed load */ 84 COSTS_N_INSNS (1), /* int zeroed load */ 85 COSTS_N_INSNS (0), /* float load */ 86 COSTS_N_INSNS (3), /* fmov, fneg, fabs */ 87 COSTS_N_INSNS (3), /* fadd, fsub */ 88 COSTS_N_INSNS (3), /* fcmp */ 89 COSTS_N_INSNS (1), /* fmov, fmovr */ 90 COSTS_N_INSNS (3), /* fmul */ 91 COSTS_N_INSNS (6), /* fdivs */ 92 COSTS_N_INSNS (9), /* fdivd */ 93 COSTS_N_INSNS (12), /* fsqrts */ 94 COSTS_N_INSNS (12), /* fsqrtd */ 95 COSTS_N_INSNS (4), /* imul */ 96 COSTS_N_INSNS (4), /* imulX */ 97 0, /* imul bit factor */ 98 COSTS_N_INSNS (4), /* idiv */ 99 COSTS_N_INSNS (4), /* idivX */ 100 COSTS_N_INSNS (1), /* movcc/movr */ 101 1, /* shift penalty */ 102}; 103 104static const 105struct processor_costs hypersparc_costs = { 106 COSTS_N_INSNS (1), /* int load */ 107 COSTS_N_INSNS (1), /* int signed load */ 108 COSTS_N_INSNS (1), /* int zeroed load */ 109 COSTS_N_INSNS (1), /* float load */ 110 COSTS_N_INSNS (1), /* fmov, fneg, fabs */ 111 COSTS_N_INSNS (1), /* fadd, fsub */ 112 COSTS_N_INSNS (1), /* fcmp */ 113 COSTS_N_INSNS (1), /* fmov, fmovr */ 114 COSTS_N_INSNS (1), /* fmul */ 115 COSTS_N_INSNS (8), /* fdivs */ 116 COSTS_N_INSNS (12), /* fdivd */ 117 COSTS_N_INSNS (17), /* fsqrts */ 118 COSTS_N_INSNS (17), /* fsqrtd */ 119 COSTS_N_INSNS (17), /* imul */ 120 COSTS_N_INSNS (17), /* imulX */ 121 0, /* imul bit factor */ 122 COSTS_N_INSNS (17), /* idiv */ 123 COSTS_N_INSNS (17), /* idivX */ 124 COSTS_N_INSNS (1), /* movcc/movr */ 125 0, /* shift penalty */ 126}; 127 128static const 129struct processor_costs sparclet_costs = { 130 COSTS_N_INSNS (3), /* int load */ 131 COSTS_N_INSNS (3), /* int signed load */ 132 COSTS_N_INSNS (1), /* int zeroed load */ 133 COSTS_N_INSNS (1), /* float load */ 134 COSTS_N_INSNS (1), /* fmov, fneg, fabs */ 135 COSTS_N_INSNS (1), /* fadd, fsub */ 136 COSTS_N_INSNS (1), /* fcmp */ 137 COSTS_N_INSNS (1), /* fmov, fmovr */ 138 COSTS_N_INSNS (1), /* fmul */ 139 COSTS_N_INSNS (1), /* fdivs */ 140 COSTS_N_INSNS (1), /* fdivd */ 141 COSTS_N_INSNS (1), /* fsqrts */ 142 COSTS_N_INSNS (1), /* fsqrtd */ 143 COSTS_N_INSNS (5), /* imul */ 144 COSTS_N_INSNS (5), /* imulX */ 145 0, /* imul bit factor */ 146 COSTS_N_INSNS (5), /* idiv */ 147 COSTS_N_INSNS (5), /* idivX */ 148 COSTS_N_INSNS (1), /* movcc/movr */ 149 0, /* shift penalty */ 150}; 151 152static const 153struct processor_costs ultrasparc_costs = { 154 COSTS_N_INSNS (2), /* int load */ 155 COSTS_N_INSNS (3), /* int signed load */ 156 COSTS_N_INSNS (2), /* int zeroed load */ 157 COSTS_N_INSNS (2), /* float load */ 158 COSTS_N_INSNS (1), /* fmov, fneg, fabs */ 159 COSTS_N_INSNS (4), /* fadd, fsub */ 160 COSTS_N_INSNS (1), /* fcmp */ 161 COSTS_N_INSNS (2), /* fmov, fmovr */ 162 COSTS_N_INSNS (4), /* fmul */ 163 COSTS_N_INSNS (13), /* fdivs */ 164 COSTS_N_INSNS (23), /* fdivd */ 165 COSTS_N_INSNS (13), /* fsqrts */ 166 COSTS_N_INSNS (23), /* fsqrtd */ 167 COSTS_N_INSNS (4), /* imul */ 168 COSTS_N_INSNS (4), /* imulX */ 169 2, /* imul bit factor */ 170 COSTS_N_INSNS (37), /* idiv */ 171 COSTS_N_INSNS (68), /* idivX */ 172 COSTS_N_INSNS (2), /* movcc/movr */ 173 2, /* shift penalty */ 174}; 175 176static const 177struct processor_costs ultrasparc3_costs = { 178 COSTS_N_INSNS (2), /* int load */ 179 COSTS_N_INSNS (3), /* int signed load */ 180 COSTS_N_INSNS (3), /* int zeroed load */ 181 COSTS_N_INSNS (2), /* float load */ 182 COSTS_N_INSNS (3), /* fmov, fneg, fabs */ 183 COSTS_N_INSNS (4), /* fadd, fsub */ 184 COSTS_N_INSNS (5), /* fcmp */ 185 COSTS_N_INSNS (3), /* fmov, fmovr */ 186 COSTS_N_INSNS (4), /* fmul */ 187 COSTS_N_INSNS (17), /* fdivs */ 188 COSTS_N_INSNS (20), /* fdivd */ 189 COSTS_N_INSNS (20), /* fsqrts */ 190 COSTS_N_INSNS (29), /* fsqrtd */ 191 COSTS_N_INSNS (6), /* imul */ 192 COSTS_N_INSNS (6), /* imulX */ 193 0, /* imul bit factor */ 194 COSTS_N_INSNS (40), /* idiv */ 195 COSTS_N_INSNS (71), /* idivX */ 196 COSTS_N_INSNS (2), /* movcc/movr */ 197 0, /* shift penalty */ 198}; 199 200static const 201struct processor_costs niagara_costs = { 202 COSTS_N_INSNS (3), /* int load */ 203 COSTS_N_INSNS (3), /* int signed load */ 204 COSTS_N_INSNS (3), /* int zeroed load */ 205 COSTS_N_INSNS (9), /* float load */ 206 COSTS_N_INSNS (8), /* fmov, fneg, fabs */ 207 COSTS_N_INSNS (8), /* fadd, fsub */ 208 COSTS_N_INSNS (26), /* fcmp */ 209 COSTS_N_INSNS (8), /* fmov, fmovr */ 210 COSTS_N_INSNS (29), /* fmul */ 211 COSTS_N_INSNS (54), /* fdivs */ 212 COSTS_N_INSNS (83), /* fdivd */ 213 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */ 214 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */ 215 COSTS_N_INSNS (11), /* imul */ 216 COSTS_N_INSNS (11), /* imulX */ 217 0, /* imul bit factor */ 218 COSTS_N_INSNS (72), /* idiv */ 219 COSTS_N_INSNS (72), /* idivX */ 220 COSTS_N_INSNS (1), /* movcc/movr */ 221 0, /* shift penalty */ 222}; 223 224const struct processor_costs *sparc_costs = &cypress_costs; 225 226#ifdef HAVE_AS_RELAX_OPTION 227/* If 'as' and 'ld' are relaxing tail call insns into branch always, use 228 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized. 229 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if 230 somebody does not branch between the sethi and jmp. */ 231#define LEAF_SIBCALL_SLOT_RESERVED_P 1 232#else 233#define LEAF_SIBCALL_SLOT_RESERVED_P \ 234 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic) 235#endif 236 237/* Global variables for machine-dependent things. */ 238 239/* Size of frame. Need to know this to emit return insns from leaf procedures. 240 ACTUAL_FSIZE is set by sparc_compute_frame_size() which is called during the 241 reload pass. This is important as the value is later used for scheduling 242 (to see what can go in a delay slot). 243 APPARENT_FSIZE is the size of the stack less the register save area and less 244 the outgoing argument area. It is used when saving call preserved regs. */ 245static HOST_WIDE_INT apparent_fsize; 246static HOST_WIDE_INT actual_fsize; 247 248/* Number of live general or floating point registers needed to be 249 saved (as 4-byte quantities). */ 250static int num_gfregs; 251 252/* The alias set for prologue/epilogue register save/restore. */ 253static GTY(()) int sparc_sr_alias_set; 254 255/* The alias set for the structure return value. */ 256static GTY(()) int struct_value_alias_set; 257 258/* Save the operands last given to a compare for use when we 259 generate a scc or bcc insn. */ 260rtx sparc_compare_op0, sparc_compare_op1, sparc_compare_emitted; 261 262/* Vector to say how input registers are mapped to output registers. 263 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to 264 eliminate it. You must use -fomit-frame-pointer to get that. */ 265char leaf_reg_remap[] = 266{ 0, 1, 2, 3, 4, 5, 6, 7, 267 -1, -1, -1, -1, -1, -1, 14, -1, 268 -1, -1, -1, -1, -1, -1, -1, -1, 269 8, 9, 10, 11, 12, 13, -1, 15, 270 271 32, 33, 34, 35, 36, 37, 38, 39, 272 40, 41, 42, 43, 44, 45, 46, 47, 273 48, 49, 50, 51, 52, 53, 54, 55, 274 56, 57, 58, 59, 60, 61, 62, 63, 275 64, 65, 66, 67, 68, 69, 70, 71, 276 72, 73, 74, 75, 76, 77, 78, 79, 277 80, 81, 82, 83, 84, 85, 86, 87, 278 88, 89, 90, 91, 92, 93, 94, 95, 279 96, 97, 98, 99, 100}; 280 281/* Vector, indexed by hard register number, which contains 1 282 for a register that is allowable in a candidate for leaf 283 function treatment. */ 284char sparc_leaf_regs[] = 285{ 1, 1, 1, 1, 1, 1, 1, 1, 286 0, 0, 0, 0, 0, 0, 1, 0, 287 0, 0, 0, 0, 0, 0, 0, 0, 288 1, 1, 1, 1, 1, 1, 0, 1, 289 1, 1, 1, 1, 1, 1, 1, 1, 290 1, 1, 1, 1, 1, 1, 1, 1, 291 1, 1, 1, 1, 1, 1, 1, 1, 292 1, 1, 1, 1, 1, 1, 1, 1, 293 1, 1, 1, 1, 1, 1, 1, 1, 294 1, 1, 1, 1, 1, 1, 1, 1, 295 1, 1, 1, 1, 1, 1, 1, 1, 296 1, 1, 1, 1, 1, 1, 1, 1, 297 1, 1, 1, 1, 1}; 298 299struct machine_function GTY(()) 300{ 301 /* Some local-dynamic TLS symbol name. */ 302 const char *some_ld_name; 303 304 /* True if the current function is leaf and uses only leaf regs, 305 so that the SPARC leaf function optimization can be applied. 306 Private version of current_function_uses_only_leaf_regs, see 307 sparc_expand_prologue for the rationale. */ 308 int leaf_function_p; 309 310 /* True if the data calculated by sparc_expand_prologue are valid. */ 311 bool prologue_data_valid_p; 312}; 313 314#define sparc_leaf_function_p cfun->machine->leaf_function_p 315#define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p 316 317/* Register we pretend to think the frame pointer is allocated to. 318 Normally, this is %fp, but if we are in a leaf procedure, this 319 is %sp+"something". We record "something" separately as it may 320 be too big for reg+constant addressing. */ 321static rtx frame_base_reg; 322static HOST_WIDE_INT frame_base_offset; 323 324/* 1 if the next opcode is to be specially indented. */ 325int sparc_indent_opcode = 0; 326 327static bool sparc_handle_option (size_t, const char *, int); 328static void sparc_init_modes (void); 329static void scan_record_type (tree, int *, int *, int *); 330static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode, 331 tree, int, int, int *, int *); 332 333static int supersparc_adjust_cost (rtx, rtx, rtx, int); 334static int hypersparc_adjust_cost (rtx, rtx, rtx, int); 335 336static void sparc_output_addr_vec (rtx); 337static void sparc_output_addr_diff_vec (rtx); 338static void sparc_output_deferred_case_vectors (void); 339static rtx sparc_builtin_saveregs (void); 340static int epilogue_renumber (rtx *, int); 341static bool sparc_assemble_integer (rtx, unsigned int, int); 342static int set_extends (rtx); 343static void emit_pic_helper (void); 344static void load_pic_register (bool); 345static int save_or_restore_regs (int, int, rtx, int, int); 346static void emit_save_or_restore_regs (int); 347static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT); 348static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT); 349#ifdef OBJECT_FORMAT_ELF 350static void sparc_elf_asm_named_section (const char *, unsigned int, tree); 351#endif 352 353static int sparc_adjust_cost (rtx, rtx, rtx, int); 354static int sparc_issue_rate (void); 355static void sparc_sched_init (FILE *, int, int); 356static int sparc_use_sched_lookahead (void); 357 358static void emit_soft_tfmode_libcall (const char *, int, rtx *); 359static void emit_soft_tfmode_binop (enum rtx_code, rtx *); 360static void emit_soft_tfmode_unop (enum rtx_code, rtx *); 361static void emit_soft_tfmode_cvt (enum rtx_code, rtx *); 362static void emit_hard_tfmode_operation (enum rtx_code, rtx *); 363 364static bool sparc_function_ok_for_sibcall (tree, tree); 365static void sparc_init_libfuncs (void); 366static void sparc_init_builtins (void); 367static void sparc_vis_init_builtins (void); 368static rtx sparc_expand_builtin (tree, rtx, rtx, enum machine_mode, int); 369static tree sparc_fold_builtin (tree, tree, bool); 370static int sparc_vis_mul8x16 (int, int); 371static tree sparc_handle_vis_mul8x16 (int, tree, tree, tree); 372static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, 373 HOST_WIDE_INT, tree); 374static bool sparc_can_output_mi_thunk (tree, HOST_WIDE_INT, 375 HOST_WIDE_INT, tree); 376static struct machine_function * sparc_init_machine_status (void); 377static bool sparc_cannot_force_const_mem (rtx); 378static rtx sparc_tls_get_addr (void); 379static rtx sparc_tls_got (void); 380static const char *get_some_local_dynamic_name (void); 381static int get_some_local_dynamic_name_1 (rtx *, void *); 382static bool sparc_rtx_costs (rtx, int, int, int *); 383static bool sparc_promote_prototypes (tree); 384static rtx sparc_struct_value_rtx (tree, int); 385static bool sparc_return_in_memory (tree, tree); 386static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *); 387static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *); 388static bool sparc_vector_mode_supported_p (enum machine_mode); 389static bool sparc_pass_by_reference (CUMULATIVE_ARGS *, 390 enum machine_mode, tree, bool); 391static int sparc_arg_partial_bytes (CUMULATIVE_ARGS *, 392 enum machine_mode, tree, bool); 393static void sparc_dwarf_handle_frame_unspec (const char *, rtx, int); 394static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; 395static void sparc_file_end (void); 396#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING 397static const char *sparc_mangle_fundamental_type (tree); 398#endif 399#ifdef SUBTARGET_ATTRIBUTE_TABLE 400const struct attribute_spec sparc_attribute_table[]; 401#endif 402 403/* Option handling. */ 404 405/* Parsed value. */ 406enum cmodel sparc_cmodel; 407 408char sparc_hard_reg_printed[8]; 409 410struct sparc_cpu_select sparc_select[] = 411{ 412 /* switch name, tune arch */ 413 { (char *)0, "default", 1, 1 }, 414 { (char *)0, "-mcpu=", 1, 1 }, 415 { (char *)0, "-mtune=", 1, 0 }, 416 { 0, 0, 0, 0 } 417}; 418 419/* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */ 420enum processor_type sparc_cpu; 421 422/* Whether an FPU option was specified. */ 423static bool fpu_option_set = false; 424 425/* Initialize the GCC target structure. */ 426 427/* The sparc default is to use .half rather than .short for aligned 428 HI objects. Use .word instead of .long on non-ELF systems. */ 429#undef TARGET_ASM_ALIGNED_HI_OP 430#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 431#ifndef OBJECT_FORMAT_ELF 432#undef TARGET_ASM_ALIGNED_SI_OP 433#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 434#endif 435 436#undef TARGET_ASM_UNALIGNED_HI_OP 437#define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" 438#undef TARGET_ASM_UNALIGNED_SI_OP 439#define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" 440#undef TARGET_ASM_UNALIGNED_DI_OP 441#define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" 442 443/* The target hook has to handle DI-mode values. */ 444#undef TARGET_ASM_INTEGER 445#define TARGET_ASM_INTEGER sparc_assemble_integer 446 447#undef TARGET_ASM_FUNCTION_PROLOGUE 448#define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue 449#undef TARGET_ASM_FUNCTION_EPILOGUE 450#define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue 451 452#undef TARGET_SCHED_ADJUST_COST 453#define TARGET_SCHED_ADJUST_COST sparc_adjust_cost 454#undef TARGET_SCHED_ISSUE_RATE 455#define TARGET_SCHED_ISSUE_RATE sparc_issue_rate 456#undef TARGET_SCHED_INIT 457#define TARGET_SCHED_INIT sparc_sched_init 458#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD 459#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead 460 461#undef TARGET_FUNCTION_OK_FOR_SIBCALL 462#define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall 463 464#undef TARGET_INIT_LIBFUNCS 465#define TARGET_INIT_LIBFUNCS sparc_init_libfuncs 466#undef TARGET_INIT_BUILTINS 467#define TARGET_INIT_BUILTINS sparc_init_builtins 468 469#undef TARGET_EXPAND_BUILTIN 470#define TARGET_EXPAND_BUILTIN sparc_expand_builtin 471#undef TARGET_FOLD_BUILTIN 472#define TARGET_FOLD_BUILTIN sparc_fold_builtin 473 474#if TARGET_TLS 475#undef TARGET_HAVE_TLS 476#define TARGET_HAVE_TLS true 477#endif 478 479#undef TARGET_CANNOT_FORCE_CONST_MEM 480#define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem 481 482#undef TARGET_ASM_OUTPUT_MI_THUNK 483#define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk 484#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 485#define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk 486 487#undef TARGET_RTX_COSTS 488#define TARGET_RTX_COSTS sparc_rtx_costs 489#undef TARGET_ADDRESS_COST 490#define TARGET_ADDRESS_COST hook_int_rtx_0 491 492/* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a 493 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime 494 test for this value. */ 495#undef TARGET_PROMOTE_FUNCTION_ARGS 496#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true 497 498/* This is only needed for TARGET_ARCH64, but since PROMOTE_FUNCTION_MODE is a 499 no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime 500 test for this value. */ 501#undef TARGET_PROMOTE_FUNCTION_RETURN 502#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true 503 504#undef TARGET_PROMOTE_PROTOTYPES 505#define TARGET_PROMOTE_PROTOTYPES sparc_promote_prototypes 506 507#undef TARGET_STRUCT_VALUE_RTX 508#define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx 509#undef TARGET_RETURN_IN_MEMORY 510#define TARGET_RETURN_IN_MEMORY sparc_return_in_memory 511#undef TARGET_MUST_PASS_IN_STACK 512#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size 513#undef TARGET_PASS_BY_REFERENCE 514#define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference 515#undef TARGET_ARG_PARTIAL_BYTES 516#define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes 517 518#undef TARGET_EXPAND_BUILTIN_SAVEREGS 519#define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs 520#undef TARGET_STRICT_ARGUMENT_NAMING 521#define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming 522 523#undef TARGET_GIMPLIFY_VA_ARG_EXPR 524#define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg 525 526#undef TARGET_VECTOR_MODE_SUPPORTED_P 527#define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p 528 529#undef TARGET_DWARF_HANDLE_FRAME_UNSPEC 530#define TARGET_DWARF_HANDLE_FRAME_UNSPEC sparc_dwarf_handle_frame_unspec 531 532#ifdef SUBTARGET_INSERT_ATTRIBUTES 533#undef TARGET_INSERT_ATTRIBUTES 534#define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES 535#endif 536 537#ifdef SUBTARGET_ATTRIBUTE_TABLE 538#undef TARGET_ATTRIBUTE_TABLE 539#define TARGET_ATTRIBUTE_TABLE sparc_attribute_table 540#endif 541 542#undef TARGET_RELAXED_ORDERING 543#define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING 544 545#undef TARGET_DEFAULT_TARGET_FLAGS 546#define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT 547#undef TARGET_HANDLE_OPTION 548#define TARGET_HANDLE_OPTION sparc_handle_option 549 550#if TARGET_GNU_TLS 551#undef TARGET_ASM_OUTPUT_DWARF_DTPREL 552#define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel 553#endif 554 555#undef TARGET_ASM_FILE_END 556#define TARGET_ASM_FILE_END sparc_file_end 557 558#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING 559#undef TARGET_MANGLE_FUNDAMENTAL_TYPE 560#define TARGET_MANGLE_FUNDAMENTAL_TYPE sparc_mangle_fundamental_type 561#endif 562 563struct gcc_target targetm = TARGET_INITIALIZER; 564 565/* Implement TARGET_HANDLE_OPTION. */ 566 567static bool 568sparc_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) 569{ 570 switch (code) 571 { 572 case OPT_mfpu: 573 case OPT_mhard_float: 574 case OPT_msoft_float: 575 fpu_option_set = true; 576 break; 577 578 case OPT_mcpu_: 579 sparc_select[1].string = arg; 580 break; 581 582 case OPT_mtune_: 583 sparc_select[2].string = arg; 584 break; 585 } 586 587 return true; 588} 589 590/* Validate and override various options, and do some machine dependent 591 initialization. */ 592 593void 594sparc_override_options (void) 595{ 596 static struct code_model { 597 const char *const name; 598 const int value; 599 } const cmodels[] = { 600 { "32", CM_32 }, 601 { "medlow", CM_MEDLOW }, 602 { "medmid", CM_MEDMID }, 603 { "medany", CM_MEDANY }, 604 { "embmedany", CM_EMBMEDANY }, 605 { 0, 0 } 606 }; 607 const struct code_model *cmodel; 608 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */ 609 static struct cpu_default { 610 const int cpu; 611 const char *const name; 612 } const cpu_default[] = { 613 /* There must be one entry here for each TARGET_CPU value. */ 614 { TARGET_CPU_sparc, "cypress" }, 615 { TARGET_CPU_sparclet, "tsc701" }, 616 { TARGET_CPU_sparclite, "f930" }, 617 { TARGET_CPU_v8, "v8" }, 618 { TARGET_CPU_hypersparc, "hypersparc" }, 619 { TARGET_CPU_sparclite86x, "sparclite86x" }, 620 { TARGET_CPU_supersparc, "supersparc" }, 621 { TARGET_CPU_v9, "v9" }, 622 { TARGET_CPU_ultrasparc, "ultrasparc" }, 623 { TARGET_CPU_ultrasparc3, "ultrasparc3" }, 624 { TARGET_CPU_niagara, "niagara" }, 625 { 0, 0 } 626 }; 627 const struct cpu_default *def; 628 /* Table of values for -m{cpu,tune}=. */ 629 static struct cpu_table { 630 const char *const name; 631 const enum processor_type processor; 632 const int disable; 633 const int enable; 634 } const cpu_table[] = { 635 { "v7", PROCESSOR_V7, MASK_ISA, 0 }, 636 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 }, 637 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 }, 638 /* TI TMS390Z55 supersparc */ 639 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 }, 640 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE }, 641 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu. 642 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */ 643 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE }, 644 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU }, 645 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU }, 646 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU, 647 MASK_SPARCLITE }, 648 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET }, 649 /* TEMIC sparclet */ 650 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET }, 651 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 }, 652 /* TI ultrasparc I, II, IIi */ 653 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9 654 /* Although insns using %y are deprecated, it is a clear win on current 655 ultrasparcs. */ 656 |MASK_DEPRECATED_V8_INSNS}, 657 /* TI ultrasparc III */ 658 /* ??? Check if %y issue still holds true in ultra3. */ 659 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, 660 /* UltraSPARC T1 */ 661 { "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, 662 { 0, 0, 0, 0 } 663 }; 664 const struct cpu_table *cpu; 665 const struct sparc_cpu_select *sel; 666 int fpu; 667 668#ifndef SPARC_BI_ARCH 669 /* Check for unsupported architecture size. */ 670 if (! TARGET_64BIT != DEFAULT_ARCH32_P) 671 error ("%s is not supported by this configuration", 672 DEFAULT_ARCH32_P ? "-m64" : "-m32"); 673#endif 674 675 /* We force all 64bit archs to use 128 bit long double */ 676 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) 677 { 678 error ("-mlong-double-64 not allowed with -m64"); 679 target_flags |= MASK_LONG_DOUBLE_128; 680 } 681 682 /* Code model selection. */ 683 sparc_cmodel = SPARC_DEFAULT_CMODEL; 684 685#ifdef SPARC_BI_ARCH 686 if (TARGET_ARCH32) 687 sparc_cmodel = CM_32; 688#endif 689 690 if (sparc_cmodel_string != NULL) 691 { 692 if (TARGET_ARCH64) 693 { 694 for (cmodel = &cmodels[0]; cmodel->name; cmodel++) 695 if (strcmp (sparc_cmodel_string, cmodel->name) == 0) 696 break; 697 if (cmodel->name == NULL) 698 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); 699 else 700 sparc_cmodel = cmodel->value; 701 } 702 else 703 error ("-mcmodel= is not supported on 32 bit systems"); 704 } 705 706 fpu = target_flags & MASK_FPU; /* save current -mfpu status */ 707 708 /* Set the default CPU. */ 709 for (def = &cpu_default[0]; def->name; ++def) 710 if (def->cpu == TARGET_CPU_DEFAULT) 711 break; 712 gcc_assert (def->name); 713 sparc_select[0].string = def->name; 714 715 for (sel = &sparc_select[0]; sel->name; ++sel) 716 { 717 if (sel->string) 718 { 719 for (cpu = &cpu_table[0]; cpu->name; ++cpu) 720 if (! strcmp (sel->string, cpu->name)) 721 { 722 if (sel->set_tune_p) 723 sparc_cpu = cpu->processor; 724 725 if (sel->set_arch_p) 726 { 727 target_flags &= ~cpu->disable; 728 target_flags |= cpu->enable; 729 } 730 break; 731 } 732 733 if (! cpu->name) 734 error ("bad value (%s) for %s switch", sel->string, sel->name); 735 } 736 } 737 738 /* If -mfpu or -mno-fpu was explicitly used, don't override with 739 the processor default. */ 740 if (fpu_option_set) 741 target_flags = (target_flags & ~MASK_FPU) | fpu; 742 743 /* Don't allow -mvis if FPU is disabled. */ 744 if (! TARGET_FPU) 745 target_flags &= ~MASK_VIS; 746 747 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions 748 are available. 749 -m64 also implies v9. */ 750 if (TARGET_VIS || TARGET_ARCH64) 751 { 752 target_flags |= MASK_V9; 753 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); 754 } 755 756 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */ 757 if (TARGET_V9 && TARGET_ARCH32) 758 target_flags |= MASK_DEPRECATED_V8_INSNS; 759 760 /* V8PLUS requires V9, makes no sense in 64 bit mode. */ 761 if (! TARGET_V9 || TARGET_ARCH64) 762 target_flags &= ~MASK_V8PLUS; 763 764 /* Don't use stack biasing in 32 bit mode. */ 765 if (TARGET_ARCH32) 766 target_flags &= ~MASK_STACK_BIAS; 767 768 /* Supply a default value for align_functions. */ 769 if (align_functions == 0 770 && (sparc_cpu == PROCESSOR_ULTRASPARC 771 || sparc_cpu == PROCESSOR_ULTRASPARC3 772 || sparc_cpu == PROCESSOR_NIAGARA)) 773 align_functions = 32; 774 775 /* Validate PCC_STRUCT_RETURN. */ 776 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) 777 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); 778 779 /* Only use .uaxword when compiling for a 64-bit target. */ 780 if (!TARGET_ARCH64) 781 targetm.asm_out.unaligned_op.di = NULL; 782 783 /* Do various machine dependent initializations. */ 784 sparc_init_modes (); 785 786 /* Acquire unique alias sets for our private stuff. */ 787 sparc_sr_alias_set = new_alias_set (); 788 struct_value_alias_set = new_alias_set (); 789 790 /* Set up function hooks. */ 791 init_machine_status = sparc_init_machine_status; 792 793 switch (sparc_cpu) 794 { 795 case PROCESSOR_V7: 796 case PROCESSOR_CYPRESS: 797 sparc_costs = &cypress_costs; 798 break; 799 case PROCESSOR_V8: 800 case PROCESSOR_SPARCLITE: 801 case PROCESSOR_SUPERSPARC: 802 sparc_costs = &supersparc_costs; 803 break; 804 case PROCESSOR_F930: 805 case PROCESSOR_F934: 806 case PROCESSOR_HYPERSPARC: 807 case PROCESSOR_SPARCLITE86X: 808 sparc_costs = &hypersparc_costs; 809 break; 810 case PROCESSOR_SPARCLET: 811 case PROCESSOR_TSC701: 812 sparc_costs = &sparclet_costs; 813 break; 814 case PROCESSOR_V9: 815 case PROCESSOR_ULTRASPARC: 816 sparc_costs = &ultrasparc_costs; 817 break; 818 case PROCESSOR_ULTRASPARC3: 819 sparc_costs = &ultrasparc3_costs; 820 break; 821 case PROCESSOR_NIAGARA: 822 sparc_costs = &niagara_costs; 823 break; 824 }; 825 826#ifdef TARGET_DEFAULT_LONG_DOUBLE_128 827 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128)) 828 target_flags |= MASK_LONG_DOUBLE_128; 829#endif 830} 831 832#ifdef SUBTARGET_ATTRIBUTE_TABLE 833/* Table of valid machine attributes. */ 834const struct attribute_spec sparc_attribute_table[] = 835{ 836 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ 837 SUBTARGET_ATTRIBUTE_TABLE, 838 { NULL, 0, 0, false, false, false, NULL } 839}; 840#endif 841 842/* Miscellaneous utilities. */ 843 844/* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move 845 or branch on register contents instructions. */ 846 847int 848v9_regcmp_p (enum rtx_code code) 849{ 850 return (code == EQ || code == NE || code == GE || code == LT 851 || code == LE || code == GT); 852} 853 854/* Nonzero if OP is a floating point constant which can 855 be loaded into an integer register using a single 856 sethi instruction. */ 857 858int 859fp_sethi_p (rtx op) 860{ 861 if (GET_CODE (op) == CONST_DOUBLE) 862 { 863 REAL_VALUE_TYPE r; 864 long i; 865 866 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 867 REAL_VALUE_TO_TARGET_SINGLE (r, i); 868 return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i); 869 } 870 871 return 0; 872} 873 874/* Nonzero if OP is a floating point constant which can 875 be loaded into an integer register using a single 876 mov instruction. */ 877 878int 879fp_mov_p (rtx op) 880{ 881 if (GET_CODE (op) == CONST_DOUBLE) 882 { 883 REAL_VALUE_TYPE r; 884 long i; 885 886 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 887 REAL_VALUE_TO_TARGET_SINGLE (r, i); 888 return SPARC_SIMM13_P (i); 889 } 890 891 return 0; 892} 893 894/* Nonzero if OP is a floating point constant which can 895 be loaded into an integer register using a high/losum 896 instruction sequence. */ 897 898int 899fp_high_losum_p (rtx op) 900{ 901 /* The constraints calling this should only be in 902 SFmode move insns, so any constant which cannot 903 be moved using a single insn will do. */ 904 if (GET_CODE (op) == CONST_DOUBLE) 905 { 906 REAL_VALUE_TYPE r; 907 long i; 908 909 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 910 REAL_VALUE_TO_TARGET_SINGLE (r, i); 911 return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i); 912 } 913 914 return 0; 915} 916 917/* Expand a move instruction. Return true if all work is done. */ 918 919bool 920sparc_expand_move (enum machine_mode mode, rtx *operands) 921{ 922 /* Handle sets of MEM first. */ 923 if (GET_CODE (operands[0]) == MEM) 924 { 925 /* 0 is a register (or a pair of registers) on SPARC. */ 926 if (register_or_zero_operand (operands[1], mode)) 927 return false; 928 929 if (!reload_in_progress) 930 { 931 operands[0] = validize_mem (operands[0]); 932 operands[1] = force_reg (mode, operands[1]); 933 } 934 } 935 936 /* Fixup TLS cases. */ 937 if (TARGET_HAVE_TLS 938 && CONSTANT_P (operands[1]) 939 && GET_CODE (operands[1]) != HIGH 940 && sparc_tls_referenced_p (operands [1])) 941 { 942 rtx sym = operands[1]; 943 rtx addend = NULL; 944 945 if (GET_CODE (sym) == CONST && GET_CODE (XEXP (sym, 0)) == PLUS) 946 { 947 addend = XEXP (XEXP (sym, 0), 1); 948 sym = XEXP (XEXP (sym, 0), 0); 949 } 950 951 gcc_assert (SPARC_SYMBOL_REF_TLS_P (sym)); 952 953 sym = legitimize_tls_address (sym); 954 if (addend) 955 { 956 sym = gen_rtx_PLUS (mode, sym, addend); 957 sym = force_operand (sym, operands[0]); 958 } 959 operands[1] = sym; 960 } 961 962 /* Fixup PIC cases. */ 963 if (flag_pic && CONSTANT_P (operands[1])) 964 { 965 if (pic_address_needs_scratch (operands[1])) 966 operands[1] = legitimize_pic_address (operands[1], mode, 0); 967 968 if (GET_CODE (operands[1]) == LABEL_REF && mode == SImode) 969 { 970 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1])); 971 return true; 972 } 973 974 if (GET_CODE (operands[1]) == LABEL_REF && mode == DImode) 975 { 976 gcc_assert (TARGET_ARCH64); 977 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1])); 978 return true; 979 } 980 981 if (symbolic_operand (operands[1], mode)) 982 { 983 operands[1] = legitimize_pic_address (operands[1], 984 mode, 985 (reload_in_progress ? 986 operands[0] : 987 NULL_RTX)); 988 return false; 989 } 990 } 991 992 /* If we are trying to toss an integer constant into FP registers, 993 or loading a FP or vector constant, force it into memory. */ 994 if (CONSTANT_P (operands[1]) 995 && REG_P (operands[0]) 996 && (SPARC_FP_REG_P (REGNO (operands[0])) 997 || SCALAR_FLOAT_MODE_P (mode) 998 || VECTOR_MODE_P (mode))) 999 { 1000 /* emit_group_store will send such bogosity to us when it is 1001 not storing directly into memory. So fix this up to avoid 1002 crashes in output_constant_pool. */ 1003 if (operands [1] == const0_rtx) 1004 operands[1] = CONST0_RTX (mode); 1005 1006 /* We can clear FP registers if TARGET_VIS, and always other regs. */ 1007 if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG) 1008 && const_zero_operand (operands[1], mode)) 1009 return false; 1010 1011 if (REGNO (operands[0]) < SPARC_FIRST_FP_REG 1012 /* We are able to build any SF constant in integer registers 1013 with at most 2 instructions. */ 1014 && (mode == SFmode 1015 /* And any DF constant in integer registers. */ 1016 || (mode == DFmode 1017 && (reload_completed || reload_in_progress)))) 1018 return false; 1019 1020 operands[1] = force_const_mem (mode, operands[1]); 1021 if (!reload_in_progress) 1022 operands[1] = validize_mem (operands[1]); 1023 return false; 1024 } 1025 1026 /* Accept non-constants and valid constants unmodified. */ 1027 if (!CONSTANT_P (operands[1]) 1028 || GET_CODE (operands[1]) == HIGH 1029 || input_operand (operands[1], mode)) 1030 return false; 1031 1032 switch (mode) 1033 { 1034 case QImode: 1035 /* All QImode constants require only one insn, so proceed. */ 1036 break; 1037 1038 case HImode: 1039 case SImode: 1040 sparc_emit_set_const32 (operands[0], operands[1]); 1041 return true; 1042 1043 case DImode: 1044 /* input_operand should have filtered out 32-bit mode. */ 1045 sparc_emit_set_const64 (operands[0], operands[1]); 1046 return true; 1047 1048 default: 1049 gcc_unreachable (); 1050 } 1051 1052 return false; 1053} 1054 1055/* Load OP1, a 32-bit constant, into OP0, a register. 1056 We know it can't be done in one insn when we get 1057 here, the move expander guarantees this. */ 1058 1059void 1060sparc_emit_set_const32 (rtx op0, rtx op1) 1061{ 1062 enum machine_mode mode = GET_MODE (op0); 1063 rtx temp; 1064 1065 if (reload_in_progress || reload_completed) 1066 temp = op0; 1067 else 1068 temp = gen_reg_rtx (mode); 1069 1070 if (GET_CODE (op1) == CONST_INT) 1071 { 1072 gcc_assert (!small_int_operand (op1, mode) 1073 && !const_high_operand (op1, mode)); 1074 1075 /* Emit them as real moves instead of a HIGH/LO_SUM, 1076 this way CSE can see everything and reuse intermediate 1077 values if it wants. */ 1078 emit_insn (gen_rtx_SET (VOIDmode, temp, 1079 GEN_INT (INTVAL (op1) 1080 & ~(HOST_WIDE_INT)0x3ff))); 1081 1082 emit_insn (gen_rtx_SET (VOIDmode, 1083 op0, 1084 gen_rtx_IOR (mode, temp, 1085 GEN_INT (INTVAL (op1) & 0x3ff)))); 1086 } 1087 else 1088 { 1089 /* A symbol, emit in the traditional way. */ 1090 emit_insn (gen_rtx_SET (VOIDmode, temp, 1091 gen_rtx_HIGH (mode, op1))); 1092 emit_insn (gen_rtx_SET (VOIDmode, 1093 op0, gen_rtx_LO_SUM (mode, temp, op1))); 1094 } 1095} 1096 1097/* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register. 1098 If TEMP is nonzero, we are forbidden to use any other scratch 1099 registers. Otherwise, we are allowed to generate them as needed. 1100 1101 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY 1102 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */ 1103 1104void 1105sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp) 1106{ 1107 rtx temp1, temp2, temp3, temp4, temp5; 1108 rtx ti_temp = 0; 1109 1110 if (temp && GET_MODE (temp) == TImode) 1111 { 1112 ti_temp = temp; 1113 temp = gen_rtx_REG (DImode, REGNO (temp)); 1114 } 1115 1116 /* SPARC-V9 code-model support. */ 1117 switch (sparc_cmodel) 1118 { 1119 case CM_MEDLOW: 1120 /* The range spanned by all instructions in the object is less 1121 than 2^31 bytes (2GB) and the distance from any instruction 1122 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1123 than 2^31 bytes (2GB). 1124 1125 The executable must be in the low 4TB of the virtual address 1126 space. 1127 1128 sethi %hi(symbol), %temp1 1129 or %temp1, %lo(symbol), %reg */ 1130 if (temp) 1131 temp1 = temp; /* op0 is allowed. */ 1132 else 1133 temp1 = gen_reg_rtx (DImode); 1134 1135 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1))); 1136 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1))); 1137 break; 1138 1139 case CM_MEDMID: 1140 /* The range spanned by all instructions in the object is less 1141 than 2^31 bytes (2GB) and the distance from any instruction 1142 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1143 than 2^31 bytes (2GB). 1144 1145 The executable must be in the low 16TB of the virtual address 1146 space. 1147 1148 sethi %h44(symbol), %temp1 1149 or %temp1, %m44(symbol), %temp2 1150 sllx %temp2, 12, %temp3 1151 or %temp3, %l44(symbol), %reg */ 1152 if (temp) 1153 { 1154 temp1 = op0; 1155 temp2 = op0; 1156 temp3 = temp; /* op0 is allowed. */ 1157 } 1158 else 1159 { 1160 temp1 = gen_reg_rtx (DImode); 1161 temp2 = gen_reg_rtx (DImode); 1162 temp3 = gen_reg_rtx (DImode); 1163 } 1164 1165 emit_insn (gen_seth44 (temp1, op1)); 1166 emit_insn (gen_setm44 (temp2, temp1, op1)); 1167 emit_insn (gen_rtx_SET (VOIDmode, temp3, 1168 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12)))); 1169 emit_insn (gen_setl44 (op0, temp3, op1)); 1170 break; 1171 1172 case CM_MEDANY: 1173 /* The range spanned by all instructions in the object is less 1174 than 2^31 bytes (2GB) and the distance from any instruction 1175 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 1176 than 2^31 bytes (2GB). 1177 1178 The executable can be placed anywhere in the virtual address 1179 space. 1180 1181 sethi %hh(symbol), %temp1 1182 sethi %lm(symbol), %temp2 1183 or %temp1, %hm(symbol), %temp3 1184 sllx %temp3, 32, %temp4 1185 or %temp4, %temp2, %temp5 1186 or %temp5, %lo(symbol), %reg */ 1187 if (temp) 1188 { 1189 /* It is possible that one of the registers we got for operands[2] 1190 might coincide with that of operands[0] (which is why we made 1191 it TImode). Pick the other one to use as our scratch. */ 1192 if (rtx_equal_p (temp, op0)) 1193 { 1194 gcc_assert (ti_temp); 1195 temp = gen_rtx_REG (DImode, REGNO (temp) + 1); 1196 } 1197 temp1 = op0; 1198 temp2 = temp; /* op0 is _not_ allowed, see above. */ 1199 temp3 = op0; 1200 temp4 = op0; 1201 temp5 = op0; 1202 } 1203 else 1204 { 1205 temp1 = gen_reg_rtx (DImode); 1206 temp2 = gen_reg_rtx (DImode); 1207 temp3 = gen_reg_rtx (DImode); 1208 temp4 = gen_reg_rtx (DImode); 1209 temp5 = gen_reg_rtx (DImode); 1210 } 1211 1212 emit_insn (gen_sethh (temp1, op1)); 1213 emit_insn (gen_setlm (temp2, op1)); 1214 emit_insn (gen_sethm (temp3, temp1, op1)); 1215 emit_insn (gen_rtx_SET (VOIDmode, temp4, 1216 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32)))); 1217 emit_insn (gen_rtx_SET (VOIDmode, temp5, 1218 gen_rtx_PLUS (DImode, temp4, temp2))); 1219 emit_insn (gen_setlo (op0, temp5, op1)); 1220 break; 1221 1222 case CM_EMBMEDANY: 1223 /* Old old old backwards compatibility kruft here. 1224 Essentially it is MEDLOW with a fixed 64-bit 1225 virtual base added to all data segment addresses. 1226 Text-segment stuff is computed like MEDANY, we can't 1227 reuse the code above because the relocation knobs 1228 look different. 1229 1230 Data segment: sethi %hi(symbol), %temp1 1231 add %temp1, EMBMEDANY_BASE_REG, %temp2 1232 or %temp2, %lo(symbol), %reg */ 1233 if (data_segment_operand (op1, GET_MODE (op1))) 1234 { 1235 if (temp) 1236 { 1237 temp1 = temp; /* op0 is allowed. */ 1238 temp2 = op0; 1239 } 1240 else 1241 { 1242 temp1 = gen_reg_rtx (DImode); 1243 temp2 = gen_reg_rtx (DImode); 1244 } 1245 1246 emit_insn (gen_embmedany_sethi (temp1, op1)); 1247 emit_insn (gen_embmedany_brsum (temp2, temp1)); 1248 emit_insn (gen_embmedany_losum (op0, temp2, op1)); 1249 } 1250 1251 /* Text segment: sethi %uhi(symbol), %temp1 1252 sethi %hi(symbol), %temp2 1253 or %temp1, %ulo(symbol), %temp3 1254 sllx %temp3, 32, %temp4 1255 or %temp4, %temp2, %temp5 1256 or %temp5, %lo(symbol), %reg */ 1257 else 1258 { 1259 if (temp) 1260 { 1261 /* It is possible that one of the registers we got for operands[2] 1262 might coincide with that of operands[0] (which is why we made 1263 it TImode). Pick the other one to use as our scratch. */ 1264 if (rtx_equal_p (temp, op0)) 1265 { 1266 gcc_assert (ti_temp); 1267 temp = gen_rtx_REG (DImode, REGNO (temp) + 1); 1268 } 1269 temp1 = op0; 1270 temp2 = temp; /* op0 is _not_ allowed, see above. */ 1271 temp3 = op0; 1272 temp4 = op0; 1273 temp5 = op0; 1274 } 1275 else 1276 { 1277 temp1 = gen_reg_rtx (DImode); 1278 temp2 = gen_reg_rtx (DImode); 1279 temp3 = gen_reg_rtx (DImode); 1280 temp4 = gen_reg_rtx (DImode); 1281 temp5 = gen_reg_rtx (DImode); 1282 } 1283 1284 emit_insn (gen_embmedany_textuhi (temp1, op1)); 1285 emit_insn (gen_embmedany_texthi (temp2, op1)); 1286 emit_insn (gen_embmedany_textulo (temp3, temp1, op1)); 1287 emit_insn (gen_rtx_SET (VOIDmode, temp4, 1288 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32)))); 1289 emit_insn (gen_rtx_SET (VOIDmode, temp5, 1290 gen_rtx_PLUS (DImode, temp4, temp2))); 1291 emit_insn (gen_embmedany_textlo (op0, temp5, op1)); 1292 } 1293 break; 1294 1295 default: 1296 gcc_unreachable (); 1297 } 1298} 1299 1300#if HOST_BITS_PER_WIDE_INT == 32 1301void 1302sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED, rtx op1 ATTRIBUTE_UNUSED) 1303{ 1304 gcc_unreachable (); 1305} 1306#else 1307/* These avoid problems when cross compiling. If we do not 1308 go through all this hair then the optimizer will see 1309 invalid REG_EQUAL notes or in some cases none at all. */ 1310static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT); 1311static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT); 1312static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT); 1313static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT); 1314 1315/* The optimizer is not to assume anything about exactly 1316 which bits are set for a HIGH, they are unspecified. 1317 Unfortunately this leads to many missed optimizations 1318 during CSE. We mask out the non-HIGH bits, and matches 1319 a plain movdi, to alleviate this problem. */ 1320static rtx 1321gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val) 1322{ 1323 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff)); 1324} 1325 1326static rtx 1327gen_safe_SET64 (rtx dest, HOST_WIDE_INT val) 1328{ 1329 return gen_rtx_SET (VOIDmode, dest, GEN_INT (val)); 1330} 1331 1332static rtx 1333gen_safe_OR64 (rtx src, HOST_WIDE_INT val) 1334{ 1335 return gen_rtx_IOR (DImode, src, GEN_INT (val)); 1336} 1337 1338static rtx 1339gen_safe_XOR64 (rtx src, HOST_WIDE_INT val) 1340{ 1341 return gen_rtx_XOR (DImode, src, GEN_INT (val)); 1342} 1343 1344/* Worker routines for 64-bit constant formation on arch64. 1345 One of the key things to be doing in these emissions is 1346 to create as many temp REGs as possible. This makes it 1347 possible for half-built constants to be used later when 1348 such values are similar to something required later on. 1349 Without doing this, the optimizer cannot see such 1350 opportunities. */ 1351 1352static void sparc_emit_set_const64_quick1 (rtx, rtx, 1353 unsigned HOST_WIDE_INT, int); 1354 1355static void 1356sparc_emit_set_const64_quick1 (rtx op0, rtx temp, 1357 unsigned HOST_WIDE_INT low_bits, int is_neg) 1358{ 1359 unsigned HOST_WIDE_INT high_bits; 1360 1361 if (is_neg) 1362 high_bits = (~low_bits) & 0xffffffff; 1363 else 1364 high_bits = low_bits; 1365 1366 emit_insn (gen_safe_HIGH64 (temp, high_bits)); 1367 if (!is_neg) 1368 { 1369 emit_insn (gen_rtx_SET (VOIDmode, op0, 1370 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1371 } 1372 else 1373 { 1374 /* If we are XOR'ing with -1, then we should emit a one's complement 1375 instead. This way the combiner will notice logical operations 1376 such as ANDN later on and substitute. */ 1377 if ((low_bits & 0x3ff) == 0x3ff) 1378 { 1379 emit_insn (gen_rtx_SET (VOIDmode, op0, 1380 gen_rtx_NOT (DImode, temp))); 1381 } 1382 else 1383 { 1384 emit_insn (gen_rtx_SET (VOIDmode, op0, 1385 gen_safe_XOR64 (temp, 1386 (-(HOST_WIDE_INT)0x400 1387 | (low_bits & 0x3ff))))); 1388 } 1389 } 1390} 1391 1392static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT, 1393 unsigned HOST_WIDE_INT, int); 1394 1395static void 1396sparc_emit_set_const64_quick2 (rtx op0, rtx temp, 1397 unsigned HOST_WIDE_INT high_bits, 1398 unsigned HOST_WIDE_INT low_immediate, 1399 int shift_count) 1400{ 1401 rtx temp2 = op0; 1402 1403 if ((high_bits & 0xfffffc00) != 0) 1404 { 1405 emit_insn (gen_safe_HIGH64 (temp, high_bits)); 1406 if ((high_bits & ~0xfffffc00) != 0) 1407 emit_insn (gen_rtx_SET (VOIDmode, op0, 1408 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1409 else 1410 temp2 = temp; 1411 } 1412 else 1413 { 1414 emit_insn (gen_safe_SET64 (temp, high_bits)); 1415 temp2 = temp; 1416 } 1417 1418 /* Now shift it up into place. */ 1419 emit_insn (gen_rtx_SET (VOIDmode, op0, 1420 gen_rtx_ASHIFT (DImode, temp2, 1421 GEN_INT (shift_count)))); 1422 1423 /* If there is a low immediate part piece, finish up by 1424 putting that in as well. */ 1425 if (low_immediate != 0) 1426 emit_insn (gen_rtx_SET (VOIDmode, op0, 1427 gen_safe_OR64 (op0, low_immediate))); 1428} 1429 1430static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT, 1431 unsigned HOST_WIDE_INT); 1432 1433/* Full 64-bit constant decomposition. Even though this is the 1434 'worst' case, we still optimize a few things away. */ 1435static void 1436sparc_emit_set_const64_longway (rtx op0, rtx temp, 1437 unsigned HOST_WIDE_INT high_bits, 1438 unsigned HOST_WIDE_INT low_bits) 1439{ 1440 rtx sub_temp; 1441 1442 if (reload_in_progress || reload_completed) 1443 sub_temp = op0; 1444 else 1445 sub_temp = gen_reg_rtx (DImode); 1446 1447 if ((high_bits & 0xfffffc00) != 0) 1448 { 1449 emit_insn (gen_safe_HIGH64 (temp, high_bits)); 1450 if ((high_bits & ~0xfffffc00) != 0) 1451 emit_insn (gen_rtx_SET (VOIDmode, 1452 sub_temp, 1453 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 1454 else 1455 sub_temp = temp; 1456 } 1457 else 1458 { 1459 emit_insn (gen_safe_SET64 (temp, high_bits)); 1460 sub_temp = temp; 1461 } 1462 1463 if (!reload_in_progress && !reload_completed) 1464 { 1465 rtx temp2 = gen_reg_rtx (DImode); 1466 rtx temp3 = gen_reg_rtx (DImode); 1467 rtx temp4 = gen_reg_rtx (DImode); 1468 1469 emit_insn (gen_rtx_SET (VOIDmode, temp4, 1470 gen_rtx_ASHIFT (DImode, sub_temp, 1471 GEN_INT (32)))); 1472 1473 emit_insn (gen_safe_HIGH64 (temp2, low_bits)); 1474 if ((low_bits & ~0xfffffc00) != 0) 1475 { 1476 emit_insn (gen_rtx_SET (VOIDmode, temp3, 1477 gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); 1478 emit_insn (gen_rtx_SET (VOIDmode, op0, 1479 gen_rtx_PLUS (DImode, temp4, temp3))); 1480 } 1481 else 1482 { 1483 emit_insn (gen_rtx_SET (VOIDmode, op0, 1484 gen_rtx_PLUS (DImode, temp4, temp2))); 1485 } 1486 } 1487 else 1488 { 1489 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); 1490 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); 1491 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); 1492 int to_shift = 12; 1493 1494 /* We are in the middle of reload, so this is really 1495 painful. However we do still make an attempt to 1496 avoid emitting truly stupid code. */ 1497 if (low1 != const0_rtx) 1498 { 1499 emit_insn (gen_rtx_SET (VOIDmode, op0, 1500 gen_rtx_ASHIFT (DImode, sub_temp, 1501 GEN_INT (to_shift)))); 1502 emit_insn (gen_rtx_SET (VOIDmode, op0, 1503 gen_rtx_IOR (DImode, op0, low1))); 1504 sub_temp = op0; 1505 to_shift = 12; 1506 } 1507 else 1508 { 1509 to_shift += 12; 1510 } 1511 if (low2 != const0_rtx) 1512 { 1513 emit_insn (gen_rtx_SET (VOIDmode, op0, 1514 gen_rtx_ASHIFT (DImode, sub_temp, 1515 GEN_INT (to_shift)))); 1516 emit_insn (gen_rtx_SET (VOIDmode, op0, 1517 gen_rtx_IOR (DImode, op0, low2))); 1518 sub_temp = op0; 1519 to_shift = 8; 1520 } 1521 else 1522 { 1523 to_shift += 8; 1524 } 1525 emit_insn (gen_rtx_SET (VOIDmode, op0, 1526 gen_rtx_ASHIFT (DImode, sub_temp, 1527 GEN_INT (to_shift)))); 1528 if (low3 != const0_rtx) 1529 emit_insn (gen_rtx_SET (VOIDmode, op0, 1530 gen_rtx_IOR (DImode, op0, low3))); 1531 /* phew... */ 1532 } 1533} 1534 1535/* Analyze a 64-bit constant for certain properties. */ 1536static void analyze_64bit_constant (unsigned HOST_WIDE_INT, 1537 unsigned HOST_WIDE_INT, 1538 int *, int *, int *); 1539 1540static void 1541analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits, 1542 unsigned HOST_WIDE_INT low_bits, 1543 int *hbsp, int *lbsp, int *abbasp) 1544{ 1545 int lowest_bit_set, highest_bit_set, all_bits_between_are_set; 1546 int i; 1547 1548 lowest_bit_set = highest_bit_set = -1; 1549 i = 0; 1550 do 1551 { 1552 if ((lowest_bit_set == -1) 1553 && ((low_bits >> i) & 1)) 1554 lowest_bit_set = i; 1555 if ((highest_bit_set == -1) 1556 && ((high_bits >> (32 - i - 1)) & 1)) 1557 highest_bit_set = (64 - i - 1); 1558 } 1559 while (++i < 32 1560 && ((highest_bit_set == -1) 1561 || (lowest_bit_set == -1))); 1562 if (i == 32) 1563 { 1564 i = 0; 1565 do 1566 { 1567 if ((lowest_bit_set == -1) 1568 && ((high_bits >> i) & 1)) 1569 lowest_bit_set = i + 32; 1570 if ((highest_bit_set == -1) 1571 && ((low_bits >> (32 - i - 1)) & 1)) 1572 highest_bit_set = 32 - i - 1; 1573 } 1574 while (++i < 32 1575 && ((highest_bit_set == -1) 1576 || (lowest_bit_set == -1))); 1577 } 1578 /* If there are no bits set this should have gone out 1579 as one instruction! */ 1580 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1); 1581 all_bits_between_are_set = 1; 1582 for (i = lowest_bit_set; i <= highest_bit_set; i++) 1583 { 1584 if (i < 32) 1585 { 1586 if ((low_bits & (1 << i)) != 0) 1587 continue; 1588 } 1589 else 1590 { 1591 if ((high_bits & (1 << (i - 32))) != 0) 1592 continue; 1593 } 1594 all_bits_between_are_set = 0; 1595 break; 1596 } 1597 *hbsp = highest_bit_set; 1598 *lbsp = lowest_bit_set; 1599 *abbasp = all_bits_between_are_set; 1600} 1601 1602static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT); 1603 1604static int 1605const64_is_2insns (unsigned HOST_WIDE_INT high_bits, 1606 unsigned HOST_WIDE_INT low_bits) 1607{ 1608 int highest_bit_set, lowest_bit_set, all_bits_between_are_set; 1609 1610 if (high_bits == 0 1611 || high_bits == 0xffffffff) 1612 return 1; 1613 1614 analyze_64bit_constant (high_bits, low_bits, 1615 &highest_bit_set, &lowest_bit_set, 1616 &all_bits_between_are_set); 1617 1618 if ((highest_bit_set == 63 1619 || lowest_bit_set == 0) 1620 && all_bits_between_are_set != 0) 1621 return 1; 1622 1623 if ((highest_bit_set - lowest_bit_set) < 21) 1624 return 1; 1625 1626 return 0; 1627} 1628 1629static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT, 1630 unsigned HOST_WIDE_INT, 1631 int, int); 1632 1633static unsigned HOST_WIDE_INT 1634create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits, 1635 unsigned HOST_WIDE_INT low_bits, 1636 int lowest_bit_set, int shift) 1637{ 1638 HOST_WIDE_INT hi, lo; 1639 1640 if (lowest_bit_set < 32) 1641 { 1642 lo = (low_bits >> lowest_bit_set) << shift; 1643 hi = ((high_bits << (32 - lowest_bit_set)) << shift); 1644 } 1645 else 1646 { 1647 lo = 0; 1648 hi = ((high_bits >> (lowest_bit_set - 32)) << shift); 1649 } 1650 gcc_assert (! (hi & lo)); 1651 return (hi | lo); 1652} 1653 1654/* Here we are sure to be arch64 and this is an integer constant 1655 being loaded into a register. Emit the most efficient 1656 insn sequence possible. Detection of all the 1-insn cases 1657 has been done already. */ 1658void 1659sparc_emit_set_const64 (rtx op0, rtx op1) 1660{ 1661 unsigned HOST_WIDE_INT high_bits, low_bits; 1662 int lowest_bit_set, highest_bit_set; 1663 int all_bits_between_are_set; 1664 rtx temp = 0; 1665 1666 /* Sanity check that we know what we are working with. */ 1667 gcc_assert (TARGET_ARCH64 1668 && (GET_CODE (op0) == SUBREG 1669 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0))))); 1670 1671 if (reload_in_progress || reload_completed) 1672 temp = op0; 1673 1674 if (GET_CODE (op1) != CONST_INT) 1675 { 1676 sparc_emit_set_symbolic_const64 (op0, op1, temp); 1677 return; 1678 } 1679 1680 if (! temp) 1681 temp = gen_reg_rtx (DImode); 1682 1683 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); 1684 low_bits = (INTVAL (op1) & 0xffffffff); 1685 1686 /* low_bits bits 0 --> 31 1687 high_bits bits 32 --> 63 */ 1688 1689 analyze_64bit_constant (high_bits, low_bits, 1690 &highest_bit_set, &lowest_bit_set, 1691 &all_bits_between_are_set); 1692 1693 /* First try for a 2-insn sequence. */ 1694 1695 /* These situations are preferred because the optimizer can 1696 * do more things with them: 1697 * 1) mov -1, %reg 1698 * sllx %reg, shift, %reg 1699 * 2) mov -1, %reg 1700 * srlx %reg, shift, %reg 1701 * 3) mov some_small_const, %reg 1702 * sllx %reg, shift, %reg 1703 */ 1704 if (((highest_bit_set == 63 1705 || lowest_bit_set == 0) 1706 && all_bits_between_are_set != 0) 1707 || ((highest_bit_set - lowest_bit_set) < 12)) 1708 { 1709 HOST_WIDE_INT the_const = -1; 1710 int shift = lowest_bit_set; 1711 1712 if ((highest_bit_set != 63 1713 && lowest_bit_set != 0) 1714 || all_bits_between_are_set == 0) 1715 { 1716 the_const = 1717 create_simple_focus_bits (high_bits, low_bits, 1718 lowest_bit_set, 0); 1719 } 1720 else if (lowest_bit_set == 0) 1721 shift = -(63 - highest_bit_set); 1722 1723 gcc_assert (SPARC_SIMM13_P (the_const)); 1724 gcc_assert (shift != 0); 1725 1726 emit_insn (gen_safe_SET64 (temp, the_const)); 1727 if (shift > 0) 1728 emit_insn (gen_rtx_SET (VOIDmode, 1729 op0, 1730 gen_rtx_ASHIFT (DImode, 1731 temp, 1732 GEN_INT (shift)))); 1733 else if (shift < 0) 1734 emit_insn (gen_rtx_SET (VOIDmode, 1735 op0, 1736 gen_rtx_LSHIFTRT (DImode, 1737 temp, 1738 GEN_INT (-shift)))); 1739 return; 1740 } 1741 1742 /* Now a range of 22 or less bits set somewhere. 1743 * 1) sethi %hi(focus_bits), %reg 1744 * sllx %reg, shift, %reg 1745 * 2) sethi %hi(focus_bits), %reg 1746 * srlx %reg, shift, %reg 1747 */ 1748 if ((highest_bit_set - lowest_bit_set) < 21) 1749 { 1750 unsigned HOST_WIDE_INT focus_bits = 1751 create_simple_focus_bits (high_bits, low_bits, 1752 lowest_bit_set, 10); 1753 1754 gcc_assert (SPARC_SETHI_P (focus_bits)); 1755 gcc_assert (lowest_bit_set != 10); 1756 1757 emit_insn (gen_safe_HIGH64 (temp, focus_bits)); 1758 1759 /* If lowest_bit_set == 10 then a sethi alone could have done it. */ 1760 if (lowest_bit_set < 10) 1761 emit_insn (gen_rtx_SET (VOIDmode, 1762 op0, 1763 gen_rtx_LSHIFTRT (DImode, temp, 1764 GEN_INT (10 - lowest_bit_set)))); 1765 else if (lowest_bit_set > 10) 1766 emit_insn (gen_rtx_SET (VOIDmode, 1767 op0, 1768 gen_rtx_ASHIFT (DImode, temp, 1769 GEN_INT (lowest_bit_set - 10)))); 1770 return; 1771 } 1772 1773 /* 1) sethi %hi(low_bits), %reg 1774 * or %reg, %lo(low_bits), %reg 1775 * 2) sethi %hi(~low_bits), %reg 1776 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg 1777 */ 1778 if (high_bits == 0 1779 || high_bits == 0xffffffff) 1780 { 1781 sparc_emit_set_const64_quick1 (op0, temp, low_bits, 1782 (high_bits == 0xffffffff)); 1783 return; 1784 } 1785 1786 /* Now, try 3-insn sequences. */ 1787 1788 /* 1) sethi %hi(high_bits), %reg 1789 * or %reg, %lo(high_bits), %reg 1790 * sllx %reg, 32, %reg 1791 */ 1792 if (low_bits == 0) 1793 { 1794 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); 1795 return; 1796 } 1797 1798 /* We may be able to do something quick 1799 when the constant is negated, so try that. */ 1800 if (const64_is_2insns ((~high_bits) & 0xffffffff, 1801 (~low_bits) & 0xfffffc00)) 1802 { 1803 /* NOTE: The trailing bits get XOR'd so we need the 1804 non-negated bits, not the negated ones. */ 1805 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; 1806 1807 if ((((~high_bits) & 0xffffffff) == 0 1808 && ((~low_bits) & 0x80000000) == 0) 1809 || (((~high_bits) & 0xffffffff) == 0xffffffff 1810 && ((~low_bits) & 0x80000000) != 0)) 1811 { 1812 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff); 1813 1814 if ((SPARC_SETHI_P (fast_int) 1815 && (~high_bits & 0xffffffff) == 0) 1816 || SPARC_SIMM13_P (fast_int)) 1817 emit_insn (gen_safe_SET64 (temp, fast_int)); 1818 else 1819 sparc_emit_set_const64 (temp, GEN_INT (fast_int)); 1820 } 1821 else 1822 { 1823 rtx negated_const; 1824 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | 1825 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); 1826 sparc_emit_set_const64 (temp, negated_const); 1827 } 1828 1829 /* If we are XOR'ing with -1, then we should emit a one's complement 1830 instead. This way the combiner will notice logical operations 1831 such as ANDN later on and substitute. */ 1832 if (trailing_bits == 0x3ff) 1833 { 1834 emit_insn (gen_rtx_SET (VOIDmode, op0, 1835 gen_rtx_NOT (DImode, temp))); 1836 } 1837 else 1838 { 1839 emit_insn (gen_rtx_SET (VOIDmode, 1840 op0, 1841 gen_safe_XOR64 (temp, 1842 (-0x400 | trailing_bits)))); 1843 } 1844 return; 1845 } 1846 1847 /* 1) sethi %hi(xxx), %reg 1848 * or %reg, %lo(xxx), %reg 1849 * sllx %reg, yyy, %reg 1850 * 1851 * ??? This is just a generalized version of the low_bits==0 1852 * thing above, FIXME... 1853 */ 1854 if ((highest_bit_set - lowest_bit_set) < 32) 1855 { 1856 unsigned HOST_WIDE_INT focus_bits = 1857 create_simple_focus_bits (high_bits, low_bits, 1858 lowest_bit_set, 0); 1859 1860 /* We can't get here in this state. */ 1861 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32); 1862 1863 /* So what we know is that the set bits straddle the 1864 middle of the 64-bit word. */ 1865 sparc_emit_set_const64_quick2 (op0, temp, 1866 focus_bits, 0, 1867 lowest_bit_set); 1868 return; 1869 } 1870 1871 /* 1) sethi %hi(high_bits), %reg 1872 * or %reg, %lo(high_bits), %reg 1873 * sllx %reg, 32, %reg 1874 * or %reg, low_bits, %reg 1875 */ 1876 if (SPARC_SIMM13_P(low_bits) 1877 && ((int)low_bits > 0)) 1878 { 1879 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); 1880 return; 1881 } 1882 1883 /* The easiest way when all else fails, is full decomposition. */ 1884#if 0 1885 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n", 1886 high_bits, low_bits, ~high_bits, ~low_bits); 1887#endif 1888 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); 1889} 1890#endif /* HOST_BITS_PER_WIDE_INT == 32 */ 1891 1892/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1893 return the mode to be used for the comparison. For floating-point, 1894 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 1895 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 1896 processing is needed. */ 1897 1898enum machine_mode 1899select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED) 1900{ 1901 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 1902 { 1903 switch (op) 1904 { 1905 case EQ: 1906 case NE: 1907 case UNORDERED: 1908 case ORDERED: 1909 case UNLT: 1910 case UNLE: 1911 case UNGT: 1912 case UNGE: 1913 case UNEQ: 1914 case LTGT: 1915 return CCFPmode; 1916 1917 case LT: 1918 case LE: 1919 case GT: 1920 case GE: 1921 return CCFPEmode; 1922 1923 default: 1924 gcc_unreachable (); 1925 } 1926 } 1927 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS 1928 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) 1929 { 1930 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 1931 return CCX_NOOVmode; 1932 else 1933 return CC_NOOVmode; 1934 } 1935 else 1936 { 1937 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 1938 return CCXmode; 1939 else 1940 return CCmode; 1941 } 1942} 1943 1944/* X and Y are two things to compare using CODE. Emit the compare insn and 1945 return the rtx for the cc reg in the proper mode. */ 1946 1947rtx 1948gen_compare_reg (enum rtx_code code) 1949{ 1950 rtx x = sparc_compare_op0; 1951 rtx y = sparc_compare_op1; 1952 enum machine_mode mode = SELECT_CC_MODE (code, x, y); 1953 rtx cc_reg; 1954 1955 if (sparc_compare_emitted != NULL_RTX) 1956 { 1957 cc_reg = sparc_compare_emitted; 1958 sparc_compare_emitted = NULL_RTX; 1959 return cc_reg; 1960 } 1961 1962 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the 1963 fcc regs (cse can't tell they're really call clobbered regs and will 1964 remove a duplicate comparison even if there is an intervening function 1965 call - it will then try to reload the cc reg via an int reg which is why 1966 we need the movcc patterns). It is possible to provide the movcc 1967 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two 1968 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be 1969 to tell cse that CCFPE mode registers (even pseudos) are call 1970 clobbered. */ 1971 1972 /* ??? This is an experiment. Rather than making changes to cse which may 1973 or may not be easy/clean, we do our own cse. This is possible because 1974 we will generate hard registers. Cse knows they're call clobbered (it 1975 doesn't know the same thing about pseudos). If we guess wrong, no big 1976 deal, but if we win, great! */ 1977 1978 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 1979#if 1 /* experiment */ 1980 { 1981 int reg; 1982 /* We cycle through the registers to ensure they're all exercised. */ 1983 static int next_fcc_reg = 0; 1984 /* Previous x,y for each fcc reg. */ 1985 static rtx prev_args[4][2]; 1986 1987 /* Scan prev_args for x,y. */ 1988 for (reg = 0; reg < 4; reg++) 1989 if (prev_args[reg][0] == x && prev_args[reg][1] == y) 1990 break; 1991 if (reg == 4) 1992 { 1993 reg = next_fcc_reg; 1994 prev_args[reg][0] = x; 1995 prev_args[reg][1] = y; 1996 next_fcc_reg = (next_fcc_reg + 1) & 3; 1997 } 1998 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); 1999 } 2000#else 2001 cc_reg = gen_reg_rtx (mode); 2002#endif /* ! experiment */ 2003 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 2004 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); 2005 else 2006 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); 2007 2008 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, 2009 gen_rtx_COMPARE (mode, x, y))); 2010 2011 return cc_reg; 2012} 2013 2014/* This function is used for v9 only. 2015 CODE is the code for an Scc's comparison. 2016 OPERANDS[0] is the target of the Scc insn. 2017 OPERANDS[1] is the value we compare against const0_rtx (which hasn't 2018 been generated yet). 2019 2020 This function is needed to turn 2021 2022 (set (reg:SI 110) 2023 (gt (reg:CCX 100 %icc) 2024 (const_int 0))) 2025 into 2026 (set (reg:SI 110) 2027 (gt:DI (reg:CCX 100 %icc) 2028 (const_int 0))) 2029 2030 IE: The instruction recognizer needs to see the mode of the comparison to 2031 find the right instruction. We could use "gt:DI" right in the 2032 define_expand, but leaving it out allows us to handle DI, SI, etc. 2033 2034 We refer to the global sparc compare operands sparc_compare_op0 and 2035 sparc_compare_op1. */ 2036 2037int 2038gen_v9_scc (enum rtx_code compare_code, register rtx *operands) 2039{ 2040 if (! TARGET_ARCH64 2041 && (GET_MODE (sparc_compare_op0) == DImode 2042 || GET_MODE (operands[0]) == DImode)) 2043 return 0; 2044 2045 /* Try to use the movrCC insns. */ 2046 if (TARGET_ARCH64 2047 && GET_MODE_CLASS (GET_MODE (sparc_compare_op0)) == MODE_INT 2048 && sparc_compare_op1 == const0_rtx 2049 && v9_regcmp_p (compare_code)) 2050 { 2051 rtx op0 = sparc_compare_op0; 2052 rtx temp; 2053 2054 /* Special case for op0 != 0. This can be done with one instruction if 2055 operands[0] == sparc_compare_op0. */ 2056 2057 if (compare_code == NE 2058 && GET_MODE (operands[0]) == DImode 2059 && rtx_equal_p (op0, operands[0])) 2060 { 2061 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2062 gen_rtx_IF_THEN_ELSE (DImode, 2063 gen_rtx_fmt_ee (compare_code, DImode, 2064 op0, const0_rtx), 2065 const1_rtx, 2066 operands[0]))); 2067 return 1; 2068 } 2069 2070 if (reg_overlap_mentioned_p (operands[0], op0)) 2071 { 2072 /* Handle the case where operands[0] == sparc_compare_op0. 2073 We "early clobber" the result. */ 2074 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0)); 2075 emit_move_insn (op0, sparc_compare_op0); 2076 } 2077 2078 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); 2079 if (GET_MODE (op0) != DImode) 2080 { 2081 temp = gen_reg_rtx (DImode); 2082 convert_move (temp, op0, 0); 2083 } 2084 else 2085 temp = op0; 2086 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2087 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 2088 gen_rtx_fmt_ee (compare_code, DImode, 2089 temp, const0_rtx), 2090 const1_rtx, 2091 operands[0]))); 2092 return 1; 2093 } 2094 else 2095 { 2096 operands[1] = gen_compare_reg (compare_code); 2097 2098 switch (GET_MODE (operands[1])) 2099 { 2100 case CCmode : 2101 case CCXmode : 2102 case CCFPEmode : 2103 case CCFPmode : 2104 break; 2105 default : 2106 gcc_unreachable (); 2107 } 2108 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx)); 2109 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2110 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), 2111 gen_rtx_fmt_ee (compare_code, 2112 GET_MODE (operands[1]), 2113 operands[1], const0_rtx), 2114 const1_rtx, operands[0]))); 2115 return 1; 2116 } 2117} 2118 2119/* Emit a conditional jump insn for the v9 architecture using comparison code 2120 CODE and jump target LABEL. 2121 This function exists to take advantage of the v9 brxx insns. */ 2122 2123void 2124emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label) 2125{ 2126 gcc_assert (sparc_compare_emitted == NULL_RTX); 2127 emit_jump_insn (gen_rtx_SET (VOIDmode, 2128 pc_rtx, 2129 gen_rtx_IF_THEN_ELSE (VOIDmode, 2130 gen_rtx_fmt_ee (code, GET_MODE (op0), 2131 op0, const0_rtx), 2132 gen_rtx_LABEL_REF (VOIDmode, label), 2133 pc_rtx))); 2134} 2135 2136/* Generate a DFmode part of a hard TFmode register. 2137 REG is the TFmode hard register, LOW is 1 for the 2138 low 64bit of the register and 0 otherwise. 2139 */ 2140rtx 2141gen_df_reg (rtx reg, int low) 2142{ 2143 int regno = REGNO (reg); 2144 2145 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) 2146 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2; 2147 return gen_rtx_REG (DFmode, regno); 2148} 2149 2150/* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. 2151 Unlike normal calls, TFmode operands are passed by reference. It is 2152 assumed that no more than 3 operands are required. */ 2153 2154static void 2155emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands) 2156{ 2157 rtx ret_slot = NULL, arg[3], func_sym; 2158 int i; 2159 2160 /* We only expect to be called for conversions, unary, and binary ops. */ 2161 gcc_assert (nargs == 2 || nargs == 3); 2162 2163 for (i = 0; i < nargs; ++i) 2164 { 2165 rtx this_arg = operands[i]; 2166 rtx this_slot; 2167 2168 /* TFmode arguments and return values are passed by reference. */ 2169 if (GET_MODE (this_arg) == TFmode) 2170 { 2171 int force_stack_temp; 2172 2173 force_stack_temp = 0; 2174 if (TARGET_BUGGY_QP_LIB && i == 0) 2175 force_stack_temp = 1; 2176 2177 if (GET_CODE (this_arg) == MEM 2178 && ! force_stack_temp) 2179 this_arg = XEXP (this_arg, 0); 2180 else if (CONSTANT_P (this_arg) 2181 && ! force_stack_temp) 2182 { 2183 this_slot = force_const_mem (TFmode, this_arg); 2184 this_arg = XEXP (this_slot, 0); 2185 } 2186 else 2187 { 2188 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0); 2189 2190 /* Operand 0 is the return value. We'll copy it out later. */ 2191 if (i > 0) 2192 emit_move_insn (this_slot, this_arg); 2193 else 2194 ret_slot = this_slot; 2195 2196 this_arg = XEXP (this_slot, 0); 2197 } 2198 } 2199 2200 arg[i] = this_arg; 2201 } 2202 2203 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); 2204 2205 if (GET_MODE (operands[0]) == TFmode) 2206 { 2207 if (nargs == 2) 2208 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2, 2209 arg[0], GET_MODE (arg[0]), 2210 arg[1], GET_MODE (arg[1])); 2211 else 2212 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3, 2213 arg[0], GET_MODE (arg[0]), 2214 arg[1], GET_MODE (arg[1]), 2215 arg[2], GET_MODE (arg[2])); 2216 2217 if (ret_slot) 2218 emit_move_insn (operands[0], ret_slot); 2219 } 2220 else 2221 { 2222 rtx ret; 2223 2224 gcc_assert (nargs == 2); 2225 2226 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, 2227 GET_MODE (operands[0]), 1, 2228 arg[1], GET_MODE (arg[1])); 2229 2230 if (ret != operands[0]) 2231 emit_move_insn (operands[0], ret); 2232 } 2233} 2234 2235/* Expand soft-float TFmode calls to sparc abi routines. */ 2236 2237static void 2238emit_soft_tfmode_binop (enum rtx_code code, rtx *operands) 2239{ 2240 const char *func; 2241 2242 switch (code) 2243 { 2244 case PLUS: 2245 func = "_Qp_add"; 2246 break; 2247 case MINUS: 2248 func = "_Qp_sub"; 2249 break; 2250 case MULT: 2251 func = "_Qp_mul"; 2252 break; 2253 case DIV: 2254 func = "_Qp_div"; 2255 break; 2256 default: 2257 gcc_unreachable (); 2258 } 2259 2260 emit_soft_tfmode_libcall (func, 3, operands); 2261} 2262 2263static void 2264emit_soft_tfmode_unop (enum rtx_code code, rtx *operands) 2265{ 2266 const char *func; 2267 2268 gcc_assert (code == SQRT); 2269 func = "_Qp_sqrt"; 2270 2271 emit_soft_tfmode_libcall (func, 2, operands); 2272} 2273 2274static void 2275emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) 2276{ 2277 const char *func; 2278 2279 switch (code) 2280 { 2281 case FLOAT_EXTEND: 2282 switch (GET_MODE (operands[1])) 2283 { 2284 case SFmode: 2285 func = "_Qp_stoq"; 2286 break; 2287 case DFmode: 2288 func = "_Qp_dtoq"; 2289 break; 2290 default: 2291 gcc_unreachable (); 2292 } 2293 break; 2294 2295 case FLOAT_TRUNCATE: 2296 switch (GET_MODE (operands[0])) 2297 { 2298 case SFmode: 2299 func = "_Qp_qtos"; 2300 break; 2301 case DFmode: 2302 func = "_Qp_qtod"; 2303 break; 2304 default: 2305 gcc_unreachable (); 2306 } 2307 break; 2308 2309 case FLOAT: 2310 switch (GET_MODE (operands[1])) 2311 { 2312 case SImode: 2313 func = "_Qp_itoq"; 2314 break; 2315 case DImode: 2316 func = "_Qp_xtoq"; 2317 break; 2318 default: 2319 gcc_unreachable (); 2320 } 2321 break; 2322 2323 case UNSIGNED_FLOAT: 2324 switch (GET_MODE (operands[1])) 2325 { 2326 case SImode: 2327 func = "_Qp_uitoq"; 2328 break; 2329 case DImode: 2330 func = "_Qp_uxtoq"; 2331 break; 2332 default: 2333 gcc_unreachable (); 2334 } 2335 break; 2336 2337 case FIX: 2338 switch (GET_MODE (operands[0])) 2339 { 2340 case SImode: 2341 func = "_Qp_qtoi"; 2342 break; 2343 case DImode: 2344 func = "_Qp_qtox"; 2345 break; 2346 default: 2347 gcc_unreachable (); 2348 } 2349 break; 2350 2351 case UNSIGNED_FIX: 2352 switch (GET_MODE (operands[0])) 2353 { 2354 case SImode: 2355 func = "_Qp_qtoui"; 2356 break; 2357 case DImode: 2358 func = "_Qp_qtoux"; 2359 break; 2360 default: 2361 gcc_unreachable (); 2362 } 2363 break; 2364 2365 default: 2366 gcc_unreachable (); 2367 } 2368 2369 emit_soft_tfmode_libcall (func, 2, operands); 2370} 2371 2372/* Expand a hard-float tfmode operation. All arguments must be in 2373 registers. */ 2374 2375static void 2376emit_hard_tfmode_operation (enum rtx_code code, rtx *operands) 2377{ 2378 rtx op, dest; 2379 2380 if (GET_RTX_CLASS (code) == RTX_UNARY) 2381 { 2382 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 2383 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); 2384 } 2385 else 2386 { 2387 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 2388 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); 2389 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), 2390 operands[1], operands[2]); 2391 } 2392 2393 if (register_operand (operands[0], VOIDmode)) 2394 dest = operands[0]; 2395 else 2396 dest = gen_reg_rtx (GET_MODE (operands[0])); 2397 2398 emit_insn (gen_rtx_SET (VOIDmode, dest, op)); 2399 2400 if (dest != operands[0]) 2401 emit_move_insn (operands[0], dest); 2402} 2403 2404void 2405emit_tfmode_binop (enum rtx_code code, rtx *operands) 2406{ 2407 if (TARGET_HARD_QUAD) 2408 emit_hard_tfmode_operation (code, operands); 2409 else 2410 emit_soft_tfmode_binop (code, operands); 2411} 2412 2413void 2414emit_tfmode_unop (enum rtx_code code, rtx *operands) 2415{ 2416 if (TARGET_HARD_QUAD) 2417 emit_hard_tfmode_operation (code, operands); 2418 else 2419 emit_soft_tfmode_unop (code, operands); 2420} 2421 2422void 2423emit_tfmode_cvt (enum rtx_code code, rtx *operands) 2424{ 2425 if (TARGET_HARD_QUAD) 2426 emit_hard_tfmode_operation (code, operands); 2427 else 2428 emit_soft_tfmode_cvt (code, operands); 2429} 2430 2431/* Return nonzero if a branch/jump/call instruction will be emitting 2432 nop into its delay slot. */ 2433 2434int 2435empty_delay_slot (rtx insn) 2436{ 2437 rtx seq; 2438 2439 /* If no previous instruction (should not happen), return true. */ 2440 if (PREV_INSN (insn) == NULL) 2441 return 1; 2442 2443 seq = NEXT_INSN (PREV_INSN (insn)); 2444 if (GET_CODE (PATTERN (seq)) == SEQUENCE) 2445 return 0; 2446 2447 return 1; 2448} 2449 2450/* Return nonzero if TRIAL can go into the call delay slot. */ 2451 2452int 2453tls_call_delay (rtx trial) 2454{ 2455 rtx pat; 2456 2457 /* Binutils allows 2458 call __tls_get_addr, %tgd_call (foo) 2459 add %l7, %o0, %o0, %tgd_add (foo) 2460 while Sun as/ld does not. */ 2461 if (TARGET_GNU_TLS || !TARGET_TLS) 2462 return 1; 2463 2464 pat = PATTERN (trial); 2465 2466 /* We must reject tgd_add{32|64}, i.e. 2467 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD))) 2468 and tldm_add{32|64}, i.e. 2469 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM))) 2470 for Sun as/ld. */ 2471 if (GET_CODE (pat) == SET 2472 && GET_CODE (SET_SRC (pat)) == PLUS) 2473 { 2474 rtx unspec = XEXP (SET_SRC (pat), 1); 2475 2476 if (GET_CODE (unspec) == UNSPEC 2477 && (XINT (unspec, 1) == UNSPEC_TLSGD 2478 || XINT (unspec, 1) == UNSPEC_TLSLDM)) 2479 return 0; 2480 } 2481 2482 return 1; 2483} 2484 2485/* Return nonzero if TRIAL, an insn, can be combined with a 'restore' 2486 instruction. RETURN_P is true if the v9 variant 'return' is to be 2487 considered in the test too. 2488 2489 TRIAL must be a SET whose destination is a REG appropriate for the 2490 'restore' instruction or, if RETURN_P is true, for the 'return' 2491 instruction. */ 2492 2493static int 2494eligible_for_restore_insn (rtx trial, bool return_p) 2495{ 2496 rtx pat = PATTERN (trial); 2497 rtx src = SET_SRC (pat); 2498 2499 /* The 'restore src,%g0,dest' pattern for word mode and below. */ 2500 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2501 && arith_operand (src, GET_MODE (src))) 2502 { 2503 if (TARGET_ARCH64) 2504 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2505 else 2506 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); 2507 } 2508 2509 /* The 'restore src,%g0,dest' pattern for double-word mode. */ 2510 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 2511 && arith_double_operand (src, GET_MODE (src))) 2512 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 2513 2514 /* The 'restore src,%g0,dest' pattern for float if no FPU. */ 2515 else if (! TARGET_FPU && register_operand (src, SFmode)) 2516 return 1; 2517 2518 /* The 'restore src,%g0,dest' pattern for double if no FPU. */ 2519 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode)) 2520 return 1; 2521 2522 /* If we have the 'return' instruction, anything that does not use 2523 local or output registers and can go into a delay slot wins. */ 2524 else if (return_p && TARGET_V9 && ! epilogue_renumber (&pat, 1) 2525 && (get_attr_in_uncond_branch_delay (trial) 2526 == IN_UNCOND_BRANCH_DELAY_TRUE)) 2527 return 1; 2528 2529 /* The 'restore src1,src2,dest' pattern for SImode. */ 2530 else if (GET_CODE (src) == PLUS 2531 && register_operand (XEXP (src, 0), SImode) 2532 && arith_operand (XEXP (src, 1), SImode)) 2533 return 1; 2534 2535 /* The 'restore src1,src2,dest' pattern for DImode. */ 2536 else if (GET_CODE (src) == PLUS 2537 && register_operand (XEXP (src, 0), DImode) 2538 && arith_double_operand (XEXP (src, 1), DImode)) 2539 return 1; 2540 2541 /* The 'restore src1,%lo(src2),dest' pattern. */ 2542 else if (GET_CODE (src) == LO_SUM 2543 && ! TARGET_CM_MEDMID 2544 && ((register_operand (XEXP (src, 0), SImode) 2545 && immediate_operand (XEXP (src, 1), SImode)) 2546 || (TARGET_ARCH64 2547 && register_operand (XEXP (src, 0), DImode) 2548 && immediate_operand (XEXP (src, 1), DImode)))) 2549 return 1; 2550 2551 /* The 'restore src,src,dest' pattern. */ 2552 else if (GET_CODE (src) == ASHIFT 2553 && (register_operand (XEXP (src, 0), SImode) 2554 || register_operand (XEXP (src, 0), DImode)) 2555 && XEXP (src, 1) == const1_rtx) 2556 return 1; 2557 2558 return 0; 2559} 2560 2561/* Return nonzero if TRIAL can go into the function return's 2562 delay slot. */ 2563 2564int 2565eligible_for_return_delay (rtx trial) 2566{ 2567 rtx pat; 2568 2569 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) 2570 return 0; 2571 2572 if (get_attr_length (trial) != 1) 2573 return 0; 2574 2575 /* If there are any call-saved registers, we should scan TRIAL if it 2576 does not reference them. For now just make it easy. */ 2577 if (num_gfregs) 2578 return 0; 2579 2580 /* If the function uses __builtin_eh_return, the eh_return machinery 2581 occupies the delay slot. */ 2582 if (current_function_calls_eh_return) 2583 return 0; 2584 2585 /* In the case of a true leaf function, anything can go into the slot. */ 2586 if (sparc_leaf_function_p) 2587 return get_attr_in_uncond_branch_delay (trial) 2588 == IN_UNCOND_BRANCH_DELAY_TRUE; 2589 2590 pat = PATTERN (trial); 2591 2592 /* Otherwise, only operations which can be done in tandem with 2593 a `restore' or `return' insn can go into the delay slot. */ 2594 if (GET_CODE (SET_DEST (pat)) != REG 2595 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)) 2596 return 0; 2597 2598 /* If this instruction sets up floating point register and we have a return 2599 instruction, it can probably go in. But restore will not work 2600 with FP_REGS. */ 2601 if (REGNO (SET_DEST (pat)) >= 32) 2602 return (TARGET_V9 2603 && ! epilogue_renumber (&pat, 1) 2604 && (get_attr_in_uncond_branch_delay (trial) 2605 == IN_UNCOND_BRANCH_DELAY_TRUE)); 2606 2607 return eligible_for_restore_insn (trial, true); 2608} 2609 2610/* Return nonzero if TRIAL can go into the sibling call's 2611 delay slot. */ 2612 2613int 2614eligible_for_sibcall_delay (rtx trial) 2615{ 2616 rtx pat; 2617 2618 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) 2619 return 0; 2620 2621 if (get_attr_length (trial) != 1) 2622 return 0; 2623 2624 pat = PATTERN (trial); 2625 2626 if (sparc_leaf_function_p) 2627 { 2628 /* If the tail call is done using the call instruction, 2629 we have to restore %o7 in the delay slot. */ 2630 if (LEAF_SIBCALL_SLOT_RESERVED_P) 2631 return 0; 2632 2633 /* %g1 is used to build the function address */ 2634 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) 2635 return 0; 2636 2637 return 1; 2638 } 2639 2640 /* Otherwise, only operations which can be done in tandem with 2641 a `restore' insn can go into the delay slot. */ 2642 if (GET_CODE (SET_DEST (pat)) != REG 2643 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24) 2644 || REGNO (SET_DEST (pat)) >= 32) 2645 return 0; 2646 2647 /* If it mentions %o7, it can't go in, because sibcall will clobber it 2648 in most cases. */ 2649 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) 2650 return 0; 2651 2652 return eligible_for_restore_insn (trial, false); 2653} 2654 2655int 2656short_branch (int uid1, int uid2) 2657{ 2658 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2); 2659 2660 /* Leave a few words of "slop". */ 2661 if (delta >= -1023 && delta <= 1022) 2662 return 1; 2663 2664 return 0; 2665} 2666 2667/* Return nonzero if REG is not used after INSN. 2668 We assume REG is a reload reg, and therefore does 2669 not live past labels or calls or jumps. */ 2670int 2671reg_unused_after (rtx reg, rtx insn) 2672{ 2673 enum rtx_code code, prev_code = UNKNOWN; 2674 2675 while ((insn = NEXT_INSN (insn))) 2676 { 2677 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)]) 2678 return 1; 2679 2680 code = GET_CODE (insn); 2681 if (GET_CODE (insn) == CODE_LABEL) 2682 return 1; 2683 2684 if (INSN_P (insn)) 2685 { 2686 rtx set = single_set (insn); 2687 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set)); 2688 if (set && in_src) 2689 return 0; 2690 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set))) 2691 return 1; 2692 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn))) 2693 return 0; 2694 } 2695 prev_code = code; 2696 } 2697 return 1; 2698} 2699 2700/* Determine if it's legal to put X into the constant pool. This 2701 is not possible if X contains the address of a symbol that is 2702 not constant (TLS) or not known at final link time (PIC). */ 2703 2704static bool 2705sparc_cannot_force_const_mem (rtx x) 2706{ 2707 switch (GET_CODE (x)) 2708 { 2709 case CONST_INT: 2710 case CONST_DOUBLE: 2711 case CONST_VECTOR: 2712 /* Accept all non-symbolic constants. */ 2713 return false; 2714 2715 case LABEL_REF: 2716 /* Labels are OK iff we are non-PIC. */ 2717 return flag_pic != 0; 2718 2719 case SYMBOL_REF: 2720 /* 'Naked' TLS symbol references are never OK, 2721 non-TLS symbols are OK iff we are non-PIC. */ 2722 if (SYMBOL_REF_TLS_MODEL (x)) 2723 return true; 2724 else 2725 return flag_pic != 0; 2726 2727 case CONST: 2728 return sparc_cannot_force_const_mem (XEXP (x, 0)); 2729 case PLUS: 2730 case MINUS: 2731 return sparc_cannot_force_const_mem (XEXP (x, 0)) 2732 || sparc_cannot_force_const_mem (XEXP (x, 1)); 2733 case UNSPEC: 2734 return true; 2735 default: 2736 gcc_unreachable (); 2737 } 2738} 2739 2740/* PIC support. */ 2741static GTY(()) char pic_helper_symbol_name[256]; 2742static GTY(()) rtx pic_helper_symbol; 2743static GTY(()) bool pic_helper_emitted_p = false; 2744static GTY(()) rtx global_offset_table; 2745 2746/* Ensure that we are not using patterns that are not OK with PIC. */ 2747 2748int 2749check_pic (int i) 2750{ 2751 switch (flag_pic) 2752 { 2753 case 1: 2754 gcc_assert (GET_CODE (recog_data.operand[i]) != SYMBOL_REF 2755 && (GET_CODE (recog_data.operand[i]) != CONST 2756 || (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS 2757 && (XEXP (XEXP (recog_data.operand[i], 0), 0) 2758 == global_offset_table) 2759 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1)) 2760 == CONST)))); 2761 case 2: 2762 default: 2763 return 1; 2764 } 2765} 2766 2767/* Return true if X is an address which needs a temporary register when 2768 reloaded while generating PIC code. */ 2769 2770int 2771pic_address_needs_scratch (rtx x) 2772{ 2773 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ 2774 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS 2775 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 2776 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 2777 && ! SMALL_INT (XEXP (XEXP (x, 0), 1))) 2778 return 1; 2779 2780 return 0; 2781} 2782 2783/* Determine if a given RTX is a valid constant. We already know this 2784 satisfies CONSTANT_P. */ 2785 2786bool 2787legitimate_constant_p (rtx x) 2788{ 2789 rtx inner; 2790 2791 switch (GET_CODE (x)) 2792 { 2793 case SYMBOL_REF: 2794 /* TLS symbols are not constant. */ 2795 if (SYMBOL_REF_TLS_MODEL (x)) 2796 return false; 2797 break; 2798 2799 case CONST: 2800 inner = XEXP (x, 0); 2801 2802 /* Offsets of TLS symbols are never valid. 2803 Discourage CSE from creating them. */ 2804 if (GET_CODE (inner) == PLUS 2805 && SPARC_SYMBOL_REF_TLS_P (XEXP (inner, 0))) 2806 return false; 2807 break; 2808 2809 case CONST_DOUBLE: 2810 if (GET_MODE (x) == VOIDmode) 2811 return true; 2812 2813 /* Floating point constants are generally not ok. 2814 The only exception is 0.0 in VIS. */ 2815 if (TARGET_VIS 2816 && SCALAR_FLOAT_MODE_P (GET_MODE (x)) 2817 && const_zero_operand (x, GET_MODE (x))) 2818 return true; 2819 2820 return false; 2821 2822 case CONST_VECTOR: 2823 /* Vector constants are generally not ok. 2824 The only exception is 0 in VIS. */ 2825 if (TARGET_VIS 2826 && const_zero_operand (x, GET_MODE (x))) 2827 return true; 2828 2829 return false; 2830 2831 default: 2832 break; 2833 } 2834 2835 return true; 2836} 2837 2838/* Determine if a given RTX is a valid constant address. */ 2839 2840bool 2841constant_address_p (rtx x) 2842{ 2843 switch (GET_CODE (x)) 2844 { 2845 case LABEL_REF: 2846 case CONST_INT: 2847 case HIGH: 2848 return true; 2849 2850 case CONST: 2851 if (flag_pic && pic_address_needs_scratch (x)) 2852 return false; 2853 return legitimate_constant_p (x); 2854 2855 case SYMBOL_REF: 2856 return !flag_pic && legitimate_constant_p (x); 2857 2858 default: 2859 return false; 2860 } 2861} 2862 2863/* Nonzero if the constant value X is a legitimate general operand 2864 when generating PIC code. It is given that flag_pic is on and 2865 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 2866 2867bool 2868legitimate_pic_operand_p (rtx x) 2869{ 2870 if (pic_address_needs_scratch (x)) 2871 return false; 2872 if (SPARC_SYMBOL_REF_TLS_P (x) 2873 || (GET_CODE (x) == CONST 2874 && GET_CODE (XEXP (x, 0)) == PLUS 2875 && SPARC_SYMBOL_REF_TLS_P (XEXP (XEXP (x, 0), 0)))) 2876 return false; 2877 return true; 2878} 2879 2880/* Return nonzero if ADDR is a valid memory address. 2881 STRICT specifies whether strict register checking applies. */ 2882 2883int 2884legitimate_address_p (enum machine_mode mode, rtx addr, int strict) 2885{ 2886 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL; 2887 2888 if (REG_P (addr) || GET_CODE (addr) == SUBREG) 2889 rs1 = addr; 2890 else if (GET_CODE (addr) == PLUS) 2891 { 2892 rs1 = XEXP (addr, 0); 2893 rs2 = XEXP (addr, 1); 2894 2895 /* Canonicalize. REG comes first, if there are no regs, 2896 LO_SUM comes first. */ 2897 if (!REG_P (rs1) 2898 && GET_CODE (rs1) != SUBREG 2899 && (REG_P (rs2) 2900 || GET_CODE (rs2) == SUBREG 2901 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM))) 2902 { 2903 rs1 = XEXP (addr, 1); 2904 rs2 = XEXP (addr, 0); 2905 } 2906 2907 if ((flag_pic == 1 2908 && rs1 == pic_offset_table_rtx 2909 && !REG_P (rs2) 2910 && GET_CODE (rs2) != SUBREG 2911 && GET_CODE (rs2) != LO_SUM 2912 && GET_CODE (rs2) != MEM 2913 && ! SPARC_SYMBOL_REF_TLS_P (rs2) 2914 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode) 2915 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2))) 2916 || ((REG_P (rs1) 2917 || GET_CODE (rs1) == SUBREG) 2918 && RTX_OK_FOR_OFFSET_P (rs2))) 2919 { 2920 imm1 = rs2; 2921 rs2 = NULL; 2922 } 2923 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG) 2924 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG)) 2925 { 2926 /* We prohibit REG + REG for TFmode when there are no quad move insns 2927 and we consequently need to split. We do this because REG+REG 2928 is not an offsettable address. If we get the situation in reload 2929 where source and destination of a movtf pattern are both MEMs with 2930 REG+REG address, then only one of them gets converted to an 2931 offsettable address. */ 2932 if (mode == TFmode 2933 && ! (TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD)) 2934 return 0; 2935 2936 /* We prohibit REG + REG on ARCH32 if not optimizing for 2937 DFmode/DImode because then mem_min_alignment is likely to be zero 2938 after reload and the forced split would lack a matching splitter 2939 pattern. */ 2940 if (TARGET_ARCH32 && !optimize 2941 && (mode == DFmode || mode == DImode)) 2942 return 0; 2943 } 2944 else if (USE_AS_OFFSETABLE_LO10 2945 && GET_CODE (rs1) == LO_SUM 2946 && TARGET_ARCH64 2947 && ! TARGET_CM_MEDMID 2948 && RTX_OK_FOR_OLO10_P (rs2)) 2949 { 2950 rs2 = NULL; 2951 imm1 = XEXP (rs1, 1); 2952 rs1 = XEXP (rs1, 0); 2953 if (! CONSTANT_P (imm1) || SPARC_SYMBOL_REF_TLS_P (rs1)) 2954 return 0; 2955 } 2956 } 2957 else if (GET_CODE (addr) == LO_SUM) 2958 { 2959 rs1 = XEXP (addr, 0); 2960 imm1 = XEXP (addr, 1); 2961 2962 if (! CONSTANT_P (imm1) || SPARC_SYMBOL_REF_TLS_P (rs1)) 2963 return 0; 2964 2965 /* We can't allow TFmode in 32-bit mode, because an offset greater 2966 than the alignment (8) may cause the LO_SUM to overflow. */ 2967 if (mode == TFmode && TARGET_ARCH32) 2968 return 0; 2969 } 2970 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr)) 2971 return 1; 2972 else 2973 return 0; 2974 2975 if (GET_CODE (rs1) == SUBREG) 2976 rs1 = SUBREG_REG (rs1); 2977 if (!REG_P (rs1)) 2978 return 0; 2979 2980 if (rs2) 2981 { 2982 if (GET_CODE (rs2) == SUBREG) 2983 rs2 = SUBREG_REG (rs2); 2984 if (!REG_P (rs2)) 2985 return 0; 2986 } 2987 2988 if (strict) 2989 { 2990 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1)) 2991 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2)))) 2992 return 0; 2993 } 2994 else 2995 { 2996 if ((REGNO (rs1) >= 32 2997 && REGNO (rs1) != FRAME_POINTER_REGNUM 2998 && REGNO (rs1) < FIRST_PSEUDO_REGISTER) 2999 || (rs2 3000 && (REGNO (rs2) >= 32 3001 && REGNO (rs2) != FRAME_POINTER_REGNUM 3002 && REGNO (rs2) < FIRST_PSEUDO_REGISTER))) 3003 return 0; 3004 } 3005 return 1; 3006} 3007 3008/* Construct the SYMBOL_REF for the tls_get_offset function. */ 3009 3010static GTY(()) rtx sparc_tls_symbol; 3011 3012static rtx 3013sparc_tls_get_addr (void) 3014{ 3015 if (!sparc_tls_symbol) 3016 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr"); 3017 3018 return sparc_tls_symbol; 3019} 3020 3021static rtx 3022sparc_tls_got (void) 3023{ 3024 rtx temp; 3025 if (flag_pic) 3026 { 3027 current_function_uses_pic_offset_table = 1; 3028 return pic_offset_table_rtx; 3029 } 3030 3031 if (!global_offset_table) 3032 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 3033 temp = gen_reg_rtx (Pmode); 3034 emit_move_insn (temp, global_offset_table); 3035 return temp; 3036} 3037 3038/* Return 1 if *X is a thread-local symbol. */ 3039 3040static int 3041sparc_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) 3042{ 3043 return SPARC_SYMBOL_REF_TLS_P (*x); 3044} 3045 3046/* Return 1 if X contains a thread-local symbol. */ 3047 3048bool 3049sparc_tls_referenced_p (rtx x) 3050{ 3051 if (!TARGET_HAVE_TLS) 3052 return false; 3053 3054 return for_each_rtx (&x, &sparc_tls_symbol_ref_1, 0); 3055} 3056 3057/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute 3058 this (thread-local) address. */ 3059 3060rtx 3061legitimize_tls_address (rtx addr) 3062{ 3063 rtx temp1, temp2, temp3, ret, o0, got, insn; 3064 3065 gcc_assert (! no_new_pseudos); 3066 3067 if (GET_CODE (addr) == SYMBOL_REF) 3068 switch (SYMBOL_REF_TLS_MODEL (addr)) 3069 { 3070 case TLS_MODEL_GLOBAL_DYNAMIC: 3071 start_sequence (); 3072 temp1 = gen_reg_rtx (SImode); 3073 temp2 = gen_reg_rtx (SImode); 3074 ret = gen_reg_rtx (Pmode); 3075 o0 = gen_rtx_REG (Pmode, 8); 3076 got = sparc_tls_got (); 3077 emit_insn (gen_tgd_hi22 (temp1, addr)); 3078 emit_insn (gen_tgd_lo10 (temp2, temp1, addr)); 3079 if (TARGET_ARCH32) 3080 { 3081 emit_insn (gen_tgd_add32 (o0, got, temp2, addr)); 3082 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (), 3083 addr, const1_rtx)); 3084 } 3085 else 3086 { 3087 emit_insn (gen_tgd_add64 (o0, got, temp2, addr)); 3088 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (), 3089 addr, const1_rtx)); 3090 } 3091 CALL_INSN_FUNCTION_USAGE (insn) 3092 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0), 3093 CALL_INSN_FUNCTION_USAGE (insn)); 3094 insn = get_insns (); 3095 end_sequence (); 3096 emit_libcall_block (insn, ret, o0, addr); 3097 break; 3098 3099 case TLS_MODEL_LOCAL_DYNAMIC: 3100 start_sequence (); 3101 temp1 = gen_reg_rtx (SImode); 3102 temp2 = gen_reg_rtx (SImode); 3103 temp3 = gen_reg_rtx (Pmode); 3104 ret = gen_reg_rtx (Pmode); 3105 o0 = gen_rtx_REG (Pmode, 8); 3106 got = sparc_tls_got (); 3107 emit_insn (gen_tldm_hi22 (temp1)); 3108 emit_insn (gen_tldm_lo10 (temp2, temp1)); 3109 if (TARGET_ARCH32) 3110 { 3111 emit_insn (gen_tldm_add32 (o0, got, temp2)); 3112 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (), 3113 const1_rtx)); 3114 } 3115 else 3116 { 3117 emit_insn (gen_tldm_add64 (o0, got, temp2)); 3118 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (), 3119 const1_rtx)); 3120 } 3121 CALL_INSN_FUNCTION_USAGE (insn) 3122 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0), 3123 CALL_INSN_FUNCTION_USAGE (insn)); 3124 insn = get_insns (); 3125 end_sequence (); 3126 emit_libcall_block (insn, temp3, o0, 3127 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), 3128 UNSPEC_TLSLD_BASE)); 3129 temp1 = gen_reg_rtx (SImode); 3130 temp2 = gen_reg_rtx (SImode); 3131 emit_insn (gen_tldo_hix22 (temp1, addr)); 3132 emit_insn (gen_tldo_lox10 (temp2, temp1, addr)); 3133 if (TARGET_ARCH32) 3134 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr)); 3135 else 3136 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr)); 3137 break; 3138 3139 case TLS_MODEL_INITIAL_EXEC: 3140 temp1 = gen_reg_rtx (SImode); 3141 temp2 = gen_reg_rtx (SImode); 3142 temp3 = gen_reg_rtx (Pmode); 3143 got = sparc_tls_got (); 3144 emit_insn (gen_tie_hi22 (temp1, addr)); 3145 emit_insn (gen_tie_lo10 (temp2, temp1, addr)); 3146 if (TARGET_ARCH32) 3147 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr)); 3148 else 3149 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr)); 3150 if (TARGET_SUN_TLS) 3151 { 3152 ret = gen_reg_rtx (Pmode); 3153 if (TARGET_ARCH32) 3154 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7), 3155 temp3, addr)); 3156 else 3157 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7), 3158 temp3, addr)); 3159 } 3160 else 3161 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3); 3162 break; 3163 3164 case TLS_MODEL_LOCAL_EXEC: 3165 temp1 = gen_reg_rtx (Pmode); 3166 temp2 = gen_reg_rtx (Pmode); 3167 if (TARGET_ARCH32) 3168 { 3169 emit_insn (gen_tle_hix22_sp32 (temp1, addr)); 3170 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr)); 3171 } 3172 else 3173 { 3174 emit_insn (gen_tle_hix22_sp64 (temp1, addr)); 3175 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr)); 3176 } 3177 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2); 3178 break; 3179 3180 default: 3181 gcc_unreachable (); 3182 } 3183 3184 else 3185 gcc_unreachable (); /* for now ... */ 3186 3187 return ret; 3188} 3189 3190 3191/* Legitimize PIC addresses. If the address is already position-independent, 3192 we return ORIG. Newly generated position-independent addresses go into a 3193 reg. This is REG if nonzero, otherwise we allocate register(s) as 3194 necessary. */ 3195 3196rtx 3197legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, 3198 rtx reg) 3199{ 3200 if (GET_CODE (orig) == SYMBOL_REF) 3201 { 3202 rtx pic_ref, address; 3203 rtx insn; 3204 3205 if (reg == 0) 3206 { 3207 gcc_assert (! reload_in_progress && ! reload_completed); 3208 reg = gen_reg_rtx (Pmode); 3209 } 3210 3211 if (flag_pic == 2) 3212 { 3213 /* If not during reload, allocate another temp reg here for loading 3214 in the address, so that these instructions can be optimized 3215 properly. */ 3216 rtx temp_reg = ((reload_in_progress || reload_completed) 3217 ? reg : gen_reg_rtx (Pmode)); 3218 3219 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse 3220 won't get confused into thinking that these two instructions 3221 are loading in the true address of the symbol. If in the 3222 future a PIC rtx exists, that should be used instead. */ 3223 if (TARGET_ARCH64) 3224 { 3225 emit_insn (gen_movdi_high_pic (temp_reg, orig)); 3226 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); 3227 } 3228 else 3229 { 3230 emit_insn (gen_movsi_high_pic (temp_reg, orig)); 3231 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); 3232 } 3233 address = temp_reg; 3234 } 3235 else 3236 address = orig; 3237 3238 pic_ref = gen_const_mem (Pmode, 3239 gen_rtx_PLUS (Pmode, 3240 pic_offset_table_rtx, address)); 3241 current_function_uses_pic_offset_table = 1; 3242 insn = emit_move_insn (reg, pic_ref); 3243 /* Put a REG_EQUAL note on this insn, so that it can be optimized 3244 by loop. */ 3245 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, 3246 REG_NOTES (insn)); 3247 return reg; 3248 } 3249 else if (GET_CODE (orig) == CONST) 3250 { 3251 rtx base, offset; 3252 3253 if (GET_CODE (XEXP (orig, 0)) == PLUS 3254 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) 3255 return orig; 3256 3257 if (reg == 0) 3258 { 3259 gcc_assert (! reload_in_progress && ! reload_completed); 3260 reg = gen_reg_rtx (Pmode); 3261 } 3262 3263 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); 3264 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); 3265 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, 3266 base == reg ? 0 : reg); 3267 3268 if (GET_CODE (offset) == CONST_INT) 3269 { 3270 if (SMALL_INT (offset)) 3271 return plus_constant (base, INTVAL (offset)); 3272 else if (! reload_in_progress && ! reload_completed) 3273 offset = force_reg (Pmode, offset); 3274 else 3275 /* If we reach here, then something is seriously wrong. */ 3276 gcc_unreachable (); 3277 } 3278 return gen_rtx_PLUS (Pmode, base, offset); 3279 } 3280 else if (GET_CODE (orig) == LABEL_REF) 3281 /* ??? Why do we do this? */ 3282 /* Now movsi_pic_label_ref uses it, but we ought to be checking that 3283 the register is live instead, in case it is eliminated. */ 3284 current_function_uses_pic_offset_table = 1; 3285 3286 return orig; 3287} 3288 3289/* Try machine-dependent ways of modifying an illegitimate address X 3290 to be legitimate. If we find one, return the new, valid address. 3291 3292 OLDX is the address as it was before break_out_memory_refs was called. 3293 In some cases it is useful to look at this to decide what needs to be done. 3294 3295 MODE is the mode of the operand pointed to by X. */ 3296 3297rtx 3298legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode) 3299{ 3300 rtx orig_x = x; 3301 3302 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT) 3303 x = gen_rtx_PLUS (Pmode, XEXP (x, 1), 3304 force_operand (XEXP (x, 0), NULL_RTX)); 3305 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT) 3306 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), 3307 force_operand (XEXP (x, 1), NULL_RTX)); 3308 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS) 3309 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX), 3310 XEXP (x, 1)); 3311 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS) 3312 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), 3313 force_operand (XEXP (x, 1), NULL_RTX)); 3314 3315 if (x != orig_x && legitimate_address_p (mode, x, FALSE)) 3316 return x; 3317 3318 if (SPARC_SYMBOL_REF_TLS_P (x)) 3319 x = legitimize_tls_address (x); 3320 else if (flag_pic) 3321 x = legitimize_pic_address (x, mode, 0); 3322 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1))) 3323 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), 3324 copy_to_mode_reg (Pmode, XEXP (x, 1))); 3325 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0))) 3326 x = gen_rtx_PLUS (Pmode, XEXP (x, 1), 3327 copy_to_mode_reg (Pmode, XEXP (x, 0))); 3328 else if (GET_CODE (x) == SYMBOL_REF 3329 || GET_CODE (x) == CONST 3330 || GET_CODE (x) == LABEL_REF) 3331 x = copy_to_suggested_reg (x, NULL_RTX, Pmode); 3332 return x; 3333} 3334 3335/* Emit the special PIC helper function. */ 3336 3337static void 3338emit_pic_helper (void) 3339{ 3340 const char *pic_name = reg_names[REGNO (pic_offset_table_rtx)]; 3341 int align; 3342 3343 switch_to_section (text_section); 3344 3345 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 3346 if (align > 0) 3347 ASM_OUTPUT_ALIGN (asm_out_file, align); 3348 ASM_OUTPUT_LABEL (asm_out_file, pic_helper_symbol_name); 3349 if (flag_delayed_branch) 3350 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n", 3351 pic_name, pic_name); 3352 else 3353 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n", 3354 pic_name, pic_name); 3355 3356 pic_helper_emitted_p = true; 3357} 3358 3359/* Emit code to load the PIC register. */ 3360 3361static void 3362load_pic_register (bool delay_pic_helper) 3363{ 3364 int orig_flag_pic = flag_pic; 3365 3366 /* If we haven't initialized the special PIC symbols, do so now. */ 3367 if (!pic_helper_symbol_name[0]) 3368 { 3369 ASM_GENERATE_INTERNAL_LABEL (pic_helper_symbol_name, "LADDPC", 0); 3370 pic_helper_symbol = gen_rtx_SYMBOL_REF (Pmode, pic_helper_symbol_name); 3371 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 3372 } 3373 3374 /* If we haven't emitted the special PIC helper function, do so now unless 3375 we are requested to delay it. */ 3376 if (!delay_pic_helper && !pic_helper_emitted_p) 3377 emit_pic_helper (); 3378 3379 flag_pic = 0; 3380 if (TARGET_ARCH64) 3381 emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx, global_offset_table, 3382 pic_helper_symbol)); 3383 else 3384 emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx, global_offset_table, 3385 pic_helper_symbol)); 3386 flag_pic = orig_flag_pic; 3387 3388 /* Need to emit this whether or not we obey regdecls, 3389 since setjmp/longjmp can cause life info to screw up. 3390 ??? In the case where we don't obey regdecls, this is not sufficient 3391 since we may not fall out the bottom. */ 3392 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); 3393} 3394 3395/* Return 1 if RTX is a MEM which is known to be aligned to at 3396 least a DESIRED byte boundary. */ 3397 3398int 3399mem_min_alignment (rtx mem, int desired) 3400{ 3401 rtx addr, base, offset; 3402 3403 /* If it's not a MEM we can't accept it. */ 3404 if (GET_CODE (mem) != MEM) 3405 return 0; 3406 3407 /* Obviously... */ 3408 if (!TARGET_UNALIGNED_DOUBLES 3409 && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired) 3410 return 1; 3411 3412 /* ??? The rest of the function predates MEM_ALIGN so 3413 there is probably a bit of redundancy. */ 3414 addr = XEXP (mem, 0); 3415 base = offset = NULL_RTX; 3416 if (GET_CODE (addr) == PLUS) 3417 { 3418 if (GET_CODE (XEXP (addr, 0)) == REG) 3419 { 3420 base = XEXP (addr, 0); 3421 3422 /* What we are saying here is that if the base 3423 REG is aligned properly, the compiler will make 3424 sure any REG based index upon it will be so 3425 as well. */ 3426 if (GET_CODE (XEXP (addr, 1)) == CONST_INT) 3427 offset = XEXP (addr, 1); 3428 else 3429 offset = const0_rtx; 3430 } 3431 } 3432 else if (GET_CODE (addr) == REG) 3433 { 3434 base = addr; 3435 offset = const0_rtx; 3436 } 3437 3438 if (base != NULL_RTX) 3439 { 3440 int regno = REGNO (base); 3441 3442 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) 3443 { 3444 /* Check if the compiler has recorded some information 3445 about the alignment of the base REG. If reload has 3446 completed, we already matched with proper alignments. 3447 If not running global_alloc, reload might give us 3448 unaligned pointer to local stack though. */ 3449 if (((cfun != 0 3450 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) 3451 || (optimize && reload_completed)) 3452 && (INTVAL (offset) & (desired - 1)) == 0) 3453 return 1; 3454 } 3455 else 3456 { 3457 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) 3458 return 1; 3459 } 3460 } 3461 else if (! TARGET_UNALIGNED_DOUBLES 3462 || CONSTANT_P (addr) 3463 || GET_CODE (addr) == LO_SUM) 3464 { 3465 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES 3466 is true, in which case we can only assume that an access is aligned if 3467 it is to a constant address, or the address involves a LO_SUM. */ 3468 return 1; 3469 } 3470 3471 /* An obviously unaligned address. */ 3472 return 0; 3473} 3474 3475 3476/* Vectors to keep interesting information about registers where it can easily 3477 be got. We used to use the actual mode value as the bit number, but there 3478 are more than 32 modes now. Instead we use two tables: one indexed by 3479 hard register number, and one indexed by mode. */ 3480 3481/* The purpose of sparc_mode_class is to shrink the range of modes so that 3482 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is 3483 mapped into one sparc_mode_class mode. */ 3484 3485enum sparc_mode_class { 3486 S_MODE, D_MODE, T_MODE, O_MODE, 3487 SF_MODE, DF_MODE, TF_MODE, OF_MODE, 3488 CC_MODE, CCFP_MODE 3489}; 3490 3491/* Modes for single-word and smaller quantities. */ 3492#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) 3493 3494/* Modes for double-word and smaller quantities. */ 3495#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) 3496 3497/* Modes for quad-word and smaller quantities. */ 3498#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) 3499 3500/* Modes for 8-word and smaller quantities. */ 3501#define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) 3502 3503/* Modes for single-float quantities. We must allow any single word or 3504 smaller quantity. This is because the fix/float conversion instructions 3505 take integer inputs/outputs from the float registers. */ 3506#define SF_MODES (S_MODES) 3507 3508/* Modes for double-float and smaller quantities. */ 3509#define DF_MODES (S_MODES | D_MODES) 3510 3511/* Modes for double-float only quantities. */ 3512#define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) 3513 3514/* Modes for quad-float only quantities. */ 3515#define TF_ONLY_MODES (1 << (int) TF_MODE) 3516 3517/* Modes for quad-float and smaller quantities. */ 3518#define TF_MODES (DF_MODES | TF_ONLY_MODES) 3519 3520/* Modes for quad-float and double-float quantities. */ 3521#define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES) 3522 3523/* Modes for quad-float pair only quantities. */ 3524#define OF_ONLY_MODES (1 << (int) OF_MODE) 3525 3526/* Modes for quad-float pairs and smaller quantities. */ 3527#define OF_MODES (TF_MODES | OF_ONLY_MODES) 3528 3529#define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES) 3530 3531/* Modes for condition codes. */ 3532#define CC_MODES (1 << (int) CC_MODE) 3533#define CCFP_MODES (1 << (int) CCFP_MODE) 3534 3535/* Value is 1 if register/mode pair is acceptable on sparc. 3536 The funny mixture of D and T modes is because integer operations 3537 do not specially operate on tetra quantities, so non-quad-aligned 3538 registers can hold quadword quantities (except %o4 and %i4 because 3539 they cross fixed registers). */ 3540 3541/* This points to either the 32 bit or the 64 bit version. */ 3542const int *hard_regno_mode_classes; 3543 3544static const int hard_32bit_mode_classes[] = { 3545 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 3546 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 3547 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 3548 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 3549 3550 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3551 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3552 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3553 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 3554 3555 /* FP regs f32 to f63. Only the even numbered registers actually exist, 3556 and none can hold SFmode/SImode values. */ 3557 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3558 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3559 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3560 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3561 3562 /* %fcc[0123] */ 3563 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 3564 3565 /* %icc */ 3566 CC_MODES 3567}; 3568 3569static const int hard_64bit_mode_classes[] = { 3570 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3571 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3572 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3573 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 3574 3575 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3576 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3577 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 3578 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 3579 3580 /* FP regs f32 to f63. Only the even numbered registers actually exist, 3581 and none can hold SFmode/SImode values. */ 3582 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3583 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3584 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3585 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 3586 3587 /* %fcc[0123] */ 3588 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 3589 3590 /* %icc */ 3591 CC_MODES 3592}; 3593 3594int sparc_mode_class [NUM_MACHINE_MODES]; 3595 3596enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 3597 3598static void 3599sparc_init_modes (void) 3600{ 3601 int i; 3602 3603 for (i = 0; i < NUM_MACHINE_MODES; i++) 3604 { 3605 switch (GET_MODE_CLASS (i)) 3606 { 3607 case MODE_INT: 3608 case MODE_PARTIAL_INT: 3609 case MODE_COMPLEX_INT: 3610 if (GET_MODE_SIZE (i) <= 4) 3611 sparc_mode_class[i] = 1 << (int) S_MODE; 3612 else if (GET_MODE_SIZE (i) == 8) 3613 sparc_mode_class[i] = 1 << (int) D_MODE; 3614 else if (GET_MODE_SIZE (i) == 16) 3615 sparc_mode_class[i] = 1 << (int) T_MODE; 3616 else if (GET_MODE_SIZE (i) == 32) 3617 sparc_mode_class[i] = 1 << (int) O_MODE; 3618 else 3619 sparc_mode_class[i] = 0; 3620 break; 3621 case MODE_VECTOR_INT: 3622 if (GET_MODE_SIZE (i) <= 4) 3623 sparc_mode_class[i] = 1 << (int)SF_MODE; 3624 else if (GET_MODE_SIZE (i) == 8) 3625 sparc_mode_class[i] = 1 << (int)DF_MODE; 3626 break; 3627 case MODE_FLOAT: 3628 case MODE_COMPLEX_FLOAT: 3629 if (GET_MODE_SIZE (i) <= 4) 3630 sparc_mode_class[i] = 1 << (int) SF_MODE; 3631 else if (GET_MODE_SIZE (i) == 8) 3632 sparc_mode_class[i] = 1 << (int) DF_MODE; 3633 else if (GET_MODE_SIZE (i) == 16) 3634 sparc_mode_class[i] = 1 << (int) TF_MODE; 3635 else if (GET_MODE_SIZE (i) == 32) 3636 sparc_mode_class[i] = 1 << (int) OF_MODE; 3637 else 3638 sparc_mode_class[i] = 0; 3639 break; 3640 case MODE_CC: 3641 if (i == (int) CCFPmode || i == (int) CCFPEmode) 3642 sparc_mode_class[i] = 1 << (int) CCFP_MODE; 3643 else 3644 sparc_mode_class[i] = 1 << (int) CC_MODE; 3645 break; 3646 default: 3647 sparc_mode_class[i] = 0; 3648 break; 3649 } 3650 } 3651 3652 if (TARGET_ARCH64) 3653 hard_regno_mode_classes = hard_64bit_mode_classes; 3654 else 3655 hard_regno_mode_classes = hard_32bit_mode_classes; 3656 3657 /* Initialize the array used by REGNO_REG_CLASS. */ 3658 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3659 { 3660 if (i < 16 && TARGET_V8PLUS) 3661 sparc_regno_reg_class[i] = I64_REGS; 3662 else if (i < 32 || i == FRAME_POINTER_REGNUM) 3663 sparc_regno_reg_class[i] = GENERAL_REGS; 3664 else if (i < 64) 3665 sparc_regno_reg_class[i] = FP_REGS; 3666 else if (i < 96) 3667 sparc_regno_reg_class[i] = EXTRA_FP_REGS; 3668 else if (i < 100) 3669 sparc_regno_reg_class[i] = FPCC_REGS; 3670 else 3671 sparc_regno_reg_class[i] = NO_REGS; 3672 } 3673} 3674 3675/* Compute the frame size required by the function. This function is called 3676 during the reload pass and also by sparc_expand_prologue. */ 3677 3678HOST_WIDE_INT 3679sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function_p) 3680{ 3681 int outgoing_args_size = (current_function_outgoing_args_size 3682 + REG_PARM_STACK_SPACE (current_function_decl)); 3683 int n_regs = 0; /* N_REGS is the number of 4-byte regs saved thus far. */ 3684 int i; 3685 3686 if (TARGET_ARCH64) 3687 { 3688 for (i = 0; i < 8; i++) 3689 if (regs_ever_live[i] && ! call_used_regs[i]) 3690 n_regs += 2; 3691 } 3692 else 3693 { 3694 for (i = 0; i < 8; i += 2) 3695 if ((regs_ever_live[i] && ! call_used_regs[i]) 3696 || (regs_ever_live[i+1] && ! call_used_regs[i+1])) 3697 n_regs += 2; 3698 } 3699 3700 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) 3701 if ((regs_ever_live[i] && ! call_used_regs[i]) 3702 || (regs_ever_live[i+1] && ! call_used_regs[i+1])) 3703 n_regs += 2; 3704 3705 /* Set up values for use in prologue and epilogue. */ 3706 num_gfregs = n_regs; 3707 3708 if (leaf_function_p 3709 && n_regs == 0 3710 && size == 0 3711 && current_function_outgoing_args_size == 0) 3712 actual_fsize = apparent_fsize = 0; 3713 else 3714 { 3715 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ 3716 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8; 3717 apparent_fsize += n_regs * 4; 3718 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8); 3719 } 3720 3721 /* Make sure nothing can clobber our register windows. 3722 If a SAVE must be done, or there is a stack-local variable, 3723 the register window area must be allocated. */ 3724 if (! leaf_function_p || size > 0) 3725 actual_fsize += FIRST_PARM_OFFSET (current_function_decl); 3726 3727 return SPARC_STACK_ALIGN (actual_fsize); 3728} 3729 3730/* Output any necessary .register pseudo-ops. */ 3731 3732void 3733sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED) 3734{ 3735#ifdef HAVE_AS_REGISTER_PSEUDO_OP 3736 int i; 3737 3738 if (TARGET_ARCH32) 3739 return; 3740 3741 /* Check if %g[2367] were used without 3742 .register being printed for them already. */ 3743 for (i = 2; i < 8; i++) 3744 { 3745 if (regs_ever_live [i] 3746 && ! sparc_hard_reg_printed [i]) 3747 { 3748 sparc_hard_reg_printed [i] = 1; 3749 /* %g7 is used as TLS base register, use #ignore 3750 for it instead of #scratch. */ 3751 fprintf (file, "\t.register\t%%g%d, #%s\n", i, 3752 i == 7 ? "ignore" : "scratch"); 3753 } 3754 if (i == 3) i = 5; 3755 } 3756#endif 3757} 3758 3759/* Save/restore call-saved registers from LOW to HIGH at BASE+OFFSET 3760 as needed. LOW should be double-word aligned for 32-bit registers. 3761 Return the new OFFSET. */ 3762 3763#define SORR_SAVE 0 3764#define SORR_RESTORE 1 3765 3766static int 3767save_or_restore_regs (int low, int high, rtx base, int offset, int action) 3768{ 3769 rtx mem, insn; 3770 int i; 3771 3772 if (TARGET_ARCH64 && high <= 32) 3773 { 3774 for (i = low; i < high; i++) 3775 { 3776 if (regs_ever_live[i] && ! call_used_regs[i]) 3777 { 3778 mem = gen_rtx_MEM (DImode, plus_constant (base, offset)); 3779 set_mem_alias_set (mem, sparc_sr_alias_set); 3780 if (action == SORR_SAVE) 3781 { 3782 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i)); 3783 RTX_FRAME_RELATED_P (insn) = 1; 3784 } 3785 else /* action == SORR_RESTORE */ 3786 emit_move_insn (gen_rtx_REG (DImode, i), mem); 3787 offset += 8; 3788 } 3789 } 3790 } 3791 else 3792 { 3793 for (i = low; i < high; i += 2) 3794 { 3795 bool reg0 = regs_ever_live[i] && ! call_used_regs[i]; 3796 bool reg1 = regs_ever_live[i+1] && ! call_used_regs[i+1]; 3797 enum machine_mode mode; 3798 int regno; 3799 3800 if (reg0 && reg1) 3801 { 3802 mode = i < 32 ? DImode : DFmode; 3803 regno = i; 3804 } 3805 else if (reg0) 3806 { 3807 mode = i < 32 ? SImode : SFmode; 3808 regno = i; 3809 } 3810 else if (reg1) 3811 { 3812 mode = i < 32 ? SImode : SFmode; 3813 regno = i + 1; 3814 offset += 4; 3815 } 3816 else 3817 continue; 3818 3819 mem = gen_rtx_MEM (mode, plus_constant (base, offset)); 3820 set_mem_alias_set (mem, sparc_sr_alias_set); 3821 if (action == SORR_SAVE) 3822 { 3823 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno)); 3824 RTX_FRAME_RELATED_P (insn) = 1; 3825 } 3826 else /* action == SORR_RESTORE */ 3827 emit_move_insn (gen_rtx_REG (mode, regno), mem); 3828 3829 /* Always preserve double-word alignment. */ 3830 offset = (offset + 7) & -8; 3831 } 3832 } 3833 3834 return offset; 3835} 3836 3837/* Emit code to save call-saved registers. */ 3838 3839static void 3840emit_save_or_restore_regs (int action) 3841{ 3842 HOST_WIDE_INT offset; 3843 rtx base; 3844 3845 offset = frame_base_offset - apparent_fsize; 3846 3847 if (offset < -4096 || offset + num_gfregs * 4 > 4095) 3848 { 3849 /* ??? This might be optimized a little as %g1 might already have a 3850 value close enough that a single add insn will do. */ 3851 /* ??? Although, all of this is probably only a temporary fix 3852 because if %g1 can hold a function result, then 3853 sparc_expand_epilogue will lose (the result will be 3854 clobbered). */ 3855 base = gen_rtx_REG (Pmode, 1); 3856 emit_move_insn (base, GEN_INT (offset)); 3857 emit_insn (gen_rtx_SET (VOIDmode, 3858 base, 3859 gen_rtx_PLUS (Pmode, frame_base_reg, base))); 3860 offset = 0; 3861 } 3862 else 3863 base = frame_base_reg; 3864 3865 offset = save_or_restore_regs (0, 8, base, offset, action); 3866 save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, action); 3867} 3868 3869/* Generate a save_register_window insn. */ 3870 3871static rtx 3872gen_save_register_window (rtx increment) 3873{ 3874 if (TARGET_ARCH64) 3875 return gen_save_register_windowdi (increment); 3876 else 3877 return gen_save_register_windowsi (increment); 3878} 3879 3880/* Generate an increment for the stack pointer. */ 3881 3882static rtx 3883gen_stack_pointer_inc (rtx increment) 3884{ 3885 return gen_rtx_SET (VOIDmode, 3886 stack_pointer_rtx, 3887 gen_rtx_PLUS (Pmode, 3888 stack_pointer_rtx, 3889 increment)); 3890} 3891 3892/* Generate a decrement for the stack pointer. */ 3893 3894static rtx 3895gen_stack_pointer_dec (rtx decrement) 3896{ 3897 return gen_rtx_SET (VOIDmode, 3898 stack_pointer_rtx, 3899 gen_rtx_MINUS (Pmode, 3900 stack_pointer_rtx, 3901 decrement)); 3902} 3903 3904/* Expand the function prologue. The prologue is responsible for reserving 3905 storage for the frame, saving the call-saved registers and loading the 3906 PIC register if needed. */ 3907 3908void 3909sparc_expand_prologue (void) 3910{ 3911 rtx insn; 3912 int i; 3913 3914 /* Compute a snapshot of current_function_uses_only_leaf_regs. Relying 3915 on the final value of the flag means deferring the prologue/epilogue 3916 expansion until just before the second scheduling pass, which is too 3917 late to emit multiple epilogues or return insns. 3918 3919 Of course we are making the assumption that the value of the flag 3920 will not change between now and its final value. Of the three parts 3921 of the formula, only the last one can reasonably vary. Let's take a 3922 closer look, after assuming that the first two ones are set to true 3923 (otherwise the last value is effectively silenced). 3924 3925 If only_leaf_regs_used returns false, the global predicate will also 3926 be false so the actual frame size calculated below will be positive. 3927 As a consequence, the save_register_window insn will be emitted in 3928 the instruction stream; now this insn explicitly references %fp 3929 which is not a leaf register so only_leaf_regs_used will always 3930 return false subsequently. 3931 3932 If only_leaf_regs_used returns true, we hope that the subsequent 3933 optimization passes won't cause non-leaf registers to pop up. For 3934 example, the regrename pass has special provisions to not rename to 3935 non-leaf registers in a leaf function. */ 3936 sparc_leaf_function_p 3937 = optimize > 0 && leaf_function_p () && only_leaf_regs_used (); 3938 3939 /* Need to use actual_fsize, since we are also allocating 3940 space for our callee (and our own register save area). */ 3941 actual_fsize 3942 = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p); 3943 3944 /* Advertise that the data calculated just above are now valid. */ 3945 sparc_prologue_data_valid_p = true; 3946 3947 if (sparc_leaf_function_p) 3948 { 3949 frame_base_reg = stack_pointer_rtx; 3950 frame_base_offset = actual_fsize + SPARC_STACK_BIAS; 3951 } 3952 else 3953 { 3954 frame_base_reg = hard_frame_pointer_rtx; 3955 frame_base_offset = SPARC_STACK_BIAS; 3956 } 3957 3958 if (actual_fsize == 0) 3959 /* do nothing. */ ; 3960 else if (sparc_leaf_function_p) 3961 { 3962 if (actual_fsize <= 4096) 3963 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-actual_fsize))); 3964 else if (actual_fsize <= 8192) 3965 { 3966 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096))); 3967 /* %sp is still the CFA register. */ 3968 RTX_FRAME_RELATED_P (insn) = 1; 3969 insn 3970 = emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize))); 3971 } 3972 else 3973 { 3974 rtx reg = gen_rtx_REG (Pmode, 1); 3975 emit_move_insn (reg, GEN_INT (-actual_fsize)); 3976 insn = emit_insn (gen_stack_pointer_inc (reg)); 3977 REG_NOTES (insn) = 3978 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, 3979 gen_stack_pointer_inc (GEN_INT (-actual_fsize)), 3980 REG_NOTES (insn)); 3981 } 3982 3983 RTX_FRAME_RELATED_P (insn) = 1; 3984 } 3985 else 3986 { 3987 if (actual_fsize <= 4096) 3988 insn = emit_insn (gen_save_register_window (GEN_INT (-actual_fsize))); 3989 else if (actual_fsize <= 8192) 3990 { 3991 insn = emit_insn (gen_save_register_window (GEN_INT (-4096))); 3992 /* %sp is not the CFA register anymore. */ 3993 emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize))); 3994 } 3995 else 3996 { 3997 rtx reg = gen_rtx_REG (Pmode, 1); 3998 emit_move_insn (reg, GEN_INT (-actual_fsize)); 3999 insn = emit_insn (gen_save_register_window (reg)); 4000 } 4001 4002 RTX_FRAME_RELATED_P (insn) = 1; 4003 for (i=0; i < XVECLEN (PATTERN (insn), 0); i++) 4004 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, i)) = 1; 4005 } 4006 4007 if (num_gfregs) 4008 emit_save_or_restore_regs (SORR_SAVE); 4009 4010 /* Load the PIC register if needed. */ 4011 if (flag_pic && current_function_uses_pic_offset_table) 4012 load_pic_register (false); 4013} 4014 4015/* This function generates the assembly code for function entry, which boils 4016 down to emitting the necessary .register directives. */ 4017 4018static void 4019sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) 4020{ 4021 /* Check that the assumption we made in sparc_expand_prologue is valid. */ 4022 gcc_assert (sparc_leaf_function_p == current_function_uses_only_leaf_regs); 4023 4024 sparc_output_scratch_registers (file); 4025} 4026 4027/* Expand the function epilogue, either normal or part of a sibcall. 4028 We emit all the instructions except the return or the call. */ 4029 4030void 4031sparc_expand_epilogue (void) 4032{ 4033 if (num_gfregs) 4034 emit_save_or_restore_regs (SORR_RESTORE); 4035 4036 if (actual_fsize == 0) 4037 /* do nothing. */ ; 4038 else if (sparc_leaf_function_p) 4039 { 4040 if (actual_fsize <= 4096) 4041 emit_insn (gen_stack_pointer_dec (GEN_INT (- actual_fsize))); 4042 else if (actual_fsize <= 8192) 4043 { 4044 emit_insn (gen_stack_pointer_dec (GEN_INT (-4096))); 4045 emit_insn (gen_stack_pointer_dec (GEN_INT (4096 - actual_fsize))); 4046 } 4047 else 4048 { 4049 rtx reg = gen_rtx_REG (Pmode, 1); 4050 emit_move_insn (reg, GEN_INT (-actual_fsize)); 4051 emit_insn (gen_stack_pointer_dec (reg)); 4052 } 4053 } 4054} 4055 4056/* Return true if it is appropriate to emit `return' instructions in the 4057 body of a function. */ 4058 4059bool 4060sparc_can_use_return_insn_p (void) 4061{ 4062 return sparc_prologue_data_valid_p 4063 && (actual_fsize == 0 || !sparc_leaf_function_p); 4064} 4065 4066/* This function generates the assembly code for function exit. */ 4067 4068static void 4069sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) 4070{ 4071 /* If code does not drop into the epilogue, we have to still output 4072 a dummy nop for the sake of sane backtraces. Otherwise, if the 4073 last two instructions of a function were "call foo; dslot;" this 4074 can make the return PC of foo (i.e. address of call instruction 4075 plus 8) point to the first instruction in the next function. */ 4076 4077 rtx insn, last_real_insn; 4078 4079 insn = get_last_insn (); 4080 4081 last_real_insn = prev_real_insn (insn); 4082 if (last_real_insn 4083 && GET_CODE (last_real_insn) == INSN 4084 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE) 4085 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0); 4086 4087 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN) 4088 fputs("\tnop\n", file); 4089 4090 sparc_output_deferred_case_vectors (); 4091} 4092 4093/* Output a 'restore' instruction. */ 4094 4095static void 4096output_restore (rtx pat) 4097{ 4098 rtx operands[3]; 4099 4100 if (! pat) 4101 { 4102 fputs ("\t restore\n", asm_out_file); 4103 return; 4104 } 4105 4106 gcc_assert (GET_CODE (pat) == SET); 4107 4108 operands[0] = SET_DEST (pat); 4109 pat = SET_SRC (pat); 4110 4111 switch (GET_CODE (pat)) 4112 { 4113 case PLUS: 4114 operands[1] = XEXP (pat, 0); 4115 operands[2] = XEXP (pat, 1); 4116 output_asm_insn (" restore %r1, %2, %Y0", operands); 4117 break; 4118 case LO_SUM: 4119 operands[1] = XEXP (pat, 0); 4120 operands[2] = XEXP (pat, 1); 4121 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); 4122 break; 4123 case ASHIFT: 4124 operands[1] = XEXP (pat, 0); 4125 gcc_assert (XEXP (pat, 1) == const1_rtx); 4126 output_asm_insn (" restore %r1, %r1, %Y0", operands); 4127 break; 4128 default: 4129 operands[1] = pat; 4130 output_asm_insn (" restore %%g0, %1, %Y0", operands); 4131 break; 4132 } 4133} 4134 4135/* Output a return. */ 4136 4137const char * 4138output_return (rtx insn) 4139{ 4140 if (sparc_leaf_function_p) 4141 { 4142 /* This is a leaf function so we don't have to bother restoring the 4143 register window, which frees us from dealing with the convoluted 4144 semantics of restore/return. We simply output the jump to the 4145 return address and the insn in the delay slot (if any). */ 4146 4147 gcc_assert (! current_function_calls_eh_return); 4148 4149 return "jmp\t%%o7+%)%#"; 4150 } 4151 else 4152 { 4153 /* This is a regular function so we have to restore the register window. 4154 We may have a pending insn for the delay slot, which will be either 4155 combined with the 'restore' instruction or put in the delay slot of 4156 the 'return' instruction. */ 4157 4158 if (current_function_calls_eh_return) 4159 { 4160 /* If the function uses __builtin_eh_return, the eh_return 4161 machinery occupies the delay slot. */ 4162 gcc_assert (! final_sequence); 4163 4164 if (! flag_delayed_branch) 4165 fputs ("\tadd\t%fp, %g1, %fp\n", asm_out_file); 4166 4167 if (TARGET_V9) 4168 fputs ("\treturn\t%i7+8\n", asm_out_file); 4169 else 4170 fputs ("\trestore\n\tjmp\t%o7+8\n", asm_out_file); 4171 4172 if (flag_delayed_branch) 4173 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file); 4174 else 4175 fputs ("\t nop\n", asm_out_file); 4176 } 4177 else if (final_sequence) 4178 { 4179 rtx delay, pat; 4180 4181 delay = NEXT_INSN (insn); 4182 gcc_assert (delay); 4183 4184 pat = PATTERN (delay); 4185 4186 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)) 4187 { 4188 epilogue_renumber (&pat, 0); 4189 return "return\t%%i7+%)%#"; 4190 } 4191 else 4192 { 4193 output_asm_insn ("jmp\t%%i7+%)", NULL); 4194 output_restore (pat); 4195 PATTERN (delay) = gen_blockage (); 4196 INSN_CODE (delay) = -1; 4197 } 4198 } 4199 else 4200 { 4201 /* The delay slot is empty. */ 4202 if (TARGET_V9) 4203 return "return\t%%i7+%)\n\t nop"; 4204 else if (flag_delayed_branch) 4205 return "jmp\t%%i7+%)\n\t restore"; 4206 else 4207 return "restore\n\tjmp\t%%o7+%)\n\t nop"; 4208 } 4209 } 4210 4211 return ""; 4212} 4213 4214/* Output a sibling call. */ 4215 4216const char * 4217output_sibcall (rtx insn, rtx call_operand) 4218{ 4219 rtx operands[1]; 4220 4221 gcc_assert (flag_delayed_branch); 4222 4223 operands[0] = call_operand; 4224 4225 if (sparc_leaf_function_p) 4226 { 4227 /* This is a leaf function so we don't have to bother restoring the 4228 register window. We simply output the jump to the function and 4229 the insn in the delay slot (if any). */ 4230 4231 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence)); 4232 4233 if (final_sequence) 4234 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#", 4235 operands); 4236 else 4237 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize 4238 it into branch if possible. */ 4239 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7", 4240 operands); 4241 } 4242 else 4243 { 4244 /* This is a regular function so we have to restore the register window. 4245 We may have a pending insn for the delay slot, which will be combined 4246 with the 'restore' instruction. */ 4247 4248 output_asm_insn ("call\t%a0, 0", operands); 4249 4250 if (final_sequence) 4251 { 4252 rtx delay = NEXT_INSN (insn); 4253 gcc_assert (delay); 4254 4255 output_restore (PATTERN (delay)); 4256 4257 PATTERN (delay) = gen_blockage (); 4258 INSN_CODE (delay) = -1; 4259 } 4260 else 4261 output_restore (NULL_RTX); 4262 } 4263 4264 return ""; 4265} 4266 4267/* Functions for handling argument passing. 4268 4269 For 32-bit, the first 6 args are normally in registers and the rest are 4270 pushed. Any arg that starts within the first 6 words is at least 4271 partially passed in a register unless its data type forbids. 4272 4273 For 64-bit, the argument registers are laid out as an array of 16 elements 4274 and arguments are added sequentially. The first 6 int args and up to the 4275 first 16 fp args (depending on size) are passed in regs. 4276 4277 Slot Stack Integral Float Float in structure Double Long Double 4278 ---- ----- -------- ----- ------------------ ------ ----------- 4279 15 [SP+248] %f31 %f30,%f31 %d30 4280 14 [SP+240] %f29 %f28,%f29 %d28 %q28 4281 13 [SP+232] %f27 %f26,%f27 %d26 4282 12 [SP+224] %f25 %f24,%f25 %d24 %q24 4283 11 [SP+216] %f23 %f22,%f23 %d22 4284 10 [SP+208] %f21 %f20,%f21 %d20 %q20 4285 9 [SP+200] %f19 %f18,%f19 %d18 4286 8 [SP+192] %f17 %f16,%f17 %d16 %q16 4287 7 [SP+184] %f15 %f14,%f15 %d14 4288 6 [SP+176] %f13 %f12,%f13 %d12 %q12 4289 5 [SP+168] %o5 %f11 %f10,%f11 %d10 4290 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 4291 3 [SP+152] %o3 %f7 %f6,%f7 %d6 4292 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 4293 1 [SP+136] %o1 %f3 %f2,%f3 %d2 4294 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 4295 4296 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. 4297 4298 Integral arguments are always passed as 64-bit quantities appropriately 4299 extended. 4300 4301 Passing of floating point values is handled as follows. 4302 If a prototype is in scope: 4303 If the value is in a named argument (i.e. not a stdarg function or a 4304 value not part of the `...') then the value is passed in the appropriate 4305 fp reg. 4306 If the value is part of the `...' and is passed in one of the first 6 4307 slots then the value is passed in the appropriate int reg. 4308 If the value is part of the `...' and is not passed in one of the first 6 4309 slots then the value is passed in memory. 4310 If a prototype is not in scope: 4311 If the value is one of the first 6 arguments the value is passed in the 4312 appropriate integer reg and the appropriate fp reg. 4313 If the value is not one of the first 6 arguments the value is passed in 4314 the appropriate fp reg and in memory. 4315 4316 4317 Summary of the calling conventions implemented by GCC on SPARC: 4318 4319 32-bit ABI: 4320 size argument return value 4321 4322 small integer <4 int. reg. int. reg. 4323 word 4 int. reg. int. reg. 4324 double word 8 int. reg. int. reg. 4325 4326 _Complex small integer <8 int. reg. int. reg. 4327 _Complex word 8 int. reg. int. reg. 4328 _Complex double word 16 memory int. reg. 4329 4330 vector integer <=8 int. reg. FP reg. 4331 vector integer >8 memory memory 4332 4333 float 4 int. reg. FP reg. 4334 double 8 int. reg. FP reg. 4335 long double 16 memory memory 4336 4337 _Complex float 8 memory FP reg. 4338 _Complex double 16 memory FP reg. 4339 _Complex long double 32 memory FP reg. 4340 4341 vector float any memory memory 4342 4343 aggregate any memory memory 4344 4345 4346 4347 64-bit ABI: 4348 size argument return value 4349 4350 small integer <8 int. reg. int. reg. 4351 word 8 int. reg. int. reg. 4352 double word 16 int. reg. int. reg. 4353 4354 _Complex small integer <16 int. reg. int. reg. 4355 _Complex word 16 int. reg. int. reg. 4356 _Complex double word 32 memory int. reg. 4357 4358 vector integer <=16 FP reg. FP reg. 4359 vector integer 16<s<=32 memory FP reg. 4360 vector integer >32 memory memory 4361 4362 float 4 FP reg. FP reg. 4363 double 8 FP reg. FP reg. 4364 long double 16 FP reg. FP reg. 4365 4366 _Complex float 8 FP reg. FP reg. 4367 _Complex double 16 FP reg. FP reg. 4368 _Complex long double 32 memory FP reg. 4369 4370 vector float <=16 FP reg. FP reg. 4371 vector float 16<s<=32 memory FP reg. 4372 vector float >32 memory memory 4373 4374 aggregate <=16 reg. reg. 4375 aggregate 16<s<=32 memory reg. 4376 aggregate >32 memory memory 4377 4378 4379 4380Note #1: complex floating-point types follow the extended SPARC ABIs as 4381implemented by the Sun compiler. 4382 4383Note #2: integral vector types follow the scalar floating-point types 4384conventions to match what is implemented by the Sun VIS SDK. 4385 4386Note #3: floating-point vector types follow the aggregate types 4387conventions. */ 4388 4389 4390/* Maximum number of int regs for args. */ 4391#define SPARC_INT_ARG_MAX 6 4392/* Maximum number of fp regs for args. */ 4393#define SPARC_FP_ARG_MAX 16 4394 4395#define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 4396 4397/* Handle the INIT_CUMULATIVE_ARGS macro. 4398 Initialize a variable CUM of type CUMULATIVE_ARGS 4399 for a call to a function whose data type is FNTYPE. 4400 For a library call, FNTYPE is 0. */ 4401 4402void 4403init_cumulative_args (struct sparc_args *cum, tree fntype, 4404 rtx libname ATTRIBUTE_UNUSED, 4405 tree fndecl ATTRIBUTE_UNUSED) 4406{ 4407 cum->words = 0; 4408 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype); 4409 cum->libcall_p = fntype == 0; 4410} 4411 4412/* Handle the TARGET_PROMOTE_PROTOTYPES target hook. 4413 When a prototype says `char' or `short', really pass an `int'. */ 4414 4415static bool 4416sparc_promote_prototypes (tree fntype ATTRIBUTE_UNUSED) 4417{ 4418 return TARGET_ARCH32 ? true : false; 4419} 4420 4421/* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */ 4422 4423static bool 4424sparc_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED) 4425{ 4426 return TARGET_ARCH64 ? true : false; 4427} 4428 4429/* Scan the record type TYPE and return the following predicates: 4430 - INTREGS_P: the record contains at least one field or sub-field 4431 that is eligible for promotion in integer registers. 4432 - FP_REGS_P: the record contains at least one field or sub-field 4433 that is eligible for promotion in floating-point registers. 4434 - PACKED_P: the record contains at least one field that is packed. 4435 4436 Sub-fields are not taken into account for the PACKED_P predicate. */ 4437 4438static void 4439scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p) 4440{ 4441 tree field; 4442 4443 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4444 { 4445 if (TREE_CODE (field) == FIELD_DECL) 4446 { 4447 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 4448 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0); 4449 else if ((FLOAT_TYPE_P (TREE_TYPE (field)) 4450 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE) 4451 && TARGET_FPU) 4452 *fpregs_p = 1; 4453 else 4454 *intregs_p = 1; 4455 4456 if (packed_p && DECL_PACKED (field)) 4457 *packed_p = 1; 4458 } 4459 } 4460} 4461 4462/* Compute the slot number to pass an argument in. 4463 Return the slot number or -1 if passing on the stack. 4464 4465 CUM is a variable of type CUMULATIVE_ARGS which gives info about 4466 the preceding args and about the function being called. 4467 MODE is the argument's machine mode. 4468 TYPE is the data type of the argument (as a tree). 4469 This is null for libcalls where that information may 4470 not be available. 4471 NAMED is nonzero if this argument is a named parameter 4472 (otherwise it is an extra parameter matching an ellipsis). 4473 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. 4474 *PREGNO records the register number to use if scalar type. 4475 *PPADDING records the amount of padding needed in words. */ 4476 4477static int 4478function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode, 4479 tree type, int named, int incoming_p, 4480 int *pregno, int *ppadding) 4481{ 4482 int regbase = (incoming_p 4483 ? SPARC_INCOMING_INT_ARG_FIRST 4484 : SPARC_OUTGOING_INT_ARG_FIRST); 4485 int slotno = cum->words; 4486 enum mode_class mclass; 4487 int regno; 4488 4489 *ppadding = 0; 4490 4491 if (type && TREE_ADDRESSABLE (type)) 4492 return -1; 4493 4494 if (TARGET_ARCH32 4495 && mode == BLKmode 4496 && type 4497 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) 4498 return -1; 4499 4500 /* For SPARC64, objects requiring 16-byte alignment get it. */ 4501 if (TARGET_ARCH64 4502 && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128 4503 && (slotno & 1) != 0) 4504 slotno++, *ppadding = 1; 4505 4506 mclass = GET_MODE_CLASS (mode); 4507 if (type && TREE_CODE (type) == VECTOR_TYPE) 4508 { 4509 /* Vector types deserve special treatment because they are 4510 polymorphic wrt their mode, depending upon whether VIS 4511 instructions are enabled. */ 4512 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE) 4513 { 4514 /* The SPARC port defines no floating-point vector modes. */ 4515 gcc_assert (mode == BLKmode); 4516 } 4517 else 4518 { 4519 /* Integral vector types should either have a vector 4520 mode or an integral mode, because we are guaranteed 4521 by pass_by_reference that their size is not greater 4522 than 16 bytes and TImode is 16-byte wide. */ 4523 gcc_assert (mode != BLKmode); 4524 4525 /* Vector integers are handled like floats according to 4526 the Sun VIS SDK. */ 4527 mclass = MODE_FLOAT; 4528 } 4529 } 4530 4531 switch (mclass) 4532 { 4533 case MODE_FLOAT: 4534 case MODE_COMPLEX_FLOAT: 4535 if (TARGET_ARCH64 && TARGET_FPU && named) 4536 { 4537 if (slotno >= SPARC_FP_ARG_MAX) 4538 return -1; 4539 regno = SPARC_FP_ARG_FIRST + slotno * 2; 4540 /* Arguments filling only one single FP register are 4541 right-justified in the outer double FP register. */ 4542 if (GET_MODE_SIZE (mode) <= 4) 4543 regno++; 4544 break; 4545 } 4546 /* fallthrough */ 4547 4548 case MODE_INT: 4549 case MODE_COMPLEX_INT: 4550 if (slotno >= SPARC_INT_ARG_MAX) 4551 return -1; 4552 regno = regbase + slotno; 4553 break; 4554 4555 case MODE_RANDOM: 4556 if (mode == VOIDmode) 4557 /* MODE is VOIDmode when generating the actual call. */ 4558 return -1; 4559 4560 gcc_assert (mode == BLKmode); 4561 4562 if (TARGET_ARCH32 4563 || !type 4564 || (TREE_CODE (type) != VECTOR_TYPE 4565 && TREE_CODE (type) != RECORD_TYPE)) 4566 { 4567 if (slotno >= SPARC_INT_ARG_MAX) 4568 return -1; 4569 regno = regbase + slotno; 4570 } 4571 else /* TARGET_ARCH64 && type */ 4572 { 4573 int intregs_p = 0, fpregs_p = 0, packed_p = 0; 4574 4575 /* First see what kinds of registers we would need. */ 4576 if (TREE_CODE (type) == VECTOR_TYPE) 4577 fpregs_p = 1; 4578 else 4579 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p); 4580 4581 /* The ABI obviously doesn't specify how packed structures 4582 are passed. These are defined to be passed in int regs 4583 if possible, otherwise memory. */ 4584 if (packed_p || !named) 4585 fpregs_p = 0, intregs_p = 1; 4586 4587 /* If all arg slots are filled, then must pass on stack. */ 4588 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX) 4589 return -1; 4590 4591 /* If there are only int args and all int arg slots are filled, 4592 then must pass on stack. */ 4593 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX) 4594 return -1; 4595 4596 /* Note that even if all int arg slots are filled, fp members may 4597 still be passed in regs if such regs are available. 4598 *PREGNO isn't set because there may be more than one, it's up 4599 to the caller to compute them. */ 4600 return slotno; 4601 } 4602 break; 4603 4604 default : 4605 gcc_unreachable (); 4606 } 4607 4608 *pregno = regno; 4609 return slotno; 4610} 4611 4612/* Handle recursive register counting for structure field layout. */ 4613 4614struct function_arg_record_value_parms 4615{ 4616 rtx ret; /* return expression being built. */ 4617 int slotno; /* slot number of the argument. */ 4618 int named; /* whether the argument is named. */ 4619 int regbase; /* regno of the base register. */ 4620 int stack; /* 1 if part of the argument is on the stack. */ 4621 int intoffset; /* offset of the first pending integer field. */ 4622 unsigned int nregs; /* number of words passed in registers. */ 4623}; 4624 4625static void function_arg_record_value_3 4626 (HOST_WIDE_INT, struct function_arg_record_value_parms *); 4627static void function_arg_record_value_2 4628 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool); 4629static void function_arg_record_value_1 4630 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool); 4631static rtx function_arg_record_value (tree, enum machine_mode, int, int, int); 4632static rtx function_arg_union_value (int, enum machine_mode, int, int); 4633 4634/* A subroutine of function_arg_record_value. Traverse the structure 4635 recursively and determine how many registers will be required. */ 4636 4637static void 4638function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos, 4639 struct function_arg_record_value_parms *parms, 4640 bool packed_p) 4641{ 4642 tree field; 4643 4644 /* We need to compute how many registers are needed so we can 4645 allocate the PARALLEL but before we can do that we need to know 4646 whether there are any packed fields. The ABI obviously doesn't 4647 specify how structures are passed in this case, so they are 4648 defined to be passed in int regs if possible, otherwise memory, 4649 regardless of whether there are fp values present. */ 4650 4651 if (! packed_p) 4652 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4653 { 4654 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 4655 { 4656 packed_p = true; 4657 break; 4658 } 4659 } 4660 4661 /* Compute how many registers we need. */ 4662 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4663 { 4664 if (TREE_CODE (field) == FIELD_DECL) 4665 { 4666 HOST_WIDE_INT bitpos = startbitpos; 4667 4668 if (DECL_SIZE (field) != 0) 4669 { 4670 if (integer_zerop (DECL_SIZE (field))) 4671 continue; 4672 4673 if (host_integerp (bit_position (field), 1)) 4674 bitpos += int_bit_position (field); 4675 } 4676 4677 /* ??? FIXME: else assume zero offset. */ 4678 4679 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 4680 function_arg_record_value_1 (TREE_TYPE (field), 4681 bitpos, 4682 parms, 4683 packed_p); 4684 else if ((FLOAT_TYPE_P (TREE_TYPE (field)) 4685 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE) 4686 && TARGET_FPU 4687 && parms->named 4688 && ! packed_p) 4689 { 4690 if (parms->intoffset != -1) 4691 { 4692 unsigned int startbit, endbit; 4693 int intslots, this_slotno; 4694 4695 startbit = parms->intoffset & -BITS_PER_WORD; 4696 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; 4697 4698 intslots = (endbit - startbit) / BITS_PER_WORD; 4699 this_slotno = parms->slotno + parms->intoffset 4700 / BITS_PER_WORD; 4701 4702 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) 4703 { 4704 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); 4705 /* We need to pass this field on the stack. */ 4706 parms->stack = 1; 4707 } 4708 4709 parms->nregs += intslots; 4710 parms->intoffset = -1; 4711 } 4712 4713 /* There's no need to check this_slotno < SPARC_FP_ARG MAX. 4714 If it wasn't true we wouldn't be here. */ 4715 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE 4716 && DECL_MODE (field) == BLKmode) 4717 parms->nregs += TYPE_VECTOR_SUBPARTS (TREE_TYPE (field)); 4718 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 4719 parms->nregs += 2; 4720 else 4721 parms->nregs += 1; 4722 } 4723 else 4724 { 4725 if (parms->intoffset == -1) 4726 parms->intoffset = bitpos; 4727 } 4728 } 4729 } 4730} 4731 4732/* A subroutine of function_arg_record_value. Assign the bits of the 4733 structure between parms->intoffset and bitpos to integer registers. */ 4734 4735static void 4736function_arg_record_value_3 (HOST_WIDE_INT bitpos, 4737 struct function_arg_record_value_parms *parms) 4738{ 4739 enum machine_mode mode; 4740 unsigned int regno; 4741 unsigned int startbit, endbit; 4742 int this_slotno, intslots, intoffset; 4743 rtx reg; 4744 4745 if (parms->intoffset == -1) 4746 return; 4747 4748 intoffset = parms->intoffset; 4749 parms->intoffset = -1; 4750 4751 startbit = intoffset & -BITS_PER_WORD; 4752 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD; 4753 intslots = (endbit - startbit) / BITS_PER_WORD; 4754 this_slotno = parms->slotno + intoffset / BITS_PER_WORD; 4755 4756 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); 4757 if (intslots <= 0) 4758 return; 4759 4760 /* If this is the trailing part of a word, only load that much into 4761 the register. Otherwise load the whole register. Note that in 4762 the latter case we may pick up unwanted bits. It's not a problem 4763 at the moment but may wish to revisit. */ 4764 4765 if (intoffset % BITS_PER_WORD != 0) 4766 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, 4767 MODE_INT); 4768 else 4769 mode = word_mode; 4770 4771 intoffset /= BITS_PER_UNIT; 4772 do 4773 { 4774 regno = parms->regbase + this_slotno; 4775 reg = gen_rtx_REG (mode, regno); 4776 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 4777 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); 4778 4779 this_slotno += 1; 4780 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1; 4781 mode = word_mode; 4782 parms->nregs += 1; 4783 intslots -= 1; 4784 } 4785 while (intslots > 0); 4786} 4787 4788/* A subroutine of function_arg_record_value. Traverse the structure 4789 recursively and assign bits to floating point registers. Track which 4790 bits in between need integer registers; invoke function_arg_record_value_3 4791 to make that happen. */ 4792 4793static void 4794function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos, 4795 struct function_arg_record_value_parms *parms, 4796 bool packed_p) 4797{ 4798 tree field; 4799 4800 if (! packed_p) 4801 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4802 { 4803 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 4804 { 4805 packed_p = true; 4806 break; 4807 } 4808 } 4809 4810 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) 4811 { 4812 if (TREE_CODE (field) == FIELD_DECL) 4813 { 4814 HOST_WIDE_INT bitpos = startbitpos; 4815 4816 if (DECL_SIZE (field) != 0) 4817 { 4818 if (integer_zerop (DECL_SIZE (field))) 4819 continue; 4820 4821 if (host_integerp (bit_position (field), 1)) 4822 bitpos += int_bit_position (field); 4823 } 4824 4825 /* ??? FIXME: else assume zero offset. */ 4826 4827 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE) 4828 function_arg_record_value_2 (TREE_TYPE (field), 4829 bitpos, 4830 parms, 4831 packed_p); 4832 else if ((FLOAT_TYPE_P (TREE_TYPE (field)) 4833 || TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE) 4834 && TARGET_FPU 4835 && parms->named 4836 && ! packed_p) 4837 { 4838 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD; 4839 int regno, nregs, pos; 4840 enum machine_mode mode = DECL_MODE (field); 4841 rtx reg; 4842 4843 function_arg_record_value_3 (bitpos, parms); 4844 4845 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE 4846 && mode == BLKmode) 4847 { 4848 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field))); 4849 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field)); 4850 } 4851 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 4852 { 4853 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field))); 4854 nregs = 2; 4855 } 4856 else 4857 nregs = 1; 4858 4859 regno = SPARC_FP_ARG_FIRST + this_slotno * 2; 4860 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0) 4861 regno++; 4862 reg = gen_rtx_REG (mode, regno); 4863 pos = bitpos / BITS_PER_UNIT; 4864 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 4865 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos)); 4866 parms->nregs += 1; 4867 while (--nregs > 0) 4868 { 4869 regno += GET_MODE_SIZE (mode) / 4; 4870 reg = gen_rtx_REG (mode, regno); 4871 pos += GET_MODE_SIZE (mode); 4872 XVECEXP (parms->ret, 0, parms->stack + parms->nregs) 4873 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos)); 4874 parms->nregs += 1; 4875 } 4876 } 4877 else 4878 { 4879 if (parms->intoffset == -1) 4880 parms->intoffset = bitpos; 4881 } 4882 } 4883 } 4884} 4885 4886/* Used by function_arg and function_value to implement the complex 4887 conventions of the 64-bit ABI for passing and returning structures. 4888 Return an expression valid as a return value for the two macros 4889 FUNCTION_ARG and FUNCTION_VALUE. 4890 4891 TYPE is the data type of the argument (as a tree). 4892 This is null for libcalls where that information may 4893 not be available. 4894 MODE is the argument's machine mode. 4895 SLOTNO is the index number of the argument's slot in the parameter array. 4896 NAMED is nonzero if this argument is a named parameter 4897 (otherwise it is an extra parameter matching an ellipsis). 4898 REGBASE is the regno of the base register for the parameter array. */ 4899 4900static rtx 4901function_arg_record_value (tree type, enum machine_mode mode, 4902 int slotno, int named, int regbase) 4903{ 4904 HOST_WIDE_INT typesize = int_size_in_bytes (type); 4905 struct function_arg_record_value_parms parms; 4906 unsigned int nregs; 4907 4908 parms.ret = NULL_RTX; 4909 parms.slotno = slotno; 4910 parms.named = named; 4911 parms.regbase = regbase; 4912 parms.stack = 0; 4913 4914 /* Compute how many registers we need. */ 4915 parms.nregs = 0; 4916 parms.intoffset = 0; 4917 function_arg_record_value_1 (type, 0, &parms, false); 4918 4919 /* Take into account pending integer fields. */ 4920 if (parms.intoffset != -1) 4921 { 4922 unsigned int startbit, endbit; 4923 int intslots, this_slotno; 4924 4925 startbit = parms.intoffset & -BITS_PER_WORD; 4926 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD; 4927 intslots = (endbit - startbit) / BITS_PER_WORD; 4928 this_slotno = slotno + parms.intoffset / BITS_PER_WORD; 4929 4930 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) 4931 { 4932 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); 4933 /* We need to pass this field on the stack. */ 4934 parms.stack = 1; 4935 } 4936 4937 parms.nregs += intslots; 4938 } 4939 nregs = parms.nregs; 4940 4941 /* Allocate the vector and handle some annoying special cases. */ 4942 if (nregs == 0) 4943 { 4944 /* ??? Empty structure has no value? Duh? */ 4945 if (typesize <= 0) 4946 { 4947 /* Though there's nothing really to store, return a word register 4948 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL 4949 leads to breakage due to the fact that there are zero bytes to 4950 load. */ 4951 return gen_rtx_REG (mode, regbase); 4952 } 4953 else 4954 { 4955 /* ??? C++ has structures with no fields, and yet a size. Give up 4956 for now and pass everything back in integer registers. */ 4957 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 4958 } 4959 if (nregs + slotno > SPARC_INT_ARG_MAX) 4960 nregs = SPARC_INT_ARG_MAX - slotno; 4961 } 4962 gcc_assert (nregs != 0); 4963 4964 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs)); 4965 4966 /* If at least one field must be passed on the stack, generate 4967 (parallel [(expr_list (nil) ...) ...]) so that all fields will 4968 also be passed on the stack. We can't do much better because the 4969 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case 4970 of structures for which the fields passed exclusively in registers 4971 are not at the beginning of the structure. */ 4972 if (parms.stack) 4973 XVECEXP (parms.ret, 0, 0) 4974 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 4975 4976 /* Fill in the entries. */ 4977 parms.nregs = 0; 4978 parms.intoffset = 0; 4979 function_arg_record_value_2 (type, 0, &parms, false); 4980 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms); 4981 4982 gcc_assert (parms.nregs == nregs); 4983 4984 return parms.ret; 4985} 4986 4987/* Used by function_arg and function_value to implement the conventions 4988 of the 64-bit ABI for passing and returning unions. 4989 Return an expression valid as a return value for the two macros 4990 FUNCTION_ARG and FUNCTION_VALUE. 4991 4992 SIZE is the size in bytes of the union. 4993 MODE is the argument's machine mode. 4994 REGNO is the hard register the union will be passed in. */ 4995 4996static rtx 4997function_arg_union_value (int size, enum machine_mode mode, int slotno, 4998 int regno) 4999{ 5000 int nwords = ROUND_ADVANCE (size), i; 5001 rtx regs; 5002 5003 /* See comment in previous function for empty structures. */ 5004 if (nwords == 0) 5005 return gen_rtx_REG (mode, regno); 5006 5007 if (slotno == SPARC_INT_ARG_MAX - 1) 5008 nwords = 1; 5009 5010 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords)); 5011 5012 for (i = 0; i < nwords; i++) 5013 { 5014 /* Unions are passed left-justified. */ 5015 XVECEXP (regs, 0, i) 5016 = gen_rtx_EXPR_LIST (VOIDmode, 5017 gen_rtx_REG (word_mode, regno), 5018 GEN_INT (UNITS_PER_WORD * i)); 5019 regno++; 5020 } 5021 5022 return regs; 5023} 5024 5025/* Used by function_arg and function_value to implement the conventions 5026 for passing and returning large (BLKmode) vectors. 5027 Return an expression valid as a return value for the two macros 5028 FUNCTION_ARG and FUNCTION_VALUE. 5029 5030 SIZE is the size in bytes of the vector. 5031 BASE_MODE is the argument's base machine mode. 5032 REGNO is the FP hard register the vector will be passed in. */ 5033 5034static rtx 5035function_arg_vector_value (int size, enum machine_mode base_mode, int regno) 5036{ 5037 unsigned short base_mode_size = GET_MODE_SIZE (base_mode); 5038 int nregs = size / base_mode_size, i; 5039 rtx regs; 5040 5041 regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs)); 5042 5043 for (i = 0; i < nregs; i++) 5044 { 5045 XVECEXP (regs, 0, i) 5046 = gen_rtx_EXPR_LIST (VOIDmode, 5047 gen_rtx_REG (base_mode, regno), 5048 GEN_INT (base_mode_size * i)); 5049 regno += base_mode_size / 4; 5050 } 5051 5052 return regs; 5053} 5054 5055/* Handle the FUNCTION_ARG macro. 5056 Determine where to put an argument to a function. 5057 Value is zero to push the argument on the stack, 5058 or a hard register in which to store the argument. 5059 5060 CUM is a variable of type CUMULATIVE_ARGS which gives info about 5061 the preceding args and about the function being called. 5062 MODE is the argument's machine mode. 5063 TYPE is the data type of the argument (as a tree). 5064 This is null for libcalls where that information may 5065 not be available. 5066 NAMED is nonzero if this argument is a named parameter 5067 (otherwise it is an extra parameter matching an ellipsis). 5068 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */ 5069 5070rtx 5071function_arg (const struct sparc_args *cum, enum machine_mode mode, 5072 tree type, int named, int incoming_p) 5073{ 5074 int regbase = (incoming_p 5075 ? SPARC_INCOMING_INT_ARG_FIRST 5076 : SPARC_OUTGOING_INT_ARG_FIRST); 5077 int slotno, regno, padding; 5078 enum mode_class mclass = GET_MODE_CLASS (mode); 5079 5080 slotno = function_arg_slotno (cum, mode, type, named, incoming_p, 5081 ®no, &padding); 5082 if (slotno == -1) 5083 return 0; 5084 5085 /* Vector types deserve special treatment because they are polymorphic wrt 5086 their mode, depending upon whether VIS instructions are enabled. */ 5087 if (type && TREE_CODE (type) == VECTOR_TYPE) 5088 { 5089 HOST_WIDE_INT size = int_size_in_bytes (type); 5090 gcc_assert ((TARGET_ARCH32 && size <= 8) 5091 || (TARGET_ARCH64 && size <= 16)); 5092 5093 if (mode == BLKmode) 5094 return function_arg_vector_value (size, 5095 TYPE_MODE (TREE_TYPE (type)), 5096 SPARC_FP_ARG_FIRST + 2*slotno); 5097 else 5098 mclass = MODE_FLOAT; 5099 } 5100 5101 if (TARGET_ARCH32) 5102 return gen_rtx_REG (mode, regno); 5103 5104 /* Structures up to 16 bytes in size are passed in arg slots on the stack 5105 and are promoted to registers if possible. */ 5106 if (type && TREE_CODE (type) == RECORD_TYPE) 5107 { 5108 HOST_WIDE_INT size = int_size_in_bytes (type); 5109 gcc_assert (size <= 16); 5110 5111 return function_arg_record_value (type, mode, slotno, named, regbase); 5112 } 5113 5114 /* Unions up to 16 bytes in size are passed in integer registers. */ 5115 else if (type && TREE_CODE (type) == UNION_TYPE) 5116 { 5117 HOST_WIDE_INT size = int_size_in_bytes (type); 5118 gcc_assert (size <= 16); 5119 5120 return function_arg_union_value (size, mode, slotno, regno); 5121 } 5122 5123 /* v9 fp args in reg slots beyond the int reg slots get passed in regs 5124 but also have the slot allocated for them. 5125 If no prototype is in scope fp values in register slots get passed 5126 in two places, either fp regs and int regs or fp regs and memory. */ 5127 else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) 5128 && SPARC_FP_REG_P (regno)) 5129 { 5130 rtx reg = gen_rtx_REG (mode, regno); 5131 if (cum->prototype_p || cum->libcall_p) 5132 { 5133 /* "* 2" because fp reg numbers are recorded in 4 byte 5134 quantities. */ 5135#if 0 5136 /* ??? This will cause the value to be passed in the fp reg and 5137 in the stack. When a prototype exists we want to pass the 5138 value in the reg but reserve space on the stack. That's an 5139 optimization, and is deferred [for a bit]. */ 5140 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2) 5141 return gen_rtx_PARALLEL (mode, 5142 gen_rtvec (2, 5143 gen_rtx_EXPR_LIST (VOIDmode, 5144 NULL_RTX, const0_rtx), 5145 gen_rtx_EXPR_LIST (VOIDmode, 5146 reg, const0_rtx))); 5147 else 5148#else 5149 /* ??? It seems that passing back a register even when past 5150 the area declared by REG_PARM_STACK_SPACE will allocate 5151 space appropriately, and will not copy the data onto the 5152 stack, exactly as we desire. 5153 5154 This is due to locate_and_pad_parm being called in 5155 expand_call whenever reg_parm_stack_space > 0, which 5156 while beneficial to our example here, would seem to be 5157 in error from what had been intended. Ho hum... -- r~ */ 5158#endif 5159 return reg; 5160 } 5161 else 5162 { 5163 rtx v0, v1; 5164 5165 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) 5166 { 5167 int intreg; 5168 5169 /* On incoming, we don't need to know that the value 5170 is passed in %f0 and %i0, and it confuses other parts 5171 causing needless spillage even on the simplest cases. */ 5172 if (incoming_p) 5173 return reg; 5174 5175 intreg = (SPARC_OUTGOING_INT_ARG_FIRST 5176 + (regno - SPARC_FP_ARG_FIRST) / 2); 5177 5178 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 5179 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), 5180 const0_rtx); 5181 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 5182 } 5183 else 5184 { 5185 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 5186 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 5187 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 5188 } 5189 } 5190 } 5191 5192 /* All other aggregate types are passed in an integer register in a mode 5193 corresponding to the size of the type. */ 5194 else if (type && AGGREGATE_TYPE_P (type)) 5195 { 5196 HOST_WIDE_INT size = int_size_in_bytes (type); 5197 gcc_assert (size <= 16); 5198 5199 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); 5200 } 5201 5202 return gen_rtx_REG (mode, regno); 5203} 5204 5205/* For an arg passed partly in registers and partly in memory, 5206 this is the number of bytes of registers used. 5207 For args passed entirely in registers or entirely in memory, zero. 5208 5209 Any arg that starts in the first 6 regs but won't entirely fit in them 5210 needs partial registers on v8. On v9, structures with integer 5211 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp 5212 values that begin in the last fp reg [where "last fp reg" varies with the 5213 mode] will be split between that reg and memory. */ 5214 5215static int 5216sparc_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode, 5217 tree type, bool named) 5218{ 5219 int slotno, regno, padding; 5220 5221 /* We pass 0 for incoming_p here, it doesn't matter. */ 5222 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); 5223 5224 if (slotno == -1) 5225 return 0; 5226 5227 if (TARGET_ARCH32) 5228 { 5229 if ((slotno + (mode == BLKmode 5230 ? ROUND_ADVANCE (int_size_in_bytes (type)) 5231 : ROUND_ADVANCE (GET_MODE_SIZE (mode)))) 5232 > SPARC_INT_ARG_MAX) 5233 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD; 5234 } 5235 else 5236 { 5237 /* We are guaranteed by pass_by_reference that the size of the 5238 argument is not greater than 16 bytes, so we only need to return 5239 one word if the argument is partially passed in registers. */ 5240 5241 if (type && AGGREGATE_TYPE_P (type)) 5242 { 5243 int size = int_size_in_bytes (type); 5244 5245 if (size > UNITS_PER_WORD 5246 && slotno == SPARC_INT_ARG_MAX - 1) 5247 return UNITS_PER_WORD; 5248 } 5249 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT 5250 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 5251 && ! (TARGET_FPU && named))) 5252 { 5253 /* The complex types are passed as packed types. */ 5254 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 5255 && slotno == SPARC_INT_ARG_MAX - 1) 5256 return UNITS_PER_WORD; 5257 } 5258 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5259 { 5260 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) 5261 > SPARC_FP_ARG_MAX) 5262 return UNITS_PER_WORD; 5263 } 5264 } 5265 5266 return 0; 5267} 5268 5269/* Handle the TARGET_PASS_BY_REFERENCE target hook. 5270 Specify whether to pass the argument by reference. */ 5271 5272static bool 5273sparc_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, 5274 enum machine_mode mode, tree type, 5275 bool named ATTRIBUTE_UNUSED) 5276{ 5277 if (TARGET_ARCH32) 5278 /* Original SPARC 32-bit ABI says that structures and unions, 5279 and quad-precision floats are passed by reference. For Pascal, 5280 also pass arrays by reference. All other base types are passed 5281 in registers. 5282 5283 Extended ABI (as implemented by the Sun compiler) says that all 5284 complex floats are passed by reference. Pass complex integers 5285 in registers up to 8 bytes. More generally, enforce the 2-word 5286 cap for passing arguments in registers. 5287 5288 Vector ABI (as implemented by the Sun VIS SDK) says that vector 5289 integers are passed like floats of the same size, that is in 5290 registers up to 8 bytes. Pass all vector floats by reference 5291 like structure and unions. */ 5292 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type))) 5293 || mode == SCmode 5294 /* Catch CDImode, TFmode, DCmode and TCmode. */ 5295 || GET_MODE_SIZE (mode) > 8 5296 || (type 5297 && TREE_CODE (type) == VECTOR_TYPE 5298 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)); 5299 else 5300 /* Original SPARC 64-bit ABI says that structures and unions 5301 smaller than 16 bytes are passed in registers, as well as 5302 all other base types. 5303 5304 Extended ABI (as implemented by the Sun compiler) says that 5305 complex floats are passed in registers up to 16 bytes. Pass 5306 all complex integers in registers up to 16 bytes. More generally, 5307 enforce the 2-word cap for passing arguments in registers. 5308 5309 Vector ABI (as implemented by the Sun VIS SDK) says that vector 5310 integers are passed like floats of the same size, that is in 5311 registers (up to 16 bytes). Pass all vector floats like structure 5312 and unions. */ 5313 return ((type 5314 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE) 5315 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16) 5316 /* Catch CTImode and TCmode. */ 5317 || GET_MODE_SIZE (mode) > 16); 5318} 5319 5320/* Handle the FUNCTION_ARG_ADVANCE macro. 5321 Update the data in CUM to advance over an argument 5322 of mode MODE and data type TYPE. 5323 TYPE is null for libcalls where that information may not be available. */ 5324 5325void 5326function_arg_advance (struct sparc_args *cum, enum machine_mode mode, 5327 tree type, int named) 5328{ 5329 int slotno, regno, padding; 5330 5331 /* We pass 0 for incoming_p here, it doesn't matter. */ 5332 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding); 5333 5334 /* If register required leading padding, add it. */ 5335 if (slotno != -1) 5336 cum->words += padding; 5337 5338 if (TARGET_ARCH32) 5339 { 5340 cum->words += (mode != BLKmode 5341 ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) 5342 : ROUND_ADVANCE (int_size_in_bytes (type))); 5343 } 5344 else 5345 { 5346 if (type && AGGREGATE_TYPE_P (type)) 5347 { 5348 int size = int_size_in_bytes (type); 5349 5350 if (size <= 8) 5351 ++cum->words; 5352 else if (size <= 16) 5353 cum->words += 2; 5354 else /* passed by reference */ 5355 ++cum->words; 5356 } 5357 else 5358 { 5359 cum->words += (mode != BLKmode 5360 ? ROUND_ADVANCE (GET_MODE_SIZE (mode)) 5361 : ROUND_ADVANCE (int_size_in_bytes (type))); 5362 } 5363 } 5364} 5365 5366/* Handle the FUNCTION_ARG_PADDING macro. 5367 For the 64 bit ABI structs are always stored left shifted in their 5368 argument slot. */ 5369 5370enum direction 5371function_arg_padding (enum machine_mode mode, tree type) 5372{ 5373 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type)) 5374 return upward; 5375 5376 /* Fall back to the default. */ 5377 return DEFAULT_FUNCTION_ARG_PADDING (mode, type); 5378} 5379 5380/* Handle the TARGET_RETURN_IN_MEMORY target hook. 5381 Specify whether to return the return value in memory. */ 5382 5383static bool 5384sparc_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) 5385{ 5386 if (TARGET_ARCH32) 5387 /* Original SPARC 32-bit ABI says that structures and unions, 5388 and quad-precision floats are returned in memory. All other 5389 base types are returned in registers. 5390 5391 Extended ABI (as implemented by the Sun compiler) says that 5392 all complex floats are returned in registers (8 FP registers 5393 at most for '_Complex long double'). Return all complex integers 5394 in registers (4 at most for '_Complex long long'). 5395 5396 Vector ABI (as implemented by the Sun VIS SDK) says that vector 5397 integers are returned like floats of the same size, that is in 5398 registers up to 8 bytes and in memory otherwise. Return all 5399 vector floats in memory like structure and unions; note that 5400 they always have BLKmode like the latter. */ 5401 return (TYPE_MODE (type) == BLKmode 5402 || TYPE_MODE (type) == TFmode 5403 || (TREE_CODE (type) == VECTOR_TYPE 5404 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)); 5405 else 5406 /* Original SPARC 64-bit ABI says that structures and unions 5407 smaller than 32 bytes are returned in registers, as well as 5408 all other base types. 5409 5410 Extended ABI (as implemented by the Sun compiler) says that all 5411 complex floats are returned in registers (8 FP registers at most 5412 for '_Complex long double'). Return all complex integers in 5413 registers (4 at most for '_Complex TItype'). 5414 5415 Vector ABI (as implemented by the Sun VIS SDK) says that vector 5416 integers are returned like floats of the same size, that is in 5417 registers. Return all vector floats like structure and unions; 5418 note that they always have BLKmode like the latter. */ 5419 return ((TYPE_MODE (type) == BLKmode 5420 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32)); 5421} 5422 5423/* Handle the TARGET_STRUCT_VALUE target hook. 5424 Return where to find the structure return value address. */ 5425 5426static rtx 5427sparc_struct_value_rtx (tree fndecl, int incoming) 5428{ 5429 if (TARGET_ARCH64) 5430 return 0; 5431 else 5432 { 5433 rtx mem; 5434 5435 if (incoming) 5436 mem = gen_rtx_MEM (Pmode, plus_constant (frame_pointer_rtx, 5437 STRUCT_VALUE_OFFSET)); 5438 else 5439 mem = gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, 5440 STRUCT_VALUE_OFFSET)); 5441 5442 /* Only follow the SPARC ABI for fixed-size structure returns. 5443 Variable size structure returns are handled per the normal 5444 procedures in GCC. This is enabled by -mstd-struct-return */ 5445 if (incoming == 2 5446 && sparc_std_struct_return 5447 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl)) 5448 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST) 5449 { 5450 /* We must check and adjust the return address, as it is 5451 optional as to whether the return object is really 5452 provided. */ 5453 rtx ret_rtx = gen_rtx_REG (Pmode, 31); 5454 rtx scratch = gen_reg_rtx (SImode); 5455 rtx endlab = gen_label_rtx (); 5456 5457 /* Calculate the return object size */ 5458 tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl)); 5459 rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff); 5460 /* Construct a temporary return value */ 5461 rtx temp_val = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0); 5462 5463 /* Implement SPARC 32-bit psABI callee returns struck checking 5464 requirements: 5465 5466 Fetch the instruction where we will return to and see if 5467 it's an unimp instruction (the most significant 10 bits 5468 will be zero). */ 5469 emit_move_insn (scratch, gen_rtx_MEM (SImode, 5470 plus_constant (ret_rtx, 8))); 5471 /* Assume the size is valid and pre-adjust */ 5472 emit_insn (gen_add3_insn (ret_rtx, ret_rtx, GEN_INT (4))); 5473 emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode, 0, endlab); 5474 emit_insn (gen_sub3_insn (ret_rtx, ret_rtx, GEN_INT (4))); 5475 /* Assign stack temp: 5476 Write the address of the memory pointed to by temp_val into 5477 the memory pointed to by mem */ 5478 emit_move_insn (mem, XEXP (temp_val, 0)); 5479 emit_label (endlab); 5480 } 5481 5482 set_mem_alias_set (mem, struct_value_alias_set); 5483 return mem; 5484 } 5485} 5486 5487/* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros. 5488 For v9, function return values are subject to the same rules as arguments, 5489 except that up to 32 bytes may be returned in registers. */ 5490 5491rtx 5492function_value (tree type, enum machine_mode mode, int incoming_p) 5493{ 5494 /* Beware that the two values are swapped here wrt function_arg. */ 5495 int regbase = (incoming_p 5496 ? SPARC_OUTGOING_INT_ARG_FIRST 5497 : SPARC_INCOMING_INT_ARG_FIRST); 5498 enum mode_class mclass = GET_MODE_CLASS (mode); 5499 int regno; 5500 5501 /* Vector types deserve special treatment because they are polymorphic wrt 5502 their mode, depending upon whether VIS instructions are enabled. */ 5503 if (type && TREE_CODE (type) == VECTOR_TYPE) 5504 { 5505 HOST_WIDE_INT size = int_size_in_bytes (type); 5506 gcc_assert ((TARGET_ARCH32 && size <= 8) 5507 || (TARGET_ARCH64 && size <= 32)); 5508 5509 if (mode == BLKmode) 5510 return function_arg_vector_value (size, 5511 TYPE_MODE (TREE_TYPE (type)), 5512 SPARC_FP_ARG_FIRST); 5513 else 5514 mclass = MODE_FLOAT; 5515 } 5516 5517 if (TARGET_ARCH64 && type) 5518 { 5519 /* Structures up to 32 bytes in size are returned in registers. */ 5520 if (TREE_CODE (type) == RECORD_TYPE) 5521 { 5522 HOST_WIDE_INT size = int_size_in_bytes (type); 5523 gcc_assert (size <= 32); 5524 5525 return function_arg_record_value (type, mode, 0, 1, regbase); 5526 } 5527 5528 /* Unions up to 32 bytes in size are returned in integer registers. */ 5529 else if (TREE_CODE (type) == UNION_TYPE) 5530 { 5531 HOST_WIDE_INT size = int_size_in_bytes (type); 5532 gcc_assert (size <= 32); 5533 5534 return function_arg_union_value (size, mode, 0, regbase); 5535 } 5536 5537 /* Objects that require it are returned in FP registers. */ 5538 else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) 5539 ; 5540 5541 /* All other aggregate types are returned in an integer register in a 5542 mode corresponding to the size of the type. */ 5543 else if (AGGREGATE_TYPE_P (type)) 5544 { 5545 /* All other aggregate types are passed in an integer register 5546 in a mode corresponding to the size of the type. */ 5547 HOST_WIDE_INT size = int_size_in_bytes (type); 5548 gcc_assert (size <= 32); 5549 5550 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); 5551 5552 /* ??? We probably should have made the same ABI change in 5553 3.4.0 as the one we made for unions. The latter was 5554 required by the SCD though, while the former is not 5555 specified, so we favored compatibility and efficiency. 5556 5557 Now we're stuck for aggregates larger than 16 bytes, 5558 because OImode vanished in the meantime. Let's not 5559 try to be unduly clever, and simply follow the ABI 5560 for unions in that case. */ 5561 if (mode == BLKmode) 5562 return function_arg_union_value (size, mode, 0, regbase); 5563 else 5564 mclass = MODE_INT; 5565 } 5566 5567 /* This must match PROMOTE_FUNCTION_MODE. */ 5568 else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD) 5569 mode = word_mode; 5570 } 5571 5572 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU) 5573 regno = SPARC_FP_ARG_FIRST; 5574 else 5575 regno = regbase; 5576 5577 return gen_rtx_REG (mode, regno); 5578} 5579 5580/* Do what is necessary for `va_start'. We look at the current function 5581 to determine if stdarg or varargs is used and return the address of 5582 the first unnamed parameter. */ 5583 5584static rtx 5585sparc_builtin_saveregs (void) 5586{ 5587 int first_reg = current_function_args_info.words; 5588 rtx address; 5589 int regno; 5590 5591 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++) 5592 emit_move_insn (gen_rtx_MEM (word_mode, 5593 gen_rtx_PLUS (Pmode, 5594 frame_pointer_rtx, 5595 GEN_INT (FIRST_PARM_OFFSET (0) 5596 + (UNITS_PER_WORD 5597 * regno)))), 5598 gen_rtx_REG (word_mode, 5599 SPARC_INCOMING_INT_ARG_FIRST + regno)); 5600 5601 address = gen_rtx_PLUS (Pmode, 5602 frame_pointer_rtx, 5603 GEN_INT (FIRST_PARM_OFFSET (0) 5604 + UNITS_PER_WORD * first_reg)); 5605 5606 return address; 5607} 5608 5609/* Implement `va_start' for stdarg. */ 5610 5611void 5612sparc_va_start (tree valist, rtx nextarg) 5613{ 5614 nextarg = expand_builtin_saveregs (); 5615 std_expand_builtin_va_start (valist, nextarg); 5616} 5617 5618/* Implement `va_arg' for stdarg. */ 5619 5620static tree 5621sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) 5622{ 5623 HOST_WIDE_INT size, rsize, align; 5624 tree addr, incr; 5625 bool indirect; 5626 tree ptrtype = build_pointer_type (type); 5627 5628 if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) 5629 { 5630 indirect = true; 5631 size = rsize = UNITS_PER_WORD; 5632 align = 0; 5633 } 5634 else 5635 { 5636 indirect = false; 5637 size = int_size_in_bytes (type); 5638 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; 5639 align = 0; 5640 5641 if (TARGET_ARCH64) 5642 { 5643 /* For SPARC64, objects requiring 16-byte alignment get it. */ 5644 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) 5645 align = 2 * UNITS_PER_WORD; 5646 5647 /* SPARC-V9 ABI states that structures up to 16 bytes in size 5648 are left-justified in their slots. */ 5649 if (AGGREGATE_TYPE_P (type)) 5650 { 5651 if (size == 0) 5652 size = rsize = UNITS_PER_WORD; 5653 else 5654 size = rsize; 5655 } 5656 } 5657 } 5658 5659 incr = valist; 5660 if (align) 5661 { 5662 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, 5663 ssize_int (align - 1))); 5664 incr = fold (build2 (BIT_AND_EXPR, ptr_type_node, incr, 5665 ssize_int (-align))); 5666 } 5667 5668 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue); 5669 addr = incr; 5670 5671 if (BYTES_BIG_ENDIAN && size < rsize) 5672 addr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, 5673 ssize_int (rsize - size))); 5674 5675 if (indirect) 5676 { 5677 addr = fold_convert (build_pointer_type (ptrtype), addr); 5678 addr = build_va_arg_indirect_ref (addr); 5679 } 5680 /* If the address isn't aligned properly for the type, 5681 we may need to copy to a temporary. 5682 FIXME: This is inefficient. Usually we can do this 5683 in registers. */ 5684 else if (align == 0 5685 && TYPE_ALIGN (type) > BITS_PER_WORD) 5686 { 5687 tree tmp = create_tmp_var (type, "va_arg_tmp"); 5688 tree dest_addr = build_fold_addr_expr (tmp); 5689 5690 tree copy = build_function_call_expr 5691 (implicit_built_in_decls[BUILT_IN_MEMCPY], 5692 tree_cons (NULL_TREE, dest_addr, 5693 tree_cons (NULL_TREE, addr, 5694 tree_cons (NULL_TREE, size_int (rsize), 5695 NULL_TREE)))); 5696 5697 gimplify_and_add (copy, pre_p); 5698 addr = dest_addr; 5699 } 5700 else 5701 addr = fold_convert (ptrtype, addr); 5702 5703 incr = fold (build2 (PLUS_EXPR, ptr_type_node, incr, ssize_int (rsize))); 5704 incr = build2 (MODIFY_EXPR, ptr_type_node, valist, incr); 5705 gimplify_and_add (incr, post_p); 5706 5707 return build_va_arg_indirect_ref (addr); 5708} 5709 5710/* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook. 5711 Specify whether the vector mode is supported by the hardware. */ 5712 5713static bool 5714sparc_vector_mode_supported_p (enum machine_mode mode) 5715{ 5716 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false; 5717} 5718 5719/* Return the string to output an unconditional branch to LABEL, which is 5720 the operand number of the label. 5721 5722 DEST is the destination insn (i.e. the label), INSN is the source. */ 5723 5724const char * 5725output_ubranch (rtx dest, int label, rtx insn) 5726{ 5727 static char string[64]; 5728 bool v9_form = false; 5729 char *p; 5730 5731 if (TARGET_V9 && INSN_ADDRESSES_SET_P ()) 5732 { 5733 int delta = (INSN_ADDRESSES (INSN_UID (dest)) 5734 - INSN_ADDRESSES (INSN_UID (insn))); 5735 /* Leave some instructions for "slop". */ 5736 if (delta >= -260000 && delta < 260000) 5737 v9_form = true; 5738 } 5739 5740 if (v9_form) 5741 strcpy (string, "ba%*,pt\t%%xcc, "); 5742 else 5743 strcpy (string, "b%*\t"); 5744 5745 p = strchr (string, '\0'); 5746 *p++ = '%'; 5747 *p++ = 'l'; 5748 *p++ = '0' + label; 5749 *p++ = '%'; 5750 *p++ = '('; 5751 *p = '\0'; 5752 5753 return string; 5754} 5755 5756/* Return the string to output a conditional branch to LABEL, which is 5757 the operand number of the label. OP is the conditional expression. 5758 XEXP (OP, 0) is assumed to be a condition code register (integer or 5759 floating point) and its mode specifies what kind of comparison we made. 5760 5761 DEST is the destination insn (i.e. the label), INSN is the source. 5762 5763 REVERSED is nonzero if we should reverse the sense of the comparison. 5764 5765 ANNUL is nonzero if we should generate an annulling branch. */ 5766 5767const char * 5768output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, 5769 rtx insn) 5770{ 5771 static char string[64]; 5772 enum rtx_code code = GET_CODE (op); 5773 rtx cc_reg = XEXP (op, 0); 5774 enum machine_mode mode = GET_MODE (cc_reg); 5775 const char *labelno, *branch; 5776 int spaces = 8, far; 5777 char *p; 5778 5779 /* v9 branches are limited to +-1MB. If it is too far away, 5780 change 5781 5782 bne,pt %xcc, .LC30 5783 5784 to 5785 5786 be,pn %xcc, .+12 5787 nop 5788 ba .LC30 5789 5790 and 5791 5792 fbne,a,pn %fcc2, .LC29 5793 5794 to 5795 5796 fbe,pt %fcc2, .+16 5797 nop 5798 ba .LC29 */ 5799 5800 far = TARGET_V9 && (get_attr_length (insn) >= 3); 5801 if (reversed ^ far) 5802 { 5803 /* Reversal of FP compares takes care -- an ordered compare 5804 becomes an unordered compare and vice versa. */ 5805 if (mode == CCFPmode || mode == CCFPEmode) 5806 code = reverse_condition_maybe_unordered (code); 5807 else 5808 code = reverse_condition (code); 5809 } 5810 5811 /* Start by writing the branch condition. */ 5812 if (mode == CCFPmode || mode == CCFPEmode) 5813 { 5814 switch (code) 5815 { 5816 case NE: 5817 branch = "fbne"; 5818 break; 5819 case EQ: 5820 branch = "fbe"; 5821 break; 5822 case GE: 5823 branch = "fbge"; 5824 break; 5825 case GT: 5826 branch = "fbg"; 5827 break; 5828 case LE: 5829 branch = "fble"; 5830 break; 5831 case LT: 5832 branch = "fbl"; 5833 break; 5834 case UNORDERED: 5835 branch = "fbu"; 5836 break; 5837 case ORDERED: 5838 branch = "fbo"; 5839 break; 5840 case UNGT: 5841 branch = "fbug"; 5842 break; 5843 case UNLT: 5844 branch = "fbul"; 5845 break; 5846 case UNEQ: 5847 branch = "fbue"; 5848 break; 5849 case UNGE: 5850 branch = "fbuge"; 5851 break; 5852 case UNLE: 5853 branch = "fbule"; 5854 break; 5855 case LTGT: 5856 branch = "fblg"; 5857 break; 5858 5859 default: 5860 gcc_unreachable (); 5861 } 5862 5863 /* ??? !v9: FP branches cannot be preceded by another floating point 5864 insn. Because there is currently no concept of pre-delay slots, 5865 we can fix this only by always emitting a nop before a floating 5866 point branch. */ 5867 5868 string[0] = '\0'; 5869 if (! TARGET_V9) 5870 strcpy (string, "nop\n\t"); 5871 strcat (string, branch); 5872 } 5873 else 5874 { 5875 switch (code) 5876 { 5877 case NE: 5878 branch = "bne"; 5879 break; 5880 case EQ: 5881 branch = "be"; 5882 break; 5883 case GE: 5884 if (mode == CC_NOOVmode || mode == CCX_NOOVmode) 5885 branch = "bpos"; 5886 else 5887 branch = "bge"; 5888 break; 5889 case GT: 5890 branch = "bg"; 5891 break; 5892 case LE: 5893 branch = "ble"; 5894 break; 5895 case LT: 5896 if (mode == CC_NOOVmode || mode == CCX_NOOVmode) 5897 branch = "bneg"; 5898 else 5899 branch = "bl"; 5900 break; 5901 case GEU: 5902 branch = "bgeu"; 5903 break; 5904 case GTU: 5905 branch = "bgu"; 5906 break; 5907 case LEU: 5908 branch = "bleu"; 5909 break; 5910 case LTU: 5911 branch = "blu"; 5912 break; 5913 5914 default: 5915 gcc_unreachable (); 5916 } 5917 strcpy (string, branch); 5918 } 5919 spaces -= strlen (branch); 5920 p = strchr (string, '\0'); 5921 5922 /* Now add the annulling, the label, and a possible noop. */ 5923 if (annul && ! far) 5924 { 5925 strcpy (p, ",a"); 5926 p += 2; 5927 spaces -= 2; 5928 } 5929 5930 if (TARGET_V9) 5931 { 5932 rtx note; 5933 int v8 = 0; 5934 5935 if (! far && insn && INSN_ADDRESSES_SET_P ()) 5936 { 5937 int delta = (INSN_ADDRESSES (INSN_UID (dest)) 5938 - INSN_ADDRESSES (INSN_UID (insn))); 5939 /* Leave some instructions for "slop". */ 5940 if (delta < -260000 || delta >= 260000) 5941 v8 = 1; 5942 } 5943 5944 if (mode == CCFPmode || mode == CCFPEmode) 5945 { 5946 static char v9_fcc_labelno[] = "%%fccX, "; 5947 /* Set the char indicating the number of the fcc reg to use. */ 5948 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; 5949 labelno = v9_fcc_labelno; 5950 if (v8) 5951 { 5952 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG); 5953 labelno = ""; 5954 } 5955 } 5956 else if (mode == CCXmode || mode == CCX_NOOVmode) 5957 { 5958 labelno = "%%xcc, "; 5959 gcc_assert (! v8); 5960 } 5961 else 5962 { 5963 labelno = "%%icc, "; 5964 if (v8) 5965 labelno = ""; 5966 } 5967 5968 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 5969 { 5970 strcpy (p, 5971 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) 5972 ? ",pt" : ",pn"); 5973 p += 3; 5974 spaces -= 3; 5975 } 5976 } 5977 else 5978 labelno = ""; 5979 5980 if (spaces > 0) 5981 *p++ = '\t'; 5982 else 5983 *p++ = ' '; 5984 strcpy (p, labelno); 5985 p = strchr (p, '\0'); 5986 if (far) 5987 { 5988 strcpy (p, ".+12\n\t nop\n\tb\t"); 5989 /* Skip the next insn if requested or 5990 if we know that it will be a nop. */ 5991 if (annul || ! final_sequence) 5992 p[3] = '6'; 5993 p += 14; 5994 } 5995 *p++ = '%'; 5996 *p++ = 'l'; 5997 *p++ = label + '0'; 5998 *p++ = '%'; 5999 *p++ = '#'; 6000 *p = '\0'; 6001 6002 return string; 6003} 6004 6005/* Emit a library call comparison between floating point X and Y. 6006 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). 6007 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode 6008 values as arguments instead of the TFmode registers themselves, 6009 that's why we cannot call emit_float_lib_cmp. */ 6010void 6011sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison) 6012{ 6013 const char *qpfunc; 6014 rtx slot0, slot1, result, tem, tem2; 6015 enum machine_mode mode; 6016 6017 switch (comparison) 6018 { 6019 case EQ: 6020 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq"; 6021 break; 6022 6023 case NE: 6024 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne"; 6025 break; 6026 6027 case GT: 6028 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt"; 6029 break; 6030 6031 case GE: 6032 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge"; 6033 break; 6034 6035 case LT: 6036 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt"; 6037 break; 6038 6039 case LE: 6040 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle"; 6041 break; 6042 6043 case ORDERED: 6044 case UNORDERED: 6045 case UNGT: 6046 case UNLT: 6047 case UNEQ: 6048 case UNGE: 6049 case UNLE: 6050 case LTGT: 6051 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp"; 6052 break; 6053 6054 default: 6055 gcc_unreachable (); 6056 } 6057 6058 if (TARGET_ARCH64) 6059 { 6060 if (GET_CODE (x) != MEM) 6061 { 6062 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); 6063 emit_move_insn (slot0, x); 6064 } 6065 else 6066 slot0 = x; 6067 6068 if (GET_CODE (y) != MEM) 6069 { 6070 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0); 6071 emit_move_insn (slot1, y); 6072 } 6073 else 6074 slot1 = y; 6075 6076 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, 6077 DImode, 2, 6078 XEXP (slot0, 0), Pmode, 6079 XEXP (slot1, 0), Pmode); 6080 6081 mode = DImode; 6082 } 6083 else 6084 { 6085 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL, 6086 SImode, 2, 6087 x, TFmode, y, TFmode); 6088 6089 mode = SImode; 6090 } 6091 6092 6093 /* Immediately move the result of the libcall into a pseudo 6094 register so reload doesn't clobber the value if it needs 6095 the return register for a spill reg. */ 6096 result = gen_reg_rtx (mode); 6097 emit_move_insn (result, hard_libcall_value (mode)); 6098 6099 switch (comparison) 6100 { 6101 default: 6102 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0); 6103 break; 6104 case ORDERED: 6105 case UNORDERED: 6106 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE, 6107 NULL_RTX, mode, 0); 6108 break; 6109 case UNGT: 6110 case UNGE: 6111 emit_cmp_insn (result, const1_rtx, 6112 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0); 6113 break; 6114 case UNLE: 6115 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0); 6116 break; 6117 case UNLT: 6118 tem = gen_reg_rtx (mode); 6119 if (TARGET_ARCH32) 6120 emit_insn (gen_andsi3 (tem, result, const1_rtx)); 6121 else 6122 emit_insn (gen_anddi3 (tem, result, const1_rtx)); 6123 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0); 6124 break; 6125 case UNEQ: 6126 case LTGT: 6127 tem = gen_reg_rtx (mode); 6128 if (TARGET_ARCH32) 6129 emit_insn (gen_addsi3 (tem, result, const1_rtx)); 6130 else 6131 emit_insn (gen_adddi3 (tem, result, const1_rtx)); 6132 tem2 = gen_reg_rtx (mode); 6133 if (TARGET_ARCH32) 6134 emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); 6135 else 6136 emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); 6137 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE, 6138 NULL_RTX, mode, 0); 6139 break; 6140 } 6141} 6142 6143/* Generate an unsigned DImode to FP conversion. This is the same code 6144 optabs would emit if we didn't have TFmode patterns. */ 6145 6146void 6147sparc_emit_floatunsdi (rtx *operands, enum machine_mode mode) 6148{ 6149 rtx neglab, donelab, i0, i1, f0, in, out; 6150 6151 out = operands[0]; 6152 in = force_reg (DImode, operands[1]); 6153 neglab = gen_label_rtx (); 6154 donelab = gen_label_rtx (); 6155 i0 = gen_reg_rtx (DImode); 6156 i1 = gen_reg_rtx (DImode); 6157 f0 = gen_reg_rtx (mode); 6158 6159 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); 6160 6161 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in))); 6162 emit_jump_insn (gen_jump (donelab)); 6163 emit_barrier (); 6164 6165 emit_label (neglab); 6166 6167 emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); 6168 emit_insn (gen_anddi3 (i1, in, const1_rtx)); 6169 emit_insn (gen_iordi3 (i0, i0, i1)); 6170 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0))); 6171 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0))); 6172 6173 emit_label (donelab); 6174} 6175 6176/* Generate an FP to unsigned DImode conversion. This is the same code 6177 optabs would emit if we didn't have TFmode patterns. */ 6178 6179void 6180sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode) 6181{ 6182 rtx neglab, donelab, i0, i1, f0, in, out, limit; 6183 6184 out = operands[0]; 6185 in = force_reg (mode, operands[1]); 6186 neglab = gen_label_rtx (); 6187 donelab = gen_label_rtx (); 6188 i0 = gen_reg_rtx (DImode); 6189 i1 = gen_reg_rtx (DImode); 6190 limit = gen_reg_rtx (mode); 6191 f0 = gen_reg_rtx (mode); 6192 6193 emit_move_insn (limit, 6194 CONST_DOUBLE_FROM_REAL_VALUE ( 6195 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode)); 6196 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab); 6197 6198 emit_insn (gen_rtx_SET (VOIDmode, 6199 out, 6200 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in)))); 6201 emit_jump_insn (gen_jump (donelab)); 6202 emit_barrier (); 6203 6204 emit_label (neglab); 6205 6206 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_MINUS (mode, in, limit))); 6207 emit_insn (gen_rtx_SET (VOIDmode, 6208 i0, 6209 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0)))); 6210 emit_insn (gen_movdi (i1, const1_rtx)); 6211 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63))); 6212 emit_insn (gen_xordi3 (out, i0, i1)); 6213 6214 emit_label (donelab); 6215} 6216 6217/* Return the string to output a conditional branch to LABEL, testing 6218 register REG. LABEL is the operand number of the label; REG is the 6219 operand number of the reg. OP is the conditional expression. The mode 6220 of REG says what kind of comparison we made. 6221 6222 DEST is the destination insn (i.e. the label), INSN is the source. 6223 6224 REVERSED is nonzero if we should reverse the sense of the comparison. 6225 6226 ANNUL is nonzero if we should generate an annulling branch. */ 6227 6228const char * 6229output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, 6230 int annul, rtx insn) 6231{ 6232 static char string[64]; 6233 enum rtx_code code = GET_CODE (op); 6234 enum machine_mode mode = GET_MODE (XEXP (op, 0)); 6235 rtx note; 6236 int far; 6237 char *p; 6238 6239 /* branch on register are limited to +-128KB. If it is too far away, 6240 change 6241 6242 brnz,pt %g1, .LC30 6243 6244 to 6245 6246 brz,pn %g1, .+12 6247 nop 6248 ba,pt %xcc, .LC30 6249 6250 and 6251 6252 brgez,a,pn %o1, .LC29 6253 6254 to 6255 6256 brlz,pt %o1, .+16 6257 nop 6258 ba,pt %xcc, .LC29 */ 6259 6260 far = get_attr_length (insn) >= 3; 6261 6262 /* If not floating-point or if EQ or NE, we can just reverse the code. */ 6263 if (reversed ^ far) 6264 code = reverse_condition (code); 6265 6266 /* Only 64 bit versions of these instructions exist. */ 6267 gcc_assert (mode == DImode); 6268 6269 /* Start by writing the branch condition. */ 6270 6271 switch (code) 6272 { 6273 case NE: 6274 strcpy (string, "brnz"); 6275 break; 6276 6277 case EQ: 6278 strcpy (string, "brz"); 6279 break; 6280 6281 case GE: 6282 strcpy (string, "brgez"); 6283 break; 6284 6285 case LT: 6286 strcpy (string, "brlz"); 6287 break; 6288 6289 case LE: 6290 strcpy (string, "brlez"); 6291 break; 6292 6293 case GT: 6294 strcpy (string, "brgz"); 6295 break; 6296 6297 default: 6298 gcc_unreachable (); 6299 } 6300 6301 p = strchr (string, '\0'); 6302 6303 /* Now add the annulling, reg, label, and nop. */ 6304 if (annul && ! far) 6305 { 6306 strcpy (p, ",a"); 6307 p += 2; 6308 } 6309 6310 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 6311 { 6312 strcpy (p, 6313 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far) 6314 ? ",pt" : ",pn"); 6315 p += 3; 6316 } 6317 6318 *p = p < string + 8 ? '\t' : ' '; 6319 p++; 6320 *p++ = '%'; 6321 *p++ = '0' + reg; 6322 *p++ = ','; 6323 *p++ = ' '; 6324 if (far) 6325 { 6326 int veryfar = 1, delta; 6327 6328 if (INSN_ADDRESSES_SET_P ()) 6329 { 6330 delta = (INSN_ADDRESSES (INSN_UID (dest)) 6331 - INSN_ADDRESSES (INSN_UID (insn))); 6332 /* Leave some instructions for "slop". */ 6333 if (delta >= -260000 && delta < 260000) 6334 veryfar = 0; 6335 } 6336 6337 strcpy (p, ".+12\n\t nop\n\t"); 6338 /* Skip the next insn if requested or 6339 if we know that it will be a nop. */ 6340 if (annul || ! final_sequence) 6341 p[3] = '6'; 6342 p += 12; 6343 if (veryfar) 6344 { 6345 strcpy (p, "b\t"); 6346 p += 2; 6347 } 6348 else 6349 { 6350 strcpy (p, "ba,pt\t%%xcc, "); 6351 p += 13; 6352 } 6353 } 6354 *p++ = '%'; 6355 *p++ = 'l'; 6356 *p++ = '0' + label; 6357 *p++ = '%'; 6358 *p++ = '#'; 6359 *p = '\0'; 6360 6361 return string; 6362} 6363 6364/* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. 6365 Such instructions cannot be used in the delay slot of return insn on v9. 6366 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. 6367 */ 6368 6369static int 6370epilogue_renumber (register rtx *where, int test) 6371{ 6372 register const char *fmt; 6373 register int i; 6374 register enum rtx_code code; 6375 6376 if (*where == 0) 6377 return 0; 6378 6379 code = GET_CODE (*where); 6380 6381 switch (code) 6382 { 6383 case REG: 6384 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ 6385 return 1; 6386 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) 6387 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); 6388 case SCRATCH: 6389 case CC0: 6390 case PC: 6391 case CONST_INT: 6392 case CONST_DOUBLE: 6393 return 0; 6394 6395 /* Do not replace the frame pointer with the stack pointer because 6396 it can cause the delayed instruction to load below the stack. 6397 This occurs when instructions like: 6398 6399 (set (reg/i:SI 24 %i0) 6400 (mem/f:SI (plus:SI (reg/f:SI 30 %fp) 6401 (const_int -20 [0xffffffec])) 0)) 6402 6403 are in the return delayed slot. */ 6404 case PLUS: 6405 if (GET_CODE (XEXP (*where, 0)) == REG 6406 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM 6407 && (GET_CODE (XEXP (*where, 1)) != CONST_INT 6408 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) 6409 return 1; 6410 break; 6411 6412 case MEM: 6413 if (SPARC_STACK_BIAS 6414 && GET_CODE (XEXP (*where, 0)) == REG 6415 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) 6416 return 1; 6417 break; 6418 6419 default: 6420 break; 6421 } 6422 6423 fmt = GET_RTX_FORMAT (code); 6424 6425 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 6426 { 6427 if (fmt[i] == 'E') 6428 { 6429 register int j; 6430 for (j = XVECLEN (*where, i) - 1; j >= 0; j--) 6431 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) 6432 return 1; 6433 } 6434 else if (fmt[i] == 'e' 6435 && epilogue_renumber (&(XEXP (*where, i)), test)) 6436 return 1; 6437 } 6438 return 0; 6439} 6440 6441/* Leaf functions and non-leaf functions have different needs. */ 6442 6443static const int 6444reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; 6445 6446static const int 6447reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; 6448 6449static const int *const reg_alloc_orders[] = { 6450 reg_leaf_alloc_order, 6451 reg_nonleaf_alloc_order}; 6452 6453void 6454order_regs_for_local_alloc (void) 6455{ 6456 static int last_order_nonleaf = 1; 6457 6458 if (regs_ever_live[15] != last_order_nonleaf) 6459 { 6460 last_order_nonleaf = !last_order_nonleaf; 6461 memcpy ((char *) reg_alloc_order, 6462 (const char *) reg_alloc_orders[last_order_nonleaf], 6463 FIRST_PSEUDO_REGISTER * sizeof (int)); 6464 } 6465} 6466 6467/* Return 1 if REG and MEM are legitimate enough to allow the various 6468 mem<-->reg splits to be run. */ 6469 6470int 6471sparc_splitdi_legitimate (rtx reg, rtx mem) 6472{ 6473 /* Punt if we are here by mistake. */ 6474 gcc_assert (reload_completed); 6475 6476 /* We must have an offsettable memory reference. */ 6477 if (! offsettable_memref_p (mem)) 6478 return 0; 6479 6480 /* If we have legitimate args for ldd/std, we do not want 6481 the split to happen. */ 6482 if ((REGNO (reg) % 2) == 0 6483 && mem_min_alignment (mem, 8)) 6484 return 0; 6485 6486 /* Success. */ 6487 return 1; 6488} 6489 6490/* Return 1 if x and y are some kind of REG and they refer to 6491 different hard registers. This test is guaranteed to be 6492 run after reload. */ 6493 6494int 6495sparc_absnegfloat_split_legitimate (rtx x, rtx y) 6496{ 6497 if (GET_CODE (x) != REG) 6498 return 0; 6499 if (GET_CODE (y) != REG) 6500 return 0; 6501 if (REGNO (x) == REGNO (y)) 6502 return 0; 6503 return 1; 6504} 6505 6506/* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. 6507 This makes them candidates for using ldd and std insns. 6508 6509 Note reg1 and reg2 *must* be hard registers. */ 6510 6511int 6512registers_ok_for_ldd_peep (rtx reg1, rtx reg2) 6513{ 6514 /* We might have been passed a SUBREG. */ 6515 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 6516 return 0; 6517 6518 if (REGNO (reg1) % 2 != 0) 6519 return 0; 6520 6521 /* Integer ldd is deprecated in SPARC V9 */ 6522 if (TARGET_V9 && REGNO (reg1) < 32) 6523 return 0; 6524 6525 return (REGNO (reg1) == REGNO (reg2) - 1); 6526} 6527 6528/* Return 1 if the addresses in mem1 and mem2 are suitable for use in 6529 an ldd or std insn. 6530 6531 This can only happen when addr1 and addr2, the addresses in mem1 6532 and mem2, are consecutive memory locations (addr1 + 4 == addr2). 6533 addr1 must also be aligned on a 64-bit boundary. 6534 6535 Also iff dependent_reg_rtx is not null it should not be used to 6536 compute the address for mem1, i.e. we cannot optimize a sequence 6537 like: 6538 ld [%o0], %o0 6539 ld [%o0 + 4], %o1 6540 to 6541 ldd [%o0], %o0 6542 nor: 6543 ld [%g3 + 4], %g3 6544 ld [%g3], %g2 6545 to 6546 ldd [%g3], %g2 6547 6548 But, note that the transformation from: 6549 ld [%g2 + 4], %g3 6550 ld [%g2], %g2 6551 to 6552 ldd [%g2], %g2 6553 is perfectly fine. Thus, the peephole2 patterns always pass us 6554 the destination register of the first load, never the second one. 6555 6556 For stores we don't have a similar problem, so dependent_reg_rtx is 6557 NULL_RTX. */ 6558 6559int 6560mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx) 6561{ 6562 rtx addr1, addr2; 6563 unsigned int reg1; 6564 HOST_WIDE_INT offset1; 6565 6566 /* The mems cannot be volatile. */ 6567 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) 6568 return 0; 6569 6570 /* MEM1 should be aligned on a 64-bit boundary. */ 6571 if (MEM_ALIGN (mem1) < 64) 6572 return 0; 6573 6574 addr1 = XEXP (mem1, 0); 6575 addr2 = XEXP (mem2, 0); 6576 6577 /* Extract a register number and offset (if used) from the first addr. */ 6578 if (GET_CODE (addr1) == PLUS) 6579 { 6580 /* If not a REG, return zero. */ 6581 if (GET_CODE (XEXP (addr1, 0)) != REG) 6582 return 0; 6583 else 6584 { 6585 reg1 = REGNO (XEXP (addr1, 0)); 6586 /* The offset must be constant! */ 6587 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) 6588 return 0; 6589 offset1 = INTVAL (XEXP (addr1, 1)); 6590 } 6591 } 6592 else if (GET_CODE (addr1) != REG) 6593 return 0; 6594 else 6595 { 6596 reg1 = REGNO (addr1); 6597 /* This was a simple (mem (reg)) expression. Offset is 0. */ 6598 offset1 = 0; 6599 } 6600 6601 /* Make sure the second address is a (mem (plus (reg) (const_int). */ 6602 if (GET_CODE (addr2) != PLUS) 6603 return 0; 6604 6605 if (GET_CODE (XEXP (addr2, 0)) != REG 6606 || GET_CODE (XEXP (addr2, 1)) != CONST_INT) 6607 return 0; 6608 6609 if (reg1 != REGNO (XEXP (addr2, 0))) 6610 return 0; 6611 6612 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) 6613 return 0; 6614 6615 /* The first offset must be evenly divisible by 8 to ensure the 6616 address is 64 bit aligned. */ 6617 if (offset1 % 8 != 0) 6618 return 0; 6619 6620 /* The offset for the second addr must be 4 more than the first addr. */ 6621 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) 6622 return 0; 6623 6624 /* All the tests passed. addr1 and addr2 are valid for ldd and std 6625 instructions. */ 6626 return 1; 6627} 6628 6629/* Return 1 if reg is a pseudo, or is the first register in 6630 a hard register pair. This makes it a candidate for use in 6631 ldd and std insns. */ 6632 6633int 6634register_ok_for_ldd (rtx reg) 6635{ 6636 /* We might have been passed a SUBREG. */ 6637 if (GET_CODE (reg) != REG) 6638 return 0; 6639 6640 if (REGNO (reg) < FIRST_PSEUDO_REGISTER) 6641 return (REGNO (reg) % 2 == 0); 6642 else 6643 return 1; 6644} 6645 6646/* Print operand X (an rtx) in assembler syntax to file FILE. 6647 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 6648 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 6649 6650void 6651print_operand (FILE *file, rtx x, int code) 6652{ 6653 switch (code) 6654 { 6655 case '#': 6656 /* Output an insn in a delay slot. */ 6657 if (final_sequence) 6658 sparc_indent_opcode = 1; 6659 else 6660 fputs ("\n\t nop", file); 6661 return; 6662 case '*': 6663 /* Output an annul flag if there's nothing for the delay slot and we 6664 are optimizing. This is always used with '(' below. 6665 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; 6666 this is a dbx bug. So, we only do this when optimizing. 6667 On UltraSPARC, a branch in a delay slot causes a pipeline flush. 6668 Always emit a nop in case the next instruction is a branch. */ 6669 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9)) 6670 fputs (",a", file); 6671 return; 6672 case '(': 6673 /* Output a 'nop' if there's nothing for the delay slot and we are 6674 not optimizing. This is always used with '*' above. */ 6675 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) 6676 fputs ("\n\t nop", file); 6677 else if (final_sequence) 6678 sparc_indent_opcode = 1; 6679 return; 6680 case ')': 6681 /* Output the right displacement from the saved PC on function return. 6682 The caller may have placed an "unimp" insn immediately after the call 6683 so we have to account for it. This insn is used in the 32-bit ABI 6684 when calling a function that returns a non zero-sized structure. The 6685 64-bit ABI doesn't have it. Be careful to have this test be the same 6686 as that used on the call. The exception here is that when 6687 sparc_std_struct_return is enabled, the psABI is followed exactly 6688 and the adjustment is made by the code in sparc_struct_value_rtx. 6689 The call emitted is the same when sparc_std_struct_return is 6690 present. */ 6691 if (! TARGET_ARCH64 6692 && current_function_returns_struct 6693 && ! sparc_std_struct_return 6694 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) 6695 == INTEGER_CST) 6696 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl)))) 6697 fputs ("12", file); 6698 else 6699 fputc ('8', file); 6700 return; 6701 case '_': 6702 /* Output the Embedded Medium/Anywhere code model base register. */ 6703 fputs (EMBMEDANY_BASE_REG, file); 6704 return; 6705 case '&': 6706 /* Print some local dynamic TLS name. */ 6707 assemble_name (file, get_some_local_dynamic_name ()); 6708 return; 6709 6710 case 'Y': 6711 /* Adjust the operand to take into account a RESTORE operation. */ 6712 if (GET_CODE (x) == CONST_INT) 6713 break; 6714 else if (GET_CODE (x) != REG) 6715 output_operand_lossage ("invalid %%Y operand"); 6716 else if (REGNO (x) < 8) 6717 fputs (reg_names[REGNO (x)], file); 6718 else if (REGNO (x) >= 24 && REGNO (x) < 32) 6719 fputs (reg_names[REGNO (x)-16], file); 6720 else 6721 output_operand_lossage ("invalid %%Y operand"); 6722 return; 6723 case 'L': 6724 /* Print out the low order register name of a register pair. */ 6725 if (WORDS_BIG_ENDIAN) 6726 fputs (reg_names[REGNO (x)+1], file); 6727 else 6728 fputs (reg_names[REGNO (x)], file); 6729 return; 6730 case 'H': 6731 /* Print out the high order register name of a register pair. */ 6732 if (WORDS_BIG_ENDIAN) 6733 fputs (reg_names[REGNO (x)], file); 6734 else 6735 fputs (reg_names[REGNO (x)+1], file); 6736 return; 6737 case 'R': 6738 /* Print out the second register name of a register pair or quad. 6739 I.e., R (%o0) => %o1. */ 6740 fputs (reg_names[REGNO (x)+1], file); 6741 return; 6742 case 'S': 6743 /* Print out the third register name of a register quad. 6744 I.e., S (%o0) => %o2. */ 6745 fputs (reg_names[REGNO (x)+2], file); 6746 return; 6747 case 'T': 6748 /* Print out the fourth register name of a register quad. 6749 I.e., T (%o0) => %o3. */ 6750 fputs (reg_names[REGNO (x)+3], file); 6751 return; 6752 case 'x': 6753 /* Print a condition code register. */ 6754 if (REGNO (x) == SPARC_ICC_REG) 6755 { 6756 /* We don't handle CC[X]_NOOVmode because they're not supposed 6757 to occur here. */ 6758 if (GET_MODE (x) == CCmode) 6759 fputs ("%icc", file); 6760 else if (GET_MODE (x) == CCXmode) 6761 fputs ("%xcc", file); 6762 else 6763 gcc_unreachable (); 6764 } 6765 else 6766 /* %fccN register */ 6767 fputs (reg_names[REGNO (x)], file); 6768 return; 6769 case 'm': 6770 /* Print the operand's address only. */ 6771 output_address (XEXP (x, 0)); 6772 return; 6773 case 'r': 6774 /* In this case we need a register. Use %g0 if the 6775 operand is const0_rtx. */ 6776 if (x == const0_rtx 6777 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) 6778 { 6779 fputs ("%g0", file); 6780 return; 6781 } 6782 else 6783 break; 6784 6785 case 'A': 6786 switch (GET_CODE (x)) 6787 { 6788 case IOR: fputs ("or", file); break; 6789 case AND: fputs ("and", file); break; 6790 case XOR: fputs ("xor", file); break; 6791 default: output_operand_lossage ("invalid %%A operand"); 6792 } 6793 return; 6794 6795 case 'B': 6796 switch (GET_CODE (x)) 6797 { 6798 case IOR: fputs ("orn", file); break; 6799 case AND: fputs ("andn", file); break; 6800 case XOR: fputs ("xnor", file); break; 6801 default: output_operand_lossage ("invalid %%B operand"); 6802 } 6803 return; 6804 6805 /* These are used by the conditional move instructions. */ 6806 case 'c' : 6807 case 'C': 6808 { 6809 enum rtx_code rc = GET_CODE (x); 6810 6811 if (code == 'c') 6812 { 6813 enum machine_mode mode = GET_MODE (XEXP (x, 0)); 6814 if (mode == CCFPmode || mode == CCFPEmode) 6815 rc = reverse_condition_maybe_unordered (GET_CODE (x)); 6816 else 6817 rc = reverse_condition (GET_CODE (x)); 6818 } 6819 switch (rc) 6820 { 6821 case NE: fputs ("ne", file); break; 6822 case EQ: fputs ("e", file); break; 6823 case GE: fputs ("ge", file); break; 6824 case GT: fputs ("g", file); break; 6825 case LE: fputs ("le", file); break; 6826 case LT: fputs ("l", file); break; 6827 case GEU: fputs ("geu", file); break; 6828 case GTU: fputs ("gu", file); break; 6829 case LEU: fputs ("leu", file); break; 6830 case LTU: fputs ("lu", file); break; 6831 case LTGT: fputs ("lg", file); break; 6832 case UNORDERED: fputs ("u", file); break; 6833 case ORDERED: fputs ("o", file); break; 6834 case UNLT: fputs ("ul", file); break; 6835 case UNLE: fputs ("ule", file); break; 6836 case UNGT: fputs ("ug", file); break; 6837 case UNGE: fputs ("uge", file); break; 6838 case UNEQ: fputs ("ue", file); break; 6839 default: output_operand_lossage (code == 'c' 6840 ? "invalid %%c operand" 6841 : "invalid %%C operand"); 6842 } 6843 return; 6844 } 6845 6846 /* These are used by the movr instruction pattern. */ 6847 case 'd': 6848 case 'D': 6849 { 6850 enum rtx_code rc = (code == 'd' 6851 ? reverse_condition (GET_CODE (x)) 6852 : GET_CODE (x)); 6853 switch (rc) 6854 { 6855 case NE: fputs ("ne", file); break; 6856 case EQ: fputs ("e", file); break; 6857 case GE: fputs ("gez", file); break; 6858 case LT: fputs ("lz", file); break; 6859 case LE: fputs ("lez", file); break; 6860 case GT: fputs ("gz", file); break; 6861 default: output_operand_lossage (code == 'd' 6862 ? "invalid %%d operand" 6863 : "invalid %%D operand"); 6864 } 6865 return; 6866 } 6867 6868 case 'b': 6869 { 6870 /* Print a sign-extended character. */ 6871 int i = trunc_int_for_mode (INTVAL (x), QImode); 6872 fprintf (file, "%d", i); 6873 return; 6874 } 6875 6876 case 'f': 6877 /* Operand must be a MEM; write its address. */ 6878 if (GET_CODE (x) != MEM) 6879 output_operand_lossage ("invalid %%f operand"); 6880 output_address (XEXP (x, 0)); 6881 return; 6882 6883 case 's': 6884 { 6885 /* Print a sign-extended 32-bit value. */ 6886 HOST_WIDE_INT i; 6887 if (GET_CODE(x) == CONST_INT) 6888 i = INTVAL (x); 6889 else if (GET_CODE(x) == CONST_DOUBLE) 6890 i = CONST_DOUBLE_LOW (x); 6891 else 6892 { 6893 output_operand_lossage ("invalid %%s operand"); 6894 return; 6895 } 6896 i = trunc_int_for_mode (i, SImode); 6897 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); 6898 return; 6899 } 6900 6901 case 0: 6902 /* Do nothing special. */ 6903 break; 6904 6905 default: 6906 /* Undocumented flag. */ 6907 output_operand_lossage ("invalid operand output code"); 6908 } 6909 6910 if (GET_CODE (x) == REG) 6911 fputs (reg_names[REGNO (x)], file); 6912 else if (GET_CODE (x) == MEM) 6913 { 6914 fputc ('[', file); 6915 /* Poor Sun assembler doesn't understand absolute addressing. */ 6916 if (CONSTANT_P (XEXP (x, 0))) 6917 fputs ("%g0+", file); 6918 output_address (XEXP (x, 0)); 6919 fputc (']', file); 6920 } 6921 else if (GET_CODE (x) == HIGH) 6922 { 6923 fputs ("%hi(", file); 6924 output_addr_const (file, XEXP (x, 0)); 6925 fputc (')', file); 6926 } 6927 else if (GET_CODE (x) == LO_SUM) 6928 { 6929 print_operand (file, XEXP (x, 0), 0); 6930 if (TARGET_CM_MEDMID) 6931 fputs ("+%l44(", file); 6932 else 6933 fputs ("+%lo(", file); 6934 output_addr_const (file, XEXP (x, 1)); 6935 fputc (')', file); 6936 } 6937 else if (GET_CODE (x) == CONST_DOUBLE 6938 && (GET_MODE (x) == VOIDmode 6939 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)) 6940 { 6941 if (CONST_DOUBLE_HIGH (x) == 0) 6942 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x)); 6943 else if (CONST_DOUBLE_HIGH (x) == -1 6944 && CONST_DOUBLE_LOW (x) < 0) 6945 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x)); 6946 else 6947 output_operand_lossage ("long long constant not a valid immediate operand"); 6948 } 6949 else if (GET_CODE (x) == CONST_DOUBLE) 6950 output_operand_lossage ("floating point constant not a valid immediate operand"); 6951 else { output_addr_const (file, x); } 6952} 6953 6954/* Target hook for assembling integer objects. The sparc version has 6955 special handling for aligned DI-mode objects. */ 6956 6957static bool 6958sparc_assemble_integer (rtx x, unsigned int size, int aligned_p) 6959{ 6960 /* ??? We only output .xword's for symbols and only then in environments 6961 where the assembler can handle them. */ 6962 if (aligned_p && size == 8 6963 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE)) 6964 { 6965 if (TARGET_V9) 6966 { 6967 assemble_integer_with_op ("\t.xword\t", x); 6968 return true; 6969 } 6970 else 6971 { 6972 assemble_aligned_integer (4, const0_rtx); 6973 assemble_aligned_integer (4, x); 6974 return true; 6975 } 6976 } 6977 return default_assemble_integer (x, size, aligned_p); 6978} 6979 6980/* Return the value of a code used in the .proc pseudo-op that says 6981 what kind of result this function returns. For non-C types, we pick 6982 the closest C type. */ 6983 6984#ifndef SHORT_TYPE_SIZE 6985#define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) 6986#endif 6987 6988#ifndef INT_TYPE_SIZE 6989#define INT_TYPE_SIZE BITS_PER_WORD 6990#endif 6991 6992#ifndef LONG_TYPE_SIZE 6993#define LONG_TYPE_SIZE BITS_PER_WORD 6994#endif 6995 6996#ifndef LONG_LONG_TYPE_SIZE 6997#define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) 6998#endif 6999 7000#ifndef FLOAT_TYPE_SIZE 7001#define FLOAT_TYPE_SIZE BITS_PER_WORD 7002#endif 7003 7004#ifndef DOUBLE_TYPE_SIZE 7005#define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 7006#endif 7007 7008#ifndef LONG_DOUBLE_TYPE_SIZE 7009#define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 7010#endif 7011 7012unsigned long 7013sparc_type_code (register tree type) 7014{ 7015 register unsigned long qualifiers = 0; 7016 register unsigned shift; 7017 7018 /* Only the first 30 bits of the qualifier are valid. We must refrain from 7019 setting more, since some assemblers will give an error for this. Also, 7020 we must be careful to avoid shifts of 32 bits or more to avoid getting 7021 unpredictable results. */ 7022 7023 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) 7024 { 7025 switch (TREE_CODE (type)) 7026 { 7027 case ERROR_MARK: 7028 return qualifiers; 7029 7030 case ARRAY_TYPE: 7031 qualifiers |= (3 << shift); 7032 break; 7033 7034 case FUNCTION_TYPE: 7035 case METHOD_TYPE: 7036 qualifiers |= (2 << shift); 7037 break; 7038 7039 case POINTER_TYPE: 7040 case REFERENCE_TYPE: 7041 case OFFSET_TYPE: 7042 qualifiers |= (1 << shift); 7043 break; 7044 7045 case RECORD_TYPE: 7046 return (qualifiers | 8); 7047 7048 case UNION_TYPE: 7049 case QUAL_UNION_TYPE: 7050 return (qualifiers | 9); 7051 7052 case ENUMERAL_TYPE: 7053 return (qualifiers | 10); 7054 7055 case VOID_TYPE: 7056 return (qualifiers | 16); 7057 7058 case INTEGER_TYPE: 7059 /* If this is a range type, consider it to be the underlying 7060 type. */ 7061 if (TREE_TYPE (type) != 0) 7062 break; 7063 7064 /* Carefully distinguish all the standard types of C, 7065 without messing up if the language is not C. We do this by 7066 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to 7067 look at both the names and the above fields, but that's redundant. 7068 Any type whose size is between two C types will be considered 7069 to be the wider of the two types. Also, we do not have a 7070 special code to use for "long long", so anything wider than 7071 long is treated the same. Note that we can't distinguish 7072 between "int" and "long" in this code if they are the same 7073 size, but that's fine, since neither can the assembler. */ 7074 7075 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) 7076 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2)); 7077 7078 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) 7079 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3)); 7080 7081 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) 7082 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4)); 7083 7084 else 7085 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5)); 7086 7087 case REAL_TYPE: 7088 /* If this is a range type, consider it to be the underlying 7089 type. */ 7090 if (TREE_TYPE (type) != 0) 7091 break; 7092 7093 /* Carefully distinguish all the standard types of C, 7094 without messing up if the language is not C. */ 7095 7096 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) 7097 return (qualifiers | 6); 7098 7099 else 7100 return (qualifiers | 7); 7101 7102 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ 7103 /* ??? We need to distinguish between double and float complex types, 7104 but I don't know how yet because I can't reach this code from 7105 existing front-ends. */ 7106 return (qualifiers | 7); /* Who knows? */ 7107 7108 case VECTOR_TYPE: 7109 case BOOLEAN_TYPE: /* Boolean truth value type. */ 7110 case LANG_TYPE: /* ? */ 7111 return qualifiers; 7112 7113 default: 7114 gcc_unreachable (); /* Not a type! */ 7115 } 7116 } 7117 7118 return qualifiers; 7119} 7120 7121/* Nested function support. */ 7122 7123/* Emit RTL insns to initialize the variable parts of a trampoline. 7124 FNADDR is an RTX for the address of the function's pure code. 7125 CXT is an RTX for the static chain value for the function. 7126 7127 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi 7128 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes 7129 (to store insns). This is a bit excessive. Perhaps a different 7130 mechanism would be better here. 7131 7132 Emit enough FLUSH insns to synchronize the data and instruction caches. */ 7133 7134void 7135sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) 7136{ 7137 /* SPARC 32-bit trampoline: 7138 7139 sethi %hi(fn), %g1 7140 sethi %hi(static), %g2 7141 jmp %g1+%lo(fn) 7142 or %g2, %lo(static), %g2 7143 7144 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii 7145 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii 7146 */ 7147 7148 emit_move_insn 7149 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)), 7150 expand_binop (SImode, ior_optab, 7151 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 7152 size_int (10), 0, 1), 7153 GEN_INT (trunc_int_for_mode (0x03000000, SImode)), 7154 NULL_RTX, 1, OPTAB_DIRECT)); 7155 7156 emit_move_insn 7157 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), 7158 expand_binop (SImode, ior_optab, 7159 expand_shift (RSHIFT_EXPR, SImode, cxt, 7160 size_int (10), 0, 1), 7161 GEN_INT (trunc_int_for_mode (0x05000000, SImode)), 7162 NULL_RTX, 1, OPTAB_DIRECT)); 7163 7164 emit_move_insn 7165 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), 7166 expand_binop (SImode, ior_optab, 7167 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), 7168 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), 7169 NULL_RTX, 1, OPTAB_DIRECT)); 7170 7171 emit_move_insn 7172 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), 7173 expand_binop (SImode, ior_optab, 7174 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), 7175 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), 7176 NULL_RTX, 1, OPTAB_DIRECT)); 7177 7178 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is 7179 aligned on a 16 byte boundary so one flush clears it all. */ 7180 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); 7181 if (sparc_cpu != PROCESSOR_ULTRASPARC 7182 && sparc_cpu != PROCESSOR_ULTRASPARC3 7183 && sparc_cpu != PROCESSOR_NIAGARA) 7184 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, 7185 plus_constant (tramp, 8))))); 7186 7187 /* Call __enable_execute_stack after writing onto the stack to make sure 7188 the stack address is accessible. */ 7189#ifdef ENABLE_EXECUTE_STACK 7190 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"), 7191 LCT_NORMAL, VOIDmode, 1, tramp, Pmode); 7192#endif 7193 7194} 7195 7196/* The 64-bit version is simpler because it makes more sense to load the 7197 values as "immediate" data out of the trampoline. It's also easier since 7198 we can read the PC without clobbering a register. */ 7199 7200void 7201sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) 7202{ 7203 /* SPARC 64-bit trampoline: 7204 7205 rd %pc, %g1 7206 ldx [%g1+24], %g5 7207 jmp %g5 7208 ldx [%g1+16], %g5 7209 +16 bytes data 7210 */ 7211 7212 emit_move_insn (gen_rtx_MEM (SImode, tramp), 7213 GEN_INT (trunc_int_for_mode (0x83414000, SImode))); 7214 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), 7215 GEN_INT (trunc_int_for_mode (0xca586018, SImode))); 7216 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), 7217 GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); 7218 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)), 7219 GEN_INT (trunc_int_for_mode (0xca586010, SImode))); 7220 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt); 7221 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); 7222 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); 7223 7224 if (sparc_cpu != PROCESSOR_ULTRASPARC 7225 && sparc_cpu != PROCESSOR_ULTRASPARC3 7226 && sparc_cpu != PROCESSOR_NIAGARA) 7227 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); 7228 7229 /* Call __enable_execute_stack after writing onto the stack to make sure 7230 the stack address is accessible. */ 7231#ifdef ENABLE_EXECUTE_STACK 7232 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"), 7233 LCT_NORMAL, VOIDmode, 1, tramp, Pmode); 7234#endif 7235} 7236 7237/* Adjust the cost of a scheduling dependency. Return the new cost of 7238 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ 7239 7240static int 7241supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) 7242{ 7243 enum attr_type insn_type; 7244 7245 if (! recog_memoized (insn)) 7246 return 0; 7247 7248 insn_type = get_attr_type (insn); 7249 7250 if (REG_NOTE_KIND (link) == 0) 7251 { 7252 /* Data dependency; DEP_INSN writes a register that INSN reads some 7253 cycles later. */ 7254 7255 /* if a load, then the dependence must be on the memory address; 7256 add an extra "cycle". Note that the cost could be two cycles 7257 if the reg was written late in an instruction group; we ca not tell 7258 here. */ 7259 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) 7260 return cost + 3; 7261 7262 /* Get the delay only if the address of the store is the dependence. */ 7263 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) 7264 { 7265 rtx pat = PATTERN(insn); 7266 rtx dep_pat = PATTERN (dep_insn); 7267 7268 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 7269 return cost; /* This should not happen! */ 7270 7271 /* The dependency between the two instructions was on the data that 7272 is being stored. Assume that this implies that the address of the 7273 store is not dependent. */ 7274 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 7275 return cost; 7276 7277 return cost + 3; /* An approximation. */ 7278 } 7279 7280 /* A shift instruction cannot receive its data from an instruction 7281 in the same cycle; add a one cycle penalty. */ 7282 if (insn_type == TYPE_SHIFT) 7283 return cost + 3; /* Split before cascade into shift. */ 7284 } 7285 else 7286 { 7287 /* Anti- or output- dependency; DEP_INSN reads/writes a register that 7288 INSN writes some cycles later. */ 7289 7290 /* These are only significant for the fpu unit; writing a fp reg before 7291 the fpu has finished with it stalls the processor. */ 7292 7293 /* Reusing an integer register causes no problems. */ 7294 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 7295 return 0; 7296 } 7297 7298 return cost; 7299} 7300 7301static int 7302hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) 7303{ 7304 enum attr_type insn_type, dep_type; 7305 rtx pat = PATTERN(insn); 7306 rtx dep_pat = PATTERN (dep_insn); 7307 7308 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) 7309 return cost; 7310 7311 insn_type = get_attr_type (insn); 7312 dep_type = get_attr_type (dep_insn); 7313 7314 switch (REG_NOTE_KIND (link)) 7315 { 7316 case 0: 7317 /* Data dependency; DEP_INSN writes a register that INSN reads some 7318 cycles later. */ 7319 7320 switch (insn_type) 7321 { 7322 case TYPE_STORE: 7323 case TYPE_FPSTORE: 7324 /* Get the delay iff the address of the store is the dependence. */ 7325 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 7326 return cost; 7327 7328 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 7329 return cost; 7330 return cost + 3; 7331 7332 case TYPE_LOAD: 7333 case TYPE_SLOAD: 7334 case TYPE_FPLOAD: 7335 /* If a load, then the dependence must be on the memory address. If 7336 the addresses aren't equal, then it might be a false dependency */ 7337 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) 7338 { 7339 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET 7340 || GET_CODE (SET_DEST (dep_pat)) != MEM 7341 || GET_CODE (SET_SRC (pat)) != MEM 7342 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), 7343 XEXP (SET_SRC (pat), 0))) 7344 return cost + 2; 7345 7346 return cost + 8; 7347 } 7348 break; 7349 7350 case TYPE_BRANCH: 7351 /* Compare to branch latency is 0. There is no benefit from 7352 separating compare and branch. */ 7353 if (dep_type == TYPE_COMPARE) 7354 return 0; 7355 /* Floating point compare to branch latency is less than 7356 compare to conditional move. */ 7357 if (dep_type == TYPE_FPCMP) 7358 return cost - 1; 7359 break; 7360 default: 7361 break; 7362 } 7363 break; 7364 7365 case REG_DEP_ANTI: 7366 /* Anti-dependencies only penalize the fpu unit. */ 7367 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 7368 return 0; 7369 break; 7370 7371 default: 7372 break; 7373 } 7374 7375 return cost; 7376} 7377 7378static int 7379sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost) 7380{ 7381 switch (sparc_cpu) 7382 { 7383 case PROCESSOR_SUPERSPARC: 7384 cost = supersparc_adjust_cost (insn, link, dep, cost); 7385 break; 7386 case PROCESSOR_HYPERSPARC: 7387 case PROCESSOR_SPARCLITE86X: 7388 cost = hypersparc_adjust_cost (insn, link, dep, cost); 7389 break; 7390 default: 7391 break; 7392 } 7393 return cost; 7394} 7395 7396static void 7397sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED, 7398 int sched_verbose ATTRIBUTE_UNUSED, 7399 int max_ready ATTRIBUTE_UNUSED) 7400{ 7401} 7402 7403static int 7404sparc_use_sched_lookahead (void) 7405{ 7406 if (sparc_cpu == PROCESSOR_NIAGARA) 7407 return 0; 7408 if (sparc_cpu == PROCESSOR_ULTRASPARC 7409 || sparc_cpu == PROCESSOR_ULTRASPARC3) 7410 return 4; 7411 if ((1 << sparc_cpu) & 7412 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | 7413 (1 << PROCESSOR_SPARCLITE86X))) 7414 return 3; 7415 return 0; 7416} 7417 7418static int 7419sparc_issue_rate (void) 7420{ 7421 switch (sparc_cpu) 7422 { 7423 case PROCESSOR_NIAGARA: 7424 default: 7425 return 1; 7426 case PROCESSOR_V9: 7427 /* Assume V9 processors are capable of at least dual-issue. */ 7428 return 2; 7429 case PROCESSOR_SUPERSPARC: 7430 return 3; 7431 case PROCESSOR_HYPERSPARC: 7432 case PROCESSOR_SPARCLITE86X: 7433 return 2; 7434 case PROCESSOR_ULTRASPARC: 7435 case PROCESSOR_ULTRASPARC3: 7436 return 4; 7437 } 7438} 7439 7440static int 7441set_extends (rtx insn) 7442{ 7443 register rtx pat = PATTERN (insn); 7444 7445 switch (GET_CODE (SET_SRC (pat))) 7446 { 7447 /* Load and some shift instructions zero extend. */ 7448 case MEM: 7449 case ZERO_EXTEND: 7450 /* sethi clears the high bits */ 7451 case HIGH: 7452 /* LO_SUM is used with sethi. sethi cleared the high 7453 bits and the values used with lo_sum are positive */ 7454 case LO_SUM: 7455 /* Store flag stores 0 or 1 */ 7456 case LT: case LTU: 7457 case GT: case GTU: 7458 case LE: case LEU: 7459 case GE: case GEU: 7460 case EQ: 7461 case NE: 7462 return 1; 7463 case AND: 7464 { 7465 rtx op0 = XEXP (SET_SRC (pat), 0); 7466 rtx op1 = XEXP (SET_SRC (pat), 1); 7467 if (GET_CODE (op1) == CONST_INT) 7468 return INTVAL (op1) >= 0; 7469 if (GET_CODE (op0) != REG) 7470 return 0; 7471 if (sparc_check_64 (op0, insn) == 1) 7472 return 1; 7473 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 7474 } 7475 case IOR: 7476 case XOR: 7477 { 7478 rtx op0 = XEXP (SET_SRC (pat), 0); 7479 rtx op1 = XEXP (SET_SRC (pat), 1); 7480 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) 7481 return 0; 7482 if (GET_CODE (op1) == CONST_INT) 7483 return INTVAL (op1) >= 0; 7484 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 7485 } 7486 case LSHIFTRT: 7487 return GET_MODE (SET_SRC (pat)) == SImode; 7488 /* Positive integers leave the high bits zero. */ 7489 case CONST_DOUBLE: 7490 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000); 7491 case CONST_INT: 7492 return ! (INTVAL (SET_SRC (pat)) & 0x80000000); 7493 case ASHIFTRT: 7494 case SIGN_EXTEND: 7495 return - (GET_MODE (SET_SRC (pat)) == SImode); 7496 case REG: 7497 return sparc_check_64 (SET_SRC (pat), insn); 7498 default: 7499 return 0; 7500 } 7501} 7502 7503/* We _ought_ to have only one kind per function, but... */ 7504static GTY(()) rtx sparc_addr_diff_list; 7505static GTY(()) rtx sparc_addr_list; 7506 7507void 7508sparc_defer_case_vector (rtx lab, rtx vec, int diff) 7509{ 7510 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); 7511 if (diff) 7512 sparc_addr_diff_list 7513 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); 7514 else 7515 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); 7516} 7517 7518static void 7519sparc_output_addr_vec (rtx vec) 7520{ 7521 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 7522 int idx, vlen = XVECLEN (body, 0); 7523 7524#ifdef ASM_OUTPUT_ADDR_VEC_START 7525 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 7526#endif 7527 7528#ifdef ASM_OUTPUT_CASE_LABEL 7529 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 7530 NEXT_INSN (lab)); 7531#else 7532 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 7533#endif 7534 7535 for (idx = 0; idx < vlen; idx++) 7536 { 7537 ASM_OUTPUT_ADDR_VEC_ELT 7538 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); 7539 } 7540 7541#ifdef ASM_OUTPUT_ADDR_VEC_END 7542 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 7543#endif 7544} 7545 7546static void 7547sparc_output_addr_diff_vec (rtx vec) 7548{ 7549 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 7550 rtx base = XEXP (XEXP (body, 0), 0); 7551 int idx, vlen = XVECLEN (body, 1); 7552 7553#ifdef ASM_OUTPUT_ADDR_VEC_START 7554 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 7555#endif 7556 7557#ifdef ASM_OUTPUT_CASE_LABEL 7558 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 7559 NEXT_INSN (lab)); 7560#else 7561 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 7562#endif 7563 7564 for (idx = 0; idx < vlen; idx++) 7565 { 7566 ASM_OUTPUT_ADDR_DIFF_ELT 7567 (asm_out_file, 7568 body, 7569 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), 7570 CODE_LABEL_NUMBER (base)); 7571 } 7572 7573#ifdef ASM_OUTPUT_ADDR_VEC_END 7574 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 7575#endif 7576} 7577 7578static void 7579sparc_output_deferred_case_vectors (void) 7580{ 7581 rtx t; 7582 int align; 7583 7584 if (sparc_addr_list == NULL_RTX 7585 && sparc_addr_diff_list == NULL_RTX) 7586 return; 7587 7588 /* Align to cache line in the function's code section. */ 7589 switch_to_section (current_function_section ()); 7590 7591 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 7592 if (align > 0) 7593 ASM_OUTPUT_ALIGN (asm_out_file, align); 7594 7595 for (t = sparc_addr_list; t ; t = XEXP (t, 1)) 7596 sparc_output_addr_vec (XEXP (t, 0)); 7597 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) 7598 sparc_output_addr_diff_vec (XEXP (t, 0)); 7599 7600 sparc_addr_list = sparc_addr_diff_list = NULL_RTX; 7601} 7602 7603/* Return 0 if the high 32 bits of X (the low word of X, if DImode) are 7604 unknown. Return 1 if the high bits are zero, -1 if the register is 7605 sign extended. */ 7606int 7607sparc_check_64 (rtx x, rtx insn) 7608{ 7609 /* If a register is set only once it is safe to ignore insns this 7610 code does not know how to handle. The loop will either recognize 7611 the single set and return the correct value or fail to recognize 7612 it and return 0. */ 7613 int set_once = 0; 7614 rtx y = x; 7615 7616 gcc_assert (GET_CODE (x) == REG); 7617 7618 if (GET_MODE (x) == DImode) 7619 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); 7620 7621 if (flag_expensive_optimizations 7622 && REG_N_SETS (REGNO (y)) == 1) 7623 set_once = 1; 7624 7625 if (insn == 0) 7626 { 7627 if (set_once) 7628 insn = get_last_insn_anywhere (); 7629 else 7630 return 0; 7631 } 7632 7633 while ((insn = PREV_INSN (insn))) 7634 { 7635 switch (GET_CODE (insn)) 7636 { 7637 case JUMP_INSN: 7638 case NOTE: 7639 break; 7640 case CODE_LABEL: 7641 case CALL_INSN: 7642 default: 7643 if (! set_once) 7644 return 0; 7645 break; 7646 case INSN: 7647 { 7648 rtx pat = PATTERN (insn); 7649 if (GET_CODE (pat) != SET) 7650 return 0; 7651 if (rtx_equal_p (x, SET_DEST (pat))) 7652 return set_extends (insn); 7653 if (y && rtx_equal_p (y, SET_DEST (pat))) 7654 return set_extends (insn); 7655 if (reg_overlap_mentioned_p (SET_DEST (pat), y)) 7656 return 0; 7657 } 7658 } 7659 } 7660 return 0; 7661} 7662 7663/* Returns assembly code to perform a DImode shift using 7664 a 64-bit global or out register on SPARC-V8+. */ 7665const char * 7666output_v8plus_shift (rtx *operands, rtx insn, const char *opcode) 7667{ 7668 static char asm_code[60]; 7669 7670 /* The scratch register is only required when the destination 7671 register is not a 64-bit global or out register. */ 7672 if (which_alternative != 2) 7673 operands[3] = operands[0]; 7674 7675 /* We can only shift by constants <= 63. */ 7676 if (GET_CODE (operands[2]) == CONST_INT) 7677 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 7678 7679 if (GET_CODE (operands[1]) == CONST_INT) 7680 { 7681 output_asm_insn ("mov\t%1, %3", operands); 7682 } 7683 else 7684 { 7685 output_asm_insn ("sllx\t%H1, 32, %3", operands); 7686 if (sparc_check_64 (operands[1], insn) <= 0) 7687 output_asm_insn ("srl\t%L1, 0, %L1", operands); 7688 output_asm_insn ("or\t%L1, %3, %3", operands); 7689 } 7690 7691 strcpy(asm_code, opcode); 7692 7693 if (which_alternative != 2) 7694 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); 7695 else 7696 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); 7697} 7698 7699/* Output rtl to increment the profiler label LABELNO 7700 for profiling a function entry. */ 7701 7702void 7703sparc_profile_hook (int labelno) 7704{ 7705 char buf[32]; 7706 rtx lab, fun; 7707 7708 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); 7709 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 7710 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); 7711 7712 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); 7713} 7714 7715#ifdef OBJECT_FORMAT_ELF 7716static void 7717sparc_elf_asm_named_section (const char *name, unsigned int flags, 7718 tree decl) 7719{ 7720 if (flags & SECTION_MERGE) 7721 { 7722 /* entsize cannot be expressed in this section attributes 7723 encoding style. */ 7724 default_elf_asm_named_section (name, flags, decl); 7725 return; 7726 } 7727 7728 fprintf (asm_out_file, "\t.section\t\"%s\"", name); 7729 7730 if (!(flags & SECTION_DEBUG)) 7731 fputs (",#alloc", asm_out_file); 7732 if (flags & SECTION_WRITE) 7733 fputs (",#write", asm_out_file); 7734 if (flags & SECTION_TLS) 7735 fputs (",#tls", asm_out_file); 7736 if (flags & SECTION_CODE) 7737 fputs (",#execinstr", asm_out_file); 7738 7739 /* ??? Handle SECTION_BSS. */ 7740 7741 fputc ('\n', asm_out_file); 7742} 7743#endif /* OBJECT_FORMAT_ELF */ 7744 7745/* We do not allow indirect calls to be optimized into sibling calls. 7746 7747 We cannot use sibling calls when delayed branches are disabled 7748 because they will likely require the call delay slot to be filled. 7749 7750 Also, on SPARC 32-bit we cannot emit a sibling call when the 7751 current function returns a structure. This is because the "unimp 7752 after call" convention would cause the callee to return to the 7753 wrong place. The generic code already disallows cases where the 7754 function being called returns a structure. 7755 7756 It may seem strange how this last case could occur. Usually there 7757 is code after the call which jumps to epilogue code which dumps the 7758 return value into the struct return area. That ought to invalidate 7759 the sibling call right? Well, in the C++ case we can end up passing 7760 the pointer to the struct return area to a constructor (which returns 7761 void) and then nothing else happens. Such a sibling call would look 7762 valid without the added check here. */ 7763static bool 7764sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) 7765{ 7766 return (decl 7767 && flag_delayed_branch 7768 && (TARGET_ARCH64 || ! current_function_returns_struct)); 7769} 7770 7771/* libfunc renaming. */ 7772#include "config/gofast.h" 7773 7774static void 7775sparc_init_libfuncs (void) 7776{ 7777 if (TARGET_ARCH32) 7778 { 7779 /* Use the subroutines that Sun's library provides for integer 7780 multiply and divide. The `*' prevents an underscore from 7781 being prepended by the compiler. .umul is a little faster 7782 than .mul. */ 7783 set_optab_libfunc (smul_optab, SImode, "*.umul"); 7784 set_optab_libfunc (sdiv_optab, SImode, "*.div"); 7785 set_optab_libfunc (udiv_optab, SImode, "*.udiv"); 7786 set_optab_libfunc (smod_optab, SImode, "*.rem"); 7787 set_optab_libfunc (umod_optab, SImode, "*.urem"); 7788 7789 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */ 7790 set_optab_libfunc (add_optab, TFmode, "_Q_add"); 7791 set_optab_libfunc (sub_optab, TFmode, "_Q_sub"); 7792 set_optab_libfunc (neg_optab, TFmode, "_Q_neg"); 7793 set_optab_libfunc (smul_optab, TFmode, "_Q_mul"); 7794 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div"); 7795 7796 /* We can define the TFmode sqrt optab only if TARGET_FPU. This 7797 is because with soft-float, the SFmode and DFmode sqrt 7798 instructions will be absent, and the compiler will notice and 7799 try to use the TFmode sqrt instruction for calls to the 7800 builtin function sqrt, but this fails. */ 7801 if (TARGET_FPU) 7802 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt"); 7803 7804 set_optab_libfunc (eq_optab, TFmode, "_Q_feq"); 7805 set_optab_libfunc (ne_optab, TFmode, "_Q_fne"); 7806 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt"); 7807 set_optab_libfunc (ge_optab, TFmode, "_Q_fge"); 7808 set_optab_libfunc (lt_optab, TFmode, "_Q_flt"); 7809 set_optab_libfunc (le_optab, TFmode, "_Q_fle"); 7810 7811 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq"); 7812 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq"); 7813 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos"); 7814 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod"); 7815 7816 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi"); 7817 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou"); 7818 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq"); 7819 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq"); 7820 7821 if (DITF_CONVERSION_LIBFUNCS) 7822 { 7823 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll"); 7824 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull"); 7825 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq"); 7826 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq"); 7827 } 7828 7829 if (SUN_CONVERSION_LIBFUNCS) 7830 { 7831 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); 7832 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); 7833 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); 7834 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); 7835 } 7836 } 7837 if (TARGET_ARCH64) 7838 { 7839 /* In the SPARC 64bit ABI, SImode multiply and divide functions 7840 do not exist in the library. Make sure the compiler does not 7841 emit calls to them by accident. (It should always use the 7842 hardware instructions.) */ 7843 set_optab_libfunc (smul_optab, SImode, 0); 7844 set_optab_libfunc (sdiv_optab, SImode, 0); 7845 set_optab_libfunc (udiv_optab, SImode, 0); 7846 set_optab_libfunc (smod_optab, SImode, 0); 7847 set_optab_libfunc (umod_optab, SImode, 0); 7848 7849 if (SUN_INTEGER_MULTIPLY_64) 7850 { 7851 set_optab_libfunc (smul_optab, DImode, "__mul64"); 7852 set_optab_libfunc (sdiv_optab, DImode, "__div64"); 7853 set_optab_libfunc (udiv_optab, DImode, "__udiv64"); 7854 set_optab_libfunc (smod_optab, DImode, "__rem64"); 7855 set_optab_libfunc (umod_optab, DImode, "__urem64"); 7856 } 7857 7858 if (SUN_CONVERSION_LIBFUNCS) 7859 { 7860 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol"); 7861 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul"); 7862 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol"); 7863 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul"); 7864 } 7865 } 7866 7867 gofast_maybe_init_libfuncs (); 7868} 7869 7870#define def_builtin(NAME, CODE, TYPE) \ 7871 lang_hooks.builtin_function((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, \ 7872 NULL_TREE) 7873 7874/* Implement the TARGET_INIT_BUILTINS target hook. 7875 Create builtin functions for special SPARC instructions. */ 7876 7877static void 7878sparc_init_builtins (void) 7879{ 7880 if (TARGET_VIS) 7881 sparc_vis_init_builtins (); 7882} 7883 7884/* Create builtin functions for VIS 1.0 instructions. */ 7885 7886static void 7887sparc_vis_init_builtins (void) 7888{ 7889 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4); 7890 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8); 7891 tree v4hi = build_vector_type (intHI_type_node, 4); 7892 tree v2hi = build_vector_type (intHI_type_node, 2); 7893 tree v2si = build_vector_type (intSI_type_node, 2); 7894 7895 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0); 7896 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0); 7897 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0); 7898 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0); 7899 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0); 7900 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0); 7901 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0); 7902 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0); 7903 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0); 7904 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0); 7905 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0); 7906 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0); 7907 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node, 7908 v8qi, v8qi, 7909 intDI_type_node, 0); 7910 tree di_ftype_di_di = build_function_type_list (intDI_type_node, 7911 intDI_type_node, 7912 intDI_type_node, 0); 7913 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node, 7914 ptr_type_node, 7915 intSI_type_node, 0); 7916 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node, 7917 ptr_type_node, 7918 intDI_type_node, 0); 7919 7920 /* Packing and expanding vectors. */ 7921 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, v4qi_ftype_v4hi); 7922 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis, 7923 v8qi_ftype_v2si_v8qi); 7924 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis, 7925 v2hi_ftype_v2si); 7926 def_builtin ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis, v4hi_ftype_v4qi); 7927 def_builtin ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis, 7928 v8qi_ftype_v4qi_v4qi); 7929 7930 /* Multiplications. */ 7931 def_builtin ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis, 7932 v4hi_ftype_v4qi_v4hi); 7933 def_builtin ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis, 7934 v4hi_ftype_v4qi_v2hi); 7935 def_builtin ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis, 7936 v4hi_ftype_v4qi_v2hi); 7937 def_builtin ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis, 7938 v4hi_ftype_v8qi_v4hi); 7939 def_builtin ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis, 7940 v4hi_ftype_v8qi_v4hi); 7941 def_builtin ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis, 7942 v2si_ftype_v4qi_v2hi); 7943 def_builtin ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis, 7944 v2si_ftype_v4qi_v2hi); 7945 7946 /* Data aligning. */ 7947 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis, 7948 v4hi_ftype_v4hi_v4hi); 7949 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis, 7950 v8qi_ftype_v8qi_v8qi); 7951 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis, 7952 v2si_ftype_v2si_v2si); 7953 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatadi_vis, 7954 di_ftype_di_di); 7955 if (TARGET_ARCH64) 7956 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis, 7957 ptr_ftype_ptr_di); 7958 else 7959 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis, 7960 ptr_ftype_ptr_si); 7961 7962 /* Pixel distance. */ 7963 def_builtin ("__builtin_vis_pdist", CODE_FOR_pdist_vis, 7964 di_ftype_v8qi_v8qi_di); 7965} 7966 7967/* Handle TARGET_EXPAND_BUILTIN target hook. 7968 Expand builtin functions for sparc intrinsics. */ 7969 7970static rtx 7971sparc_expand_builtin (tree exp, rtx target, 7972 rtx subtarget ATTRIBUTE_UNUSED, 7973 enum machine_mode tmode ATTRIBUTE_UNUSED, 7974 int ignore ATTRIBUTE_UNUSED) 7975{ 7976 tree arglist; 7977 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); 7978 unsigned int icode = DECL_FUNCTION_CODE (fndecl); 7979 rtx pat, op[4]; 7980 enum machine_mode mode[4]; 7981 int arg_count = 0; 7982 7983 mode[0] = insn_data[icode].operand[0].mode; 7984 if (!target 7985 || GET_MODE (target) != mode[0] 7986 || ! (*insn_data[icode].operand[0].predicate) (target, mode[0])) 7987 op[0] = gen_reg_rtx (mode[0]); 7988 else 7989 op[0] = target; 7990 7991 for (arglist = TREE_OPERAND (exp, 1); arglist; 7992 arglist = TREE_CHAIN (arglist)) 7993 { 7994 tree arg = TREE_VALUE (arglist); 7995 7996 arg_count++; 7997 mode[arg_count] = insn_data[icode].operand[arg_count].mode; 7998 op[arg_count] = expand_normal (arg); 7999 8000 if (! (*insn_data[icode].operand[arg_count].predicate) (op[arg_count], 8001 mode[arg_count])) 8002 op[arg_count] = copy_to_mode_reg (mode[arg_count], op[arg_count]); 8003 } 8004 8005 switch (arg_count) 8006 { 8007 case 1: 8008 pat = GEN_FCN (icode) (op[0], op[1]); 8009 break; 8010 case 2: 8011 pat = GEN_FCN (icode) (op[0], op[1], op[2]); 8012 break; 8013 case 3: 8014 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); 8015 break; 8016 default: 8017 gcc_unreachable (); 8018 } 8019 8020 if (!pat) 8021 return NULL_RTX; 8022 8023 emit_insn (pat); 8024 8025 return op[0]; 8026} 8027 8028static int 8029sparc_vis_mul8x16 (int e8, int e16) 8030{ 8031 return (e8 * e16 + 128) / 256; 8032} 8033 8034/* Multiply the vector elements in ELTS0 to the elements in ELTS1 as specified 8035 by FNCODE. All of the elements in ELTS0 and ELTS1 lists must be integer 8036 constants. A tree list with the results of the multiplications is returned, 8037 and each element in the list is of INNER_TYPE. */ 8038 8039static tree 8040sparc_handle_vis_mul8x16 (int fncode, tree inner_type, tree elts0, tree elts1) 8041{ 8042 tree n_elts = NULL_TREE; 8043 int scale; 8044 8045 switch (fncode) 8046 { 8047 case CODE_FOR_fmul8x16_vis: 8048 for (; elts0 && elts1; 8049 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1)) 8050 { 8051 int val 8052 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)), 8053 TREE_INT_CST_LOW (TREE_VALUE (elts1))); 8054 n_elts = tree_cons (NULL_TREE, 8055 build_int_cst (inner_type, val), 8056 n_elts); 8057 } 8058 break; 8059 8060 case CODE_FOR_fmul8x16au_vis: 8061 scale = TREE_INT_CST_LOW (TREE_VALUE (elts1)); 8062 8063 for (; elts0; elts0 = TREE_CHAIN (elts0)) 8064 { 8065 int val 8066 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)), 8067 scale); 8068 n_elts = tree_cons (NULL_TREE, 8069 build_int_cst (inner_type, val), 8070 n_elts); 8071 } 8072 break; 8073 8074 case CODE_FOR_fmul8x16al_vis: 8075 scale = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (elts1))); 8076 8077 for (; elts0; elts0 = TREE_CHAIN (elts0)) 8078 { 8079 int val 8080 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (TREE_VALUE (elts0)), 8081 scale); 8082 n_elts = tree_cons (NULL_TREE, 8083 build_int_cst (inner_type, val), 8084 n_elts); 8085 } 8086 break; 8087 8088 default: 8089 gcc_unreachable (); 8090 } 8091 8092 return nreverse (n_elts); 8093 8094} 8095/* Handle TARGET_FOLD_BUILTIN target hook. 8096 Fold builtin functions for SPARC intrinsics. If IGNORE is true the 8097 result of the function call is ignored. NULL_TREE is returned if the 8098 function could not be folded. */ 8099 8100static tree 8101sparc_fold_builtin (tree fndecl, tree arglist, bool ignore) 8102{ 8103 tree arg0, arg1, arg2; 8104 tree rtype = TREE_TYPE (TREE_TYPE (fndecl)); 8105 8106 if (ignore 8107 && DECL_FUNCTION_CODE (fndecl) != CODE_FOR_alignaddrsi_vis 8108 && DECL_FUNCTION_CODE (fndecl) != CODE_FOR_alignaddrdi_vis) 8109 return fold_convert (rtype, integer_zero_node); 8110 8111 switch (DECL_FUNCTION_CODE (fndecl)) 8112 { 8113 case CODE_FOR_fexpand_vis: 8114 arg0 = TREE_VALUE (arglist); 8115 STRIP_NOPS (arg0); 8116 8117 if (TREE_CODE (arg0) == VECTOR_CST) 8118 { 8119 tree inner_type = TREE_TYPE (rtype); 8120 tree elts = TREE_VECTOR_CST_ELTS (arg0); 8121 tree n_elts = NULL_TREE; 8122 8123 for (; elts; elts = TREE_CHAIN (elts)) 8124 { 8125 unsigned int val = TREE_INT_CST_LOW (TREE_VALUE (elts)) << 4; 8126 n_elts = tree_cons (NULL_TREE, 8127 build_int_cst (inner_type, val), 8128 n_elts); 8129 } 8130 return build_vector (rtype, nreverse (n_elts)); 8131 } 8132 break; 8133 8134 case CODE_FOR_fmul8x16_vis: 8135 case CODE_FOR_fmul8x16au_vis: 8136 case CODE_FOR_fmul8x16al_vis: 8137 arg0 = TREE_VALUE (arglist); 8138 arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 8139 STRIP_NOPS (arg0); 8140 STRIP_NOPS (arg1); 8141 8142 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST) 8143 { 8144 tree inner_type = TREE_TYPE (rtype); 8145 tree elts0 = TREE_VECTOR_CST_ELTS (arg0); 8146 tree elts1 = TREE_VECTOR_CST_ELTS (arg1); 8147 tree n_elts = sparc_handle_vis_mul8x16 (DECL_FUNCTION_CODE (fndecl), 8148 inner_type, elts0, elts1); 8149 8150 return build_vector (rtype, n_elts); 8151 } 8152 break; 8153 8154 case CODE_FOR_fpmerge_vis: 8155 arg0 = TREE_VALUE (arglist); 8156 arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 8157 STRIP_NOPS (arg0); 8158 STRIP_NOPS (arg1); 8159 8160 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST) 8161 { 8162 tree elts0 = TREE_VECTOR_CST_ELTS (arg0); 8163 tree elts1 = TREE_VECTOR_CST_ELTS (arg1); 8164 tree n_elts = NULL_TREE; 8165 8166 for (; elts0 && elts1; 8167 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1)) 8168 { 8169 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts0), n_elts); 8170 n_elts = tree_cons (NULL_TREE, TREE_VALUE (elts1), n_elts); 8171 } 8172 8173 return build_vector (rtype, nreverse (n_elts)); 8174 } 8175 break; 8176 8177 case CODE_FOR_pdist_vis: 8178 arg0 = TREE_VALUE (arglist); 8179 arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 8180 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); 8181 STRIP_NOPS (arg0); 8182 STRIP_NOPS (arg1); 8183 STRIP_NOPS (arg2); 8184 8185 if (TREE_CODE (arg0) == VECTOR_CST 8186 && TREE_CODE (arg1) == VECTOR_CST 8187 && TREE_CODE (arg2) == INTEGER_CST) 8188 { 8189 int overflow = 0; 8190 unsigned HOST_WIDE_INT low = TREE_INT_CST_LOW (arg2); 8191 HOST_WIDE_INT high = TREE_INT_CST_HIGH (arg2); 8192 tree elts0 = TREE_VECTOR_CST_ELTS (arg0); 8193 tree elts1 = TREE_VECTOR_CST_ELTS (arg1); 8194 8195 for (; elts0 && elts1; 8196 elts0 = TREE_CHAIN (elts0), elts1 = TREE_CHAIN (elts1)) 8197 { 8198 unsigned HOST_WIDE_INT 8199 low0 = TREE_INT_CST_LOW (TREE_VALUE (elts0)), 8200 low1 = TREE_INT_CST_LOW (TREE_VALUE (elts1)); 8201 HOST_WIDE_INT high0 = TREE_INT_CST_HIGH (TREE_VALUE (elts0)); 8202 HOST_WIDE_INT high1 = TREE_INT_CST_HIGH (TREE_VALUE (elts1)); 8203 8204 unsigned HOST_WIDE_INT l; 8205 HOST_WIDE_INT h; 8206 8207 overflow |= neg_double (low1, high1, &l, &h); 8208 overflow |= add_double (low0, high0, l, h, &l, &h); 8209 if (h < 0) 8210 overflow |= neg_double (l, h, &l, &h); 8211 8212 overflow |= add_double (low, high, l, h, &low, &high); 8213 } 8214 8215 gcc_assert (overflow == 0); 8216 8217 return build_int_cst_wide (rtype, low, high); 8218 } 8219 8220 default: 8221 break; 8222 } 8223 8224 return NULL_TREE; 8225} 8226 8227int 8228sparc_extra_constraint_check (rtx op, int c, int strict) 8229{ 8230 int reload_ok_mem; 8231 8232 if (TARGET_ARCH64 8233 && (c == 'T' || c == 'U')) 8234 return 0; 8235 8236 switch (c) 8237 { 8238 case 'Q': 8239 return fp_sethi_p (op); 8240 8241 case 'R': 8242 return fp_mov_p (op); 8243 8244 case 'S': 8245 return fp_high_losum_p (op); 8246 8247 case 'U': 8248 if (! strict 8249 || (GET_CODE (op) == REG 8250 && (REGNO (op) < FIRST_PSEUDO_REGISTER 8251 || reg_renumber[REGNO (op)] >= 0))) 8252 return register_ok_for_ldd (op); 8253 8254 return 0; 8255 8256 case 'W': 8257 case 'T': 8258 break; 8259 8260 case 'Y': 8261 return const_zero_operand (op, GET_MODE (op)); 8262 8263 default: 8264 return 0; 8265 } 8266 8267 /* Our memory extra constraints have to emulate the 8268 behavior of 'm' and 'o' in order for reload to work 8269 correctly. */ 8270 if (GET_CODE (op) == MEM) 8271 { 8272 reload_ok_mem = 0; 8273 if ((TARGET_ARCH64 || mem_min_alignment (op, 8)) 8274 && (! strict 8275 || strict_memory_address_p (Pmode, XEXP (op, 0)))) 8276 reload_ok_mem = 1; 8277 } 8278 else 8279 { 8280 reload_ok_mem = (reload_in_progress 8281 && GET_CODE (op) == REG 8282 && REGNO (op) >= FIRST_PSEUDO_REGISTER 8283 && reg_renumber [REGNO (op)] < 0); 8284 } 8285 8286 return reload_ok_mem; 8287} 8288 8289/* ??? This duplicates information provided to the compiler by the 8290 ??? scheduler description. Some day, teach genautomata to output 8291 ??? the latencies and then CSE will just use that. */ 8292 8293static bool 8294sparc_rtx_costs (rtx x, int code, int outer_code, int *total) 8295{ 8296 enum machine_mode mode = GET_MODE (x); 8297 bool float_mode_p = FLOAT_MODE_P (mode); 8298 8299 switch (code) 8300 { 8301 case CONST_INT: 8302 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000) 8303 { 8304 *total = 0; 8305 return true; 8306 } 8307 /* FALLTHRU */ 8308 8309 case HIGH: 8310 *total = 2; 8311 return true; 8312 8313 case CONST: 8314 case LABEL_REF: 8315 case SYMBOL_REF: 8316 *total = 4; 8317 return true; 8318 8319 case CONST_DOUBLE: 8320 if (GET_MODE (x) == VOIDmode 8321 && ((CONST_DOUBLE_HIGH (x) == 0 8322 && CONST_DOUBLE_LOW (x) < 0x1000) 8323 || (CONST_DOUBLE_HIGH (x) == -1 8324 && CONST_DOUBLE_LOW (x) < 0 8325 && CONST_DOUBLE_LOW (x) >= -0x1000))) 8326 *total = 0; 8327 else 8328 *total = 8; 8329 return true; 8330 8331 case MEM: 8332 /* If outer-code was a sign or zero extension, a cost 8333 of COSTS_N_INSNS (1) was already added in. This is 8334 why we are subtracting it back out. */ 8335 if (outer_code == ZERO_EXTEND) 8336 { 8337 *total = sparc_costs->int_zload - COSTS_N_INSNS (1); 8338 } 8339 else if (outer_code == SIGN_EXTEND) 8340 { 8341 *total = sparc_costs->int_sload - COSTS_N_INSNS (1); 8342 } 8343 else if (float_mode_p) 8344 { 8345 *total = sparc_costs->float_load; 8346 } 8347 else 8348 { 8349 *total = sparc_costs->int_load; 8350 } 8351 8352 return true; 8353 8354 case PLUS: 8355 case MINUS: 8356 if (float_mode_p) 8357 *total = sparc_costs->float_plusminus; 8358 else 8359 *total = COSTS_N_INSNS (1); 8360 return false; 8361 8362 case MULT: 8363 if (float_mode_p) 8364 *total = sparc_costs->float_mul; 8365 else if (! TARGET_HARD_MUL) 8366 *total = COSTS_N_INSNS (25); 8367 else 8368 { 8369 int bit_cost; 8370 8371 bit_cost = 0; 8372 if (sparc_costs->int_mul_bit_factor) 8373 { 8374 int nbits; 8375 8376 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 8377 { 8378 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1)); 8379 for (nbits = 0; value != 0; value &= value - 1) 8380 nbits++; 8381 } 8382 else if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE 8383 && GET_MODE (XEXP (x, 1)) == VOIDmode) 8384 { 8385 rtx x1 = XEXP (x, 1); 8386 unsigned HOST_WIDE_INT value1 = CONST_DOUBLE_LOW (x1); 8387 unsigned HOST_WIDE_INT value2 = CONST_DOUBLE_HIGH (x1); 8388 8389 for (nbits = 0; value1 != 0; value1 &= value1 - 1) 8390 nbits++; 8391 for (; value2 != 0; value2 &= value2 - 1) 8392 nbits++; 8393 } 8394 else 8395 nbits = 7; 8396 8397 if (nbits < 3) 8398 nbits = 3; 8399 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor; 8400 bit_cost = COSTS_N_INSNS (bit_cost); 8401 } 8402 8403 if (mode == DImode) 8404 *total = sparc_costs->int_mulX + bit_cost; 8405 else 8406 *total = sparc_costs->int_mul + bit_cost; 8407 } 8408 return false; 8409 8410 case ASHIFT: 8411 case ASHIFTRT: 8412 case LSHIFTRT: 8413 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty; 8414 return false; 8415 8416 case DIV: 8417 case UDIV: 8418 case MOD: 8419 case UMOD: 8420 if (float_mode_p) 8421 { 8422 if (mode == DFmode) 8423 *total = sparc_costs->float_div_df; 8424 else 8425 *total = sparc_costs->float_div_sf; 8426 } 8427 else 8428 { 8429 if (mode == DImode) 8430 *total = sparc_costs->int_divX; 8431 else 8432 *total = sparc_costs->int_div; 8433 } 8434 return false; 8435 8436 case NEG: 8437 if (! float_mode_p) 8438 { 8439 *total = COSTS_N_INSNS (1); 8440 return false; 8441 } 8442 /* FALLTHRU */ 8443 8444 case ABS: 8445 case FLOAT: 8446 case UNSIGNED_FLOAT: 8447 case FIX: 8448 case UNSIGNED_FIX: 8449 case FLOAT_EXTEND: 8450 case FLOAT_TRUNCATE: 8451 *total = sparc_costs->float_move; 8452 return false; 8453 8454 case SQRT: 8455 if (mode == DFmode) 8456 *total = sparc_costs->float_sqrt_df; 8457 else 8458 *total = sparc_costs->float_sqrt_sf; 8459 return false; 8460 8461 case COMPARE: 8462 if (float_mode_p) 8463 *total = sparc_costs->float_cmp; 8464 else 8465 *total = COSTS_N_INSNS (1); 8466 return false; 8467 8468 case IF_THEN_ELSE: 8469 if (float_mode_p) 8470 *total = sparc_costs->float_cmove; 8471 else 8472 *total = sparc_costs->int_cmove; 8473 return false; 8474 8475 case IOR: 8476 /* Handle the NAND vector patterns. */ 8477 if (sparc_vector_mode_supported_p (GET_MODE (x)) 8478 && GET_CODE (XEXP (x, 0)) == NOT 8479 && GET_CODE (XEXP (x, 1)) == NOT) 8480 { 8481 *total = COSTS_N_INSNS (1); 8482 return true; 8483 } 8484 else 8485 return false; 8486 8487 default: 8488 return false; 8489 } 8490} 8491 8492/* Emit the sequence of insns SEQ while preserving the registers REG and REG2. 8493 This is achieved by means of a manual dynamic stack space allocation in 8494 the current frame. We make the assumption that SEQ doesn't contain any 8495 function calls, with the possible exception of calls to the PIC helper. */ 8496 8497static void 8498emit_and_preserve (rtx seq, rtx reg, rtx reg2) 8499{ 8500 /* We must preserve the lowest 16 words for the register save area. */ 8501 HOST_WIDE_INT offset = 16*UNITS_PER_WORD; 8502 /* We really need only 2 words of fresh stack space. */ 8503 HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD); 8504 8505 rtx slot 8506 = gen_rtx_MEM (word_mode, plus_constant (stack_pointer_rtx, 8507 SPARC_STACK_BIAS + offset)); 8508 8509 emit_insn (gen_stack_pointer_dec (GEN_INT (size))); 8510 emit_insn (gen_rtx_SET (VOIDmode, slot, reg)); 8511 if (reg2) 8512 emit_insn (gen_rtx_SET (VOIDmode, 8513 adjust_address (slot, word_mode, UNITS_PER_WORD), 8514 reg2)); 8515 emit_insn (seq); 8516 if (reg2) 8517 emit_insn (gen_rtx_SET (VOIDmode, 8518 reg2, 8519 adjust_address (slot, word_mode, UNITS_PER_WORD))); 8520 emit_insn (gen_rtx_SET (VOIDmode, reg, slot)); 8521 emit_insn (gen_stack_pointer_inc (GEN_INT (size))); 8522} 8523 8524/* Output the assembler code for a thunk function. THUNK_DECL is the 8525 declaration for the thunk function itself, FUNCTION is the decl for 8526 the target function. DELTA is an immediate constant offset to be 8527 added to THIS. If VCALL_OFFSET is nonzero, the word at address 8528 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */ 8529 8530static void 8531sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 8532 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 8533 tree function) 8534{ 8535 rtx this, insn, funexp; 8536 unsigned int int_arg_first; 8537 8538 reload_completed = 1; 8539 epilogue_completed = 1; 8540 no_new_pseudos = 1; 8541 reset_block_changes (); 8542 8543 emit_note (NOTE_INSN_PROLOGUE_END); 8544 8545 if (flag_delayed_branch) 8546 { 8547 /* We will emit a regular sibcall below, so we need to instruct 8548 output_sibcall that we are in a leaf function. */ 8549 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 1; 8550 8551 /* This will cause final.c to invoke leaf_renumber_regs so we 8552 must behave as if we were in a not-yet-leafified function. */ 8553 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST; 8554 } 8555 else 8556 { 8557 /* We will emit the sibcall manually below, so we will need to 8558 manually spill non-leaf registers. */ 8559 sparc_leaf_function_p = current_function_uses_only_leaf_regs = 0; 8560 8561 /* We really are in a leaf function. */ 8562 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST; 8563 } 8564 8565 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function 8566 returns a structure, the structure return pointer is there instead. */ 8567 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 8568 this = gen_rtx_REG (Pmode, int_arg_first + 1); 8569 else 8570 this = gen_rtx_REG (Pmode, int_arg_first); 8571 8572 /* Add DELTA. When possible use a plain add, otherwise load it into 8573 a register first. */ 8574 if (delta) 8575 { 8576 rtx delta_rtx = GEN_INT (delta); 8577 8578 if (! SPARC_SIMM13_P (delta)) 8579 { 8580 rtx scratch = gen_rtx_REG (Pmode, 1); 8581 emit_move_insn (scratch, delta_rtx); 8582 delta_rtx = scratch; 8583 } 8584 8585 /* THIS += DELTA. */ 8586 emit_insn (gen_add2_insn (this, delta_rtx)); 8587 } 8588 8589 /* Add the word at address (*THIS + VCALL_OFFSET). */ 8590 if (vcall_offset) 8591 { 8592 rtx vcall_offset_rtx = GEN_INT (vcall_offset); 8593 rtx scratch = gen_rtx_REG (Pmode, 1); 8594 8595 gcc_assert (vcall_offset < 0); 8596 8597 /* SCRATCH = *THIS. */ 8598 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this)); 8599 8600 /* Prepare for adding VCALL_OFFSET. The difficulty is that we 8601 may not have any available scratch register at this point. */ 8602 if (SPARC_SIMM13_P (vcall_offset)) 8603 ; 8604 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */ 8605 else if (! fixed_regs[5] 8606 /* The below sequence is made up of at least 2 insns, 8607 while the default method may need only one. */ 8608 && vcall_offset < -8192) 8609 { 8610 rtx scratch2 = gen_rtx_REG (Pmode, 5); 8611 emit_move_insn (scratch2, vcall_offset_rtx); 8612 vcall_offset_rtx = scratch2; 8613 } 8614 else 8615 { 8616 rtx increment = GEN_INT (-4096); 8617 8618 /* VCALL_OFFSET is a negative number whose typical range can be 8619 estimated as -32768..0 in 32-bit mode. In almost all cases 8620 it is therefore cheaper to emit multiple add insns than 8621 spilling and loading the constant into a register (at least 8622 6 insns). */ 8623 while (! SPARC_SIMM13_P (vcall_offset)) 8624 { 8625 emit_insn (gen_add2_insn (scratch, increment)); 8626 vcall_offset += 4096; 8627 } 8628 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */ 8629 } 8630 8631 /* SCRATCH = *(*THIS + VCALL_OFFSET). */ 8632 emit_move_insn (scratch, gen_rtx_MEM (Pmode, 8633 gen_rtx_PLUS (Pmode, 8634 scratch, 8635 vcall_offset_rtx))); 8636 8637 /* THIS += *(*THIS + VCALL_OFFSET). */ 8638 emit_insn (gen_add2_insn (this, scratch)); 8639 } 8640 8641 /* Generate a tail call to the target function. */ 8642 if (! TREE_USED (function)) 8643 { 8644 assemble_external (function); 8645 TREE_USED (function) = 1; 8646 } 8647 funexp = XEXP (DECL_RTL (function), 0); 8648 8649 if (flag_delayed_branch) 8650 { 8651 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); 8652 insn = emit_call_insn (gen_sibcall (funexp)); 8653 SIBLING_CALL_P (insn) = 1; 8654 } 8655 else 8656 { 8657 /* The hoops we have to jump through in order to generate a sibcall 8658 without using delay slots... */ 8659 rtx spill_reg, spill_reg2, seq, scratch = gen_rtx_REG (Pmode, 1); 8660 8661 if (flag_pic) 8662 { 8663 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */ 8664 spill_reg2 = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM); 8665 start_sequence (); 8666 /* Delay emitting the PIC helper function because it needs to 8667 change the section and we are emitting assembly code. */ 8668 load_pic_register (true); /* clobbers %o7 */ 8669 scratch = legitimize_pic_address (funexp, Pmode, scratch); 8670 seq = get_insns (); 8671 end_sequence (); 8672 emit_and_preserve (seq, spill_reg, spill_reg2); 8673 } 8674 else if (TARGET_ARCH32) 8675 { 8676 emit_insn (gen_rtx_SET (VOIDmode, 8677 scratch, 8678 gen_rtx_HIGH (SImode, funexp))); 8679 emit_insn (gen_rtx_SET (VOIDmode, 8680 scratch, 8681 gen_rtx_LO_SUM (SImode, scratch, funexp))); 8682 } 8683 else /* TARGET_ARCH64 */ 8684 { 8685 switch (sparc_cmodel) 8686 { 8687 case CM_MEDLOW: 8688 case CM_MEDMID: 8689 /* The destination can serve as a temporary. */ 8690 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch); 8691 break; 8692 8693 case CM_MEDANY: 8694 case CM_EMBMEDANY: 8695 /* The destination cannot serve as a temporary. */ 8696 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */ 8697 start_sequence (); 8698 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg); 8699 seq = get_insns (); 8700 end_sequence (); 8701 emit_and_preserve (seq, spill_reg, 0); 8702 break; 8703 8704 default: 8705 gcc_unreachable (); 8706 } 8707 } 8708 8709 emit_jump_insn (gen_indirect_jump (scratch)); 8710 } 8711 8712 emit_barrier (); 8713 8714 /* Run just enough of rest_of_compilation to get the insns emitted. 8715 There's not really enough bulk here to make other passes such as 8716 instruction scheduling worth while. Note that use_thunk calls 8717 assemble_start_function and assemble_end_function. */ 8718 insn = get_insns (); 8719 insn_locators_initialize (); 8720 shorten_branches (insn); 8721 final_start_function (insn, file, 1); 8722 final (insn, file, 1); 8723 final_end_function (); 8724 8725 reload_completed = 0; 8726 epilogue_completed = 0; 8727 no_new_pseudos = 0; 8728} 8729 8730/* Return true if sparc_output_mi_thunk would be able to output the 8731 assembler code for the thunk function specified by the arguments 8732 it is passed, and false otherwise. */ 8733static bool 8734sparc_can_output_mi_thunk (tree thunk_fndecl ATTRIBUTE_UNUSED, 8735 HOST_WIDE_INT delta ATTRIBUTE_UNUSED, 8736 HOST_WIDE_INT vcall_offset, 8737 tree function ATTRIBUTE_UNUSED) 8738{ 8739 /* Bound the loop used in the default method above. */ 8740 return (vcall_offset >= -32768 || ! fixed_regs[5]); 8741} 8742 8743/* How to allocate a 'struct machine_function'. */ 8744 8745static struct machine_function * 8746sparc_init_machine_status (void) 8747{ 8748 return ggc_alloc_cleared (sizeof (struct machine_function)); 8749} 8750 8751/* Locate some local-dynamic symbol still in use by this function 8752 so that we can print its name in local-dynamic base patterns. */ 8753 8754static const char * 8755get_some_local_dynamic_name (void) 8756{ 8757 rtx insn; 8758 8759 if (cfun->machine->some_ld_name) 8760 return cfun->machine->some_ld_name; 8761 8762 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) 8763 if (INSN_P (insn) 8764 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0)) 8765 return cfun->machine->some_ld_name; 8766 8767 gcc_unreachable (); 8768} 8769 8770static int 8771get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) 8772{ 8773 rtx x = *px; 8774 8775 if (x 8776 && GET_CODE (x) == SYMBOL_REF 8777 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) 8778 { 8779 cfun->machine->some_ld_name = XSTR (x, 0); 8780 return 1; 8781 } 8782 8783 return 0; 8784} 8785 8786/* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook. 8787 This is called from dwarf2out.c to emit call frame instructions 8788 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */ 8789static void 8790sparc_dwarf_handle_frame_unspec (const char *label, 8791 rtx pattern ATTRIBUTE_UNUSED, 8792 int index ATTRIBUTE_UNUSED) 8793{ 8794 gcc_assert (index == UNSPECV_SAVEW); 8795 dwarf2out_window_save (label); 8796} 8797 8798/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. 8799 We need to emit DTP-relative relocations. */ 8800 8801static void 8802sparc_output_dwarf_dtprel (FILE *file, int size, rtx x) 8803{ 8804 switch (size) 8805 { 8806 case 4: 8807 fputs ("\t.word\t%r_tls_dtpoff32(", file); 8808 break; 8809 case 8: 8810 fputs ("\t.xword\t%r_tls_dtpoff64(", file); 8811 break; 8812 default: 8813 gcc_unreachable (); 8814 } 8815 output_addr_const (file, x); 8816 fputs (")", file); 8817} 8818 8819/* Do whatever processing is required at the end of a file. */ 8820 8821static void 8822sparc_file_end (void) 8823{ 8824 /* If we haven't emitted the special PIC helper function, do so now. */ 8825 if (pic_helper_symbol_name[0] && !pic_helper_emitted_p) 8826 emit_pic_helper (); 8827 8828 if (NEED_INDICATE_EXEC_STACK) 8829 file_end_indicate_exec_stack (); 8830} 8831 8832#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING 8833/* Implement TARGET_MANGLE_FUNDAMENTAL_TYPE. */ 8834 8835static const char * 8836sparc_mangle_fundamental_type (tree type) 8837{ 8838 if (!TARGET_64BIT 8839 && TYPE_MAIN_VARIANT (type) == long_double_type_node 8840 && TARGET_LONG_DOUBLE_128) 8841 return "g"; 8842 8843 /* For all other types, use normal C++ mangling. */ 8844 return NULL; 8845} 8846#endif 8847 8848/* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit 8849 compare and swap on the word containing the byte or half-word. */ 8850 8851void 8852sparc_expand_compare_and_swap_12 (rtx result, rtx mem, rtx oldval, rtx newval) 8853{ 8854 rtx addr1 = force_reg (Pmode, XEXP (mem, 0)); 8855 rtx addr = gen_reg_rtx (Pmode); 8856 rtx off = gen_reg_rtx (SImode); 8857 rtx oldv = gen_reg_rtx (SImode); 8858 rtx newv = gen_reg_rtx (SImode); 8859 rtx oldvalue = gen_reg_rtx (SImode); 8860 rtx newvalue = gen_reg_rtx (SImode); 8861 rtx res = gen_reg_rtx (SImode); 8862 rtx resv = gen_reg_rtx (SImode); 8863 rtx memsi, val, mask, end_label, loop_label, cc; 8864 8865 emit_insn (gen_rtx_SET (VOIDmode, addr, 8866 gen_rtx_AND (Pmode, addr1, GEN_INT (-4)))); 8867 8868 if (Pmode != SImode) 8869 addr1 = gen_lowpart (SImode, addr1); 8870 emit_insn (gen_rtx_SET (VOIDmode, off, 8871 gen_rtx_AND (SImode, addr1, GEN_INT (3)))); 8872 8873 memsi = gen_rtx_MEM (SImode, addr); 8874 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER); 8875 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem); 8876 8877 val = force_reg (SImode, memsi); 8878 8879 emit_insn (gen_rtx_SET (VOIDmode, off, 8880 gen_rtx_XOR (SImode, off, 8881 GEN_INT (GET_MODE (mem) == QImode 8882 ? 3 : 2)))); 8883 8884 emit_insn (gen_rtx_SET (VOIDmode, off, 8885 gen_rtx_ASHIFT (SImode, off, GEN_INT (3)))); 8886 8887 if (GET_MODE (mem) == QImode) 8888 mask = force_reg (SImode, GEN_INT (0xff)); 8889 else 8890 mask = force_reg (SImode, GEN_INT (0xffff)); 8891 8892 emit_insn (gen_rtx_SET (VOIDmode, mask, 8893 gen_rtx_ASHIFT (SImode, mask, off))); 8894 8895 emit_insn (gen_rtx_SET (VOIDmode, val, 8896 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask), 8897 val))); 8898 8899 oldval = gen_lowpart (SImode, oldval); 8900 emit_insn (gen_rtx_SET (VOIDmode, oldv, 8901 gen_rtx_ASHIFT (SImode, oldval, off))); 8902 8903 newval = gen_lowpart_common (SImode, newval); 8904 emit_insn (gen_rtx_SET (VOIDmode, newv, 8905 gen_rtx_ASHIFT (SImode, newval, off))); 8906 8907 emit_insn (gen_rtx_SET (VOIDmode, oldv, 8908 gen_rtx_AND (SImode, oldv, mask))); 8909 8910 emit_insn (gen_rtx_SET (VOIDmode, newv, 8911 gen_rtx_AND (SImode, newv, mask))); 8912 8913 end_label = gen_label_rtx (); 8914 loop_label = gen_label_rtx (); 8915 emit_label (loop_label); 8916 8917 emit_insn (gen_rtx_SET (VOIDmode, oldvalue, 8918 gen_rtx_IOR (SImode, oldv, val))); 8919 8920 emit_insn (gen_rtx_SET (VOIDmode, newvalue, 8921 gen_rtx_IOR (SImode, newv, val))); 8922 8923 emit_insn (gen_sync_compare_and_swapsi (res, memsi, oldvalue, newvalue)); 8924 8925 emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label); 8926 8927 emit_insn (gen_rtx_SET (VOIDmode, resv, 8928 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask), 8929 res))); 8930 8931 sparc_compare_op0 = resv; 8932 sparc_compare_op1 = val; 8933 cc = gen_compare_reg (NE); 8934 8935 emit_insn (gen_rtx_SET (VOIDmode, val, resv)); 8936 8937 sparc_compare_emitted = cc; 8938 emit_jump_insn (gen_bne (loop_label)); 8939 8940 emit_label (end_label); 8941 8942 emit_insn (gen_rtx_SET (VOIDmode, res, 8943 gen_rtx_AND (SImode, res, mask))); 8944 8945 emit_insn (gen_rtx_SET (VOIDmode, res, 8946 gen_rtx_LSHIFTRT (SImode, res, off))); 8947 8948 emit_move_insn (result, gen_lowpart (GET_MODE (result), res)); 8949} 8950 8951#include "gt-sparc.h" 8952