1193323Sed//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines the interfaces that Mips uses to lower LLVM code into a 11193323Sed// selection DAG. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed#define DEBUG_TYPE "mips-lower" 15193323Sed#include "MipsISelLowering.h" 16252723Sdim#include "InstPrinter/MipsInstPrinter.h" 17252723Sdim#include "MCTargetDesc/MipsBaseInfo.h" 18193323Sed#include "MipsMachineFunction.h" 19252723Sdim#include "MipsSubtarget.h" 20193323Sed#include "MipsTargetMachine.h" 21198090Srdivacky#include "MipsTargetObjectFile.h" 22245431Sdim#include "llvm/ADT/Statistic.h" 23263509Sdim#include "llvm/ADT/StringSwitch.h" 24193323Sed#include "llvm/CodeGen/CallingConvLower.h" 25193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 26193323Sed#include "llvm/CodeGen/MachineFunction.h" 27193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 28193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 29193323Sed#include "llvm/CodeGen/SelectionDAGISel.h" 30193323Sed#include "llvm/CodeGen/ValueTypes.h" 31252723Sdim#include "llvm/IR/CallingConv.h" 32252723Sdim#include "llvm/IR/DerivedTypes.h" 33252723Sdim#include "llvm/IR/GlobalVariable.h" 34245431Sdim#include "llvm/Support/CommandLine.h" 35193323Sed#include "llvm/Support/Debug.h" 36198090Srdivacky#include "llvm/Support/ErrorHandling.h" 37235633Sdim#include "llvm/Support/raw_ostream.h" 38263509Sdim#include <cctype> 39235633Sdim 40193323Sedusing namespace llvm; 41193323Sed 42245431SdimSTATISTIC(NumTailCalls, "Number of tail calls"); 43245431Sdim 44245431Sdimstatic cl::opt<bool> 45245431SdimLargeGOT("mxgot", cl::Hidden, 46245431Sdim cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 47245431Sdim 48263509Sdimstatic cl::opt<bool> 49263509SdimNoZeroDivCheck("mno-check-zero-division", cl::Hidden, 50263509Sdim cl::desc("MIPS: Don't trap on integer division by zero."), 51263509Sdim cl::init(false)); 52263509Sdim 53245431Sdimstatic const uint16_t O32IntRegs[4] = { 54245431Sdim Mips::A0, Mips::A1, Mips::A2, Mips::A3 55245431Sdim}; 56245431Sdim 57245431Sdimstatic const uint16_t Mips64IntRegs[8] = { 58245431Sdim Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 59245431Sdim Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 60245431Sdim}; 61245431Sdim 62245431Sdimstatic const uint16_t Mips64DPRegs[8] = { 63245431Sdim Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 64245431Sdim Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 65245431Sdim}; 66245431Sdim 67235633Sdim// If I is a shifted mask, set the size (Size) and the first bit of the 68226890Sdim// mask (Pos), and return true. 69235633Sdim// For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 70252723Sdimstatic bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 71235633Sdim if (!isShiftedMask_64(I)) 72263509Sdim return false; 73226890Sdim 74235633Sdim Size = CountPopulation_64(I); 75263509Sdim Pos = countTrailingZeros(I); 76226890Sdim return true; 77226890Sdim} 78226890Sdim 79252723SdimSDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 80235633Sdim MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 81235633Sdim return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 82235633Sdim} 83235633Sdim 84263509SdimSDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, 85263509Sdim SelectionDAG &DAG, 86263509Sdim unsigned Flag) const { 87263509Sdim return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); 88245431Sdim} 89245431Sdim 90263509SdimSDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, 91263509Sdim SelectionDAG &DAG, 92263509Sdim unsigned Flag) const { 93263509Sdim return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 94245431Sdim} 95245431Sdim 96263509SdimSDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, 97263509Sdim SelectionDAG &DAG, 98263509Sdim unsigned Flag) const { 99263509Sdim return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 100245431Sdim} 101245431Sdim 102263509SdimSDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, 103263509Sdim SelectionDAG &DAG, 104252723Sdim unsigned Flag) const { 105263509Sdim return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 106245431Sdim} 107245431Sdim 108263509SdimSDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, 109263509Sdim SelectionDAG &DAG, 110263509Sdim unsigned Flag) const { 111263509Sdim return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 112263509Sdim N->getOffset(), Flag); 113245431Sdim} 114245431Sdim 115198090Srdivackyconst char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 116198090Srdivacky switch (Opcode) { 117223017Sdim case MipsISD::JmpLink: return "MipsISD::JmpLink"; 118245431Sdim case MipsISD::TailCall: return "MipsISD::TailCall"; 119223017Sdim case MipsISD::Hi: return "MipsISD::Hi"; 120223017Sdim case MipsISD::Lo: return "MipsISD::Lo"; 121223017Sdim case MipsISD::GPRel: return "MipsISD::GPRel"; 122223017Sdim case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 123223017Sdim case MipsISD::Ret: return "MipsISD::Ret"; 124252723Sdim case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 125223017Sdim case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 126223017Sdim case MipsISD::FPCmp: return "MipsISD::FPCmp"; 127223017Sdim case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 128223017Sdim case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 129263509Sdim case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 130263509Sdim case MipsISD::MFHI: return "MipsISD::MFHI"; 131263509Sdim case MipsISD::MFLO: return "MipsISD::MFLO"; 132263509Sdim case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; 133252723Sdim case MipsISD::Mult: return "MipsISD::Mult"; 134252723Sdim case MipsISD::Multu: return "MipsISD::Multu"; 135223017Sdim case MipsISD::MAdd: return "MipsISD::MAdd"; 136223017Sdim case MipsISD::MAddu: return "MipsISD::MAddu"; 137223017Sdim case MipsISD::MSub: return "MipsISD::MSub"; 138223017Sdim case MipsISD::MSubu: return "MipsISD::MSubu"; 139223017Sdim case MipsISD::DivRem: return "MipsISD::DivRem"; 140223017Sdim case MipsISD::DivRemU: return "MipsISD::DivRemU"; 141252723Sdim case MipsISD::DivRem16: return "MipsISD::DivRem16"; 142252723Sdim case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 143223017Sdim case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 144223017Sdim case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 145235633Sdim case MipsISD::Wrapper: return "MipsISD::Wrapper"; 146226890Sdim case MipsISD::Sync: return "MipsISD::Sync"; 147226890Sdim case MipsISD::Ext: return "MipsISD::Ext"; 148226890Sdim case MipsISD::Ins: return "MipsISD::Ins"; 149245431Sdim case MipsISD::LWL: return "MipsISD::LWL"; 150245431Sdim case MipsISD::LWR: return "MipsISD::LWR"; 151245431Sdim case MipsISD::SWL: return "MipsISD::SWL"; 152245431Sdim case MipsISD::SWR: return "MipsISD::SWR"; 153245431Sdim case MipsISD::LDL: return "MipsISD::LDL"; 154245431Sdim case MipsISD::LDR: return "MipsISD::LDR"; 155245431Sdim case MipsISD::SDL: return "MipsISD::SDL"; 156245431Sdim case MipsISD::SDR: return "MipsISD::SDR"; 157245431Sdim case MipsISD::EXTP: return "MipsISD::EXTP"; 158245431Sdim case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 159245431Sdim case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 160245431Sdim case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 161245431Sdim case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 162245431Sdim case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 163245431Sdim case MipsISD::SHILO: return "MipsISD::SHILO"; 164245431Sdim case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 165245431Sdim case MipsISD::MULT: return "MipsISD::MULT"; 166245431Sdim case MipsISD::MULTU: return "MipsISD::MULTU"; 167252723Sdim case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 168245431Sdim case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 169245431Sdim case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 170245431Sdim case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 171252723Sdim case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 172252723Sdim case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 173252723Sdim case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 174252723Sdim case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 175252723Sdim case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 176263509Sdim case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; 177263509Sdim case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; 178263509Sdim case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; 179263509Sdim case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; 180263509Sdim case MipsISD::VCEQ: return "MipsISD::VCEQ"; 181263509Sdim case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; 182263509Sdim case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; 183263509Sdim case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; 184263509Sdim case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; 185263509Sdim case MipsISD::VSMAX: return "MipsISD::VSMAX"; 186263509Sdim case MipsISD::VSMIN: return "MipsISD::VSMIN"; 187263509Sdim case MipsISD::VUMAX: return "MipsISD::VUMAX"; 188263509Sdim case MipsISD::VUMIN: return "MipsISD::VUMIN"; 189263509Sdim case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; 190263509Sdim case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; 191263509Sdim case MipsISD::VNOR: return "MipsISD::VNOR"; 192263509Sdim case MipsISD::VSHF: return "MipsISD::VSHF"; 193263509Sdim case MipsISD::SHF: return "MipsISD::SHF"; 194263509Sdim case MipsISD::ILVEV: return "MipsISD::ILVEV"; 195263509Sdim case MipsISD::ILVOD: return "MipsISD::ILVOD"; 196263509Sdim case MipsISD::ILVL: return "MipsISD::ILVL"; 197263509Sdim case MipsISD::ILVR: return "MipsISD::ILVR"; 198263509Sdim case MipsISD::PCKEV: return "MipsISD::PCKEV"; 199263509Sdim case MipsISD::PCKOD: return "MipsISD::PCKOD"; 200223017Sdim default: return NULL; 201193323Sed } 202193323Sed} 203193323Sed 204193323SedMipsTargetLowering:: 205198090SrdivackyMipsTargetLowering(MipsTargetMachine &TM) 206226890Sdim : TargetLowering(TM, new MipsTargetObjectFile()), 207226890Sdim Subtarget(&TM.getSubtarget<MipsSubtarget>()), 208235633Sdim HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 209235633Sdim IsO32(Subtarget->isABI_O32()) { 210193323Sed // Mips does not have i1 type, so use i32 for 211218893Sdim // setcc operations results (slt, sgt, ...). 212193323Sed setBooleanContents(ZeroOrOneBooleanContent); 213252723Sdim setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 214193323Sed 215218893Sdim // Load extented operations for i1 types must be promoted 216193323Sed setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 217193323Sed setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 218193323Sed setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 219193323Sed 220198090Srdivacky // MIPS doesn't have extending float->double load/store 221198090Srdivacky setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 222198090Srdivacky setTruncStoreAction(MVT::f64, MVT::f32, Expand); 223198090Srdivacky 224218893Sdim // Used by legalize types to correctly generate the setcc result. 225218893Sdim // Without this, every float setcc comes with a AND/OR with the result, 226218893Sdim // we don't want this, since the fpcmp result goes to a flag register, 227193323Sed // which is used implicitly by brcond and select operations. 228193323Sed AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 229193323Sed 230193323Sed // Mips Custom Operations 231252723Sdim setOperationAction(ISD::BR_JT, MVT::Other, Custom); 232193323Sed setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 233221345Sdim setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 234193323Sed setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 235193323Sed setOperationAction(ISD::JumpTable, MVT::i32, Custom); 236193323Sed setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 237193323Sed setOperationAction(ISD::SELECT, MVT::f32, Custom); 238194612Sed setOperationAction(ISD::SELECT, MVT::f64, Custom); 239193323Sed setOperationAction(ISD::SELECT, MVT::i32, Custom); 240245431Sdim setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 241245431Sdim setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 242235633Sdim setOperationAction(ISD::SETCC, MVT::f32, Custom); 243235633Sdim setOperationAction(ISD::SETCC, MVT::f64, Custom); 244193323Sed setOperationAction(ISD::BRCOND, MVT::Other, Custom); 245203954Srdivacky setOperationAction(ISD::VASTART, MVT::Other, Custom); 246235633Sdim setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 247235633Sdim setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 248263509Sdim setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 249193323Sed 250235633Sdim if (!TM.Options.NoNaNsFPMath) { 251235633Sdim setOperationAction(ISD::FABS, MVT::f32, Custom); 252235633Sdim setOperationAction(ISD::FABS, MVT::f64, Custom); 253235633Sdim } 254235633Sdim 255235633Sdim if (HasMips64) { 256235633Sdim setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 257235633Sdim setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 258235633Sdim setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 259235633Sdim setOperationAction(ISD::JumpTable, MVT::i64, Custom); 260235633Sdim setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 261235633Sdim setOperationAction(ISD::SELECT, MVT::i64, Custom); 262245431Sdim setOperationAction(ISD::LOAD, MVT::i64, Custom); 263245431Sdim setOperationAction(ISD::STORE, MVT::i64, Custom); 264263509Sdim setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 265235633Sdim } 266235633Sdim 267245431Sdim if (!HasMips64) { 268245431Sdim setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 269245431Sdim setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 270245431Sdim setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 271245431Sdim } 272245431Sdim 273245431Sdim setOperationAction(ISD::ADD, MVT::i32, Custom); 274245431Sdim if (HasMips64) 275245431Sdim setOperationAction(ISD::ADD, MVT::i64, Custom); 276245431Sdim 277221345Sdim setOperationAction(ISD::SDIV, MVT::i32, Expand); 278221345Sdim setOperationAction(ISD::SREM, MVT::i32, Expand); 279221345Sdim setOperationAction(ISD::UDIV, MVT::i32, Expand); 280221345Sdim setOperationAction(ISD::UREM, MVT::i32, Expand); 281226890Sdim setOperationAction(ISD::SDIV, MVT::i64, Expand); 282226890Sdim setOperationAction(ISD::SREM, MVT::i64, Expand); 283226890Sdim setOperationAction(ISD::UDIV, MVT::i64, Expand); 284226890Sdim setOperationAction(ISD::UREM, MVT::i64, Expand); 285203954Srdivacky 286193323Sed // Operations not directly supported by Mips. 287252723Sdim setOperationAction(ISD::BR_CC, MVT::f32, Expand); 288252723Sdim setOperationAction(ISD::BR_CC, MVT::f64, Expand); 289252723Sdim setOperationAction(ISD::BR_CC, MVT::i32, Expand); 290252723Sdim setOperationAction(ISD::BR_CC, MVT::i64, Expand); 291193323Sed setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 292193323Sed setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 293235633Sdim setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 294193323Sed setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 295235633Sdim setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 296193323Sed setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 297193323Sed setOperationAction(ISD::CTPOP, MVT::i32, Expand); 298235633Sdim setOperationAction(ISD::CTPOP, MVT::i64, Expand); 299193323Sed setOperationAction(ISD::CTTZ, MVT::i32, Expand); 300235633Sdim setOperationAction(ISD::CTTZ, MVT::i64, Expand); 301235633Sdim setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 302235633Sdim setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 303235633Sdim setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 304235633Sdim setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 305193323Sed setOperationAction(ISD::ROTL, MVT::i32, Expand); 306226890Sdim setOperationAction(ISD::ROTL, MVT::i64, Expand); 307245431Sdim setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 308245431Sdim setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 309218893Sdim 310226890Sdim if (!Subtarget->hasMips32r2()) 311218893Sdim setOperationAction(ISD::ROTR, MVT::i32, Expand); 312218893Sdim 313226890Sdim if (!Subtarget->hasMips64r2()) 314226890Sdim setOperationAction(ISD::ROTR, MVT::i64, Expand); 315226890Sdim 316198090Srdivacky setOperationAction(ISD::FSIN, MVT::f32, Expand); 317221345Sdim setOperationAction(ISD::FSIN, MVT::f64, Expand); 318198090Srdivacky setOperationAction(ISD::FCOS, MVT::f32, Expand); 319221345Sdim setOperationAction(ISD::FCOS, MVT::f64, Expand); 320252723Sdim setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 321252723Sdim setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 322198090Srdivacky setOperationAction(ISD::FPOWI, MVT::f32, Expand); 323198090Srdivacky setOperationAction(ISD::FPOW, MVT::f32, Expand); 324223017Sdim setOperationAction(ISD::FPOW, MVT::f64, Expand); 325198090Srdivacky setOperationAction(ISD::FLOG, MVT::f32, Expand); 326198090Srdivacky setOperationAction(ISD::FLOG2, MVT::f32, Expand); 327198090Srdivacky setOperationAction(ISD::FLOG10, MVT::f32, Expand); 328198090Srdivacky setOperationAction(ISD::FEXP, MVT::f32, Expand); 329224145Sdim setOperationAction(ISD::FMA, MVT::f32, Expand); 330224145Sdim setOperationAction(ISD::FMA, MVT::f64, Expand); 331235633Sdim setOperationAction(ISD::FREM, MVT::f32, Expand); 332235633Sdim setOperationAction(ISD::FREM, MVT::f64, Expand); 333193323Sed 334235633Sdim if (!TM.Options.NoNaNsFPMath) { 335235633Sdim setOperationAction(ISD::FNEG, MVT::f32, Expand); 336235633Sdim setOperationAction(ISD::FNEG, MVT::f64, Expand); 337235633Sdim } 338235633Sdim 339252723Sdim setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 340252723Sdim 341221345Sdim setOperationAction(ISD::VAARG, MVT::Other, Expand); 342221345Sdim setOperationAction(ISD::VACOPY, MVT::Other, Expand); 343221345Sdim setOperationAction(ISD::VAEND, MVT::Other, Expand); 344221345Sdim 345193323Sed // Use the default for now 346193323Sed setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 347193323Sed setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 348193323Sed 349235633Sdim setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 350235633Sdim setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 351235633Sdim setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 352235633Sdim setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 353226890Sdim 354226890Sdim setInsertFencesForAtomic(true); 355226890Sdim 356193323Sed if (!Subtarget->hasSEInReg()) { 357193323Sed setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 358193323Sed setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 359193323Sed } 360193323Sed 361235633Sdim if (!Subtarget->hasBitCount()) { 362193323Sed setOperationAction(ISD::CTLZ, MVT::i32, Expand); 363235633Sdim setOperationAction(ISD::CTLZ, MVT::i64, Expand); 364235633Sdim } 365193323Sed 366235633Sdim if (!Subtarget->hasSwap()) { 367193323Sed setOperationAction(ISD::BSWAP, MVT::i32, Expand); 368235633Sdim setOperationAction(ISD::BSWAP, MVT::i64, Expand); 369235633Sdim } 370193323Sed 371245431Sdim if (HasMips64) { 372245431Sdim setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 373245431Sdim setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 374245431Sdim setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 375245431Sdim setTruncStoreAction(MVT::i64, MVT::i32, Custom); 376245431Sdim } 377245431Sdim 378263509Sdim setOperationAction(ISD::TRAP, MVT::Other, Legal); 379263509Sdim 380221345Sdim setTargetDAGCombine(ISD::SDIVREM); 381221345Sdim setTargetDAGCombine(ISD::UDIVREM); 382235633Sdim setTargetDAGCombine(ISD::SELECT); 383226890Sdim setTargetDAGCombine(ISD::AND); 384226890Sdim setTargetDAGCombine(ISD::OR); 385245431Sdim setTargetDAGCombine(ISD::ADD); 386218893Sdim 387235633Sdim setMinFunctionAlignment(HasMips64 ? 3 : 2); 388223017Sdim 389235633Sdim setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 390223017Sdim 391235633Sdim setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 392235633Sdim setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 393245431Sdim 394252723Sdim MaxStoresPerMemcpy = 16; 395193323Sed} 396193323Sed 397252723Sdimconst MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) { 398252723Sdim if (TM.getSubtargetImpl()->inMips16Mode()) 399252723Sdim return llvm::createMips16TargetLowering(TM); 400235633Sdim 401252723Sdim return llvm::createMipsSETargetLowering(TM); 402226890Sdim} 403226890Sdim 404263509SdimEVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 405252723Sdim if (!VT.isVector()) 406252723Sdim return MVT::i32; 407252723Sdim return VT.changeVectorElementTypeToInteger(); 408193323Sed} 409193323Sed 410252723Sdimstatic SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 411221345Sdim TargetLowering::DAGCombinerInfo &DCI, 412245431Sdim const MipsSubtarget *Subtarget) { 413221345Sdim if (DCI.isBeforeLegalizeOps()) 414221345Sdim return SDValue(); 415221345Sdim 416226890Sdim EVT Ty = N->getValueType(0); 417263509Sdim unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; 418263509Sdim unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; 419252723Sdim unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 420252723Sdim MipsISD::DivRemU16; 421263509Sdim SDLoc DL(N); 422221345Sdim 423252723Sdim SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 424221345Sdim N->getOperand(0), N->getOperand(1)); 425221345Sdim SDValue InChain = DAG.getEntryNode(); 426221345Sdim SDValue InGlue = DivRem; 427221345Sdim 428221345Sdim // insert MFLO 429221345Sdim if (N->hasAnyUseOfValue(0)) { 430252723Sdim SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 431221345Sdim InGlue); 432221345Sdim DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 433221345Sdim InChain = CopyFromLo.getValue(1); 434221345Sdim InGlue = CopyFromLo.getValue(2); 435221345Sdim } 436221345Sdim 437221345Sdim // insert MFHI 438221345Sdim if (N->hasAnyUseOfValue(1)) { 439252723Sdim SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 440226890Sdim HI, Ty, InGlue); 441221345Sdim DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 442221345Sdim } 443221345Sdim 444221345Sdim return SDValue(); 445221345Sdim} 446221345Sdim 447252723Sdimstatic Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 448221345Sdim switch (CC) { 449221345Sdim default: llvm_unreachable("Unknown fp condition code!"); 450221345Sdim case ISD::SETEQ: 451221345Sdim case ISD::SETOEQ: return Mips::FCOND_OEQ; 452221345Sdim case ISD::SETUNE: return Mips::FCOND_UNE; 453221345Sdim case ISD::SETLT: 454221345Sdim case ISD::SETOLT: return Mips::FCOND_OLT; 455221345Sdim case ISD::SETGT: 456221345Sdim case ISD::SETOGT: return Mips::FCOND_OGT; 457221345Sdim case ISD::SETLE: 458221345Sdim case ISD::SETOLE: return Mips::FCOND_OLE; 459221345Sdim case ISD::SETGE: 460221345Sdim case ISD::SETOGE: return Mips::FCOND_OGE; 461221345Sdim case ISD::SETULT: return Mips::FCOND_ULT; 462221345Sdim case ISD::SETULE: return Mips::FCOND_ULE; 463221345Sdim case ISD::SETUGT: return Mips::FCOND_UGT; 464221345Sdim case ISD::SETUGE: return Mips::FCOND_UGE; 465221345Sdim case ISD::SETUO: return Mips::FCOND_UN; 466221345Sdim case ISD::SETO: return Mips::FCOND_OR; 467221345Sdim case ISD::SETNE: 468221345Sdim case ISD::SETONE: return Mips::FCOND_ONE; 469221345Sdim case ISD::SETUEQ: return Mips::FCOND_UEQ; 470221345Sdim } 471221345Sdim} 472221345Sdim 473221345Sdim 474252723Sdim/// This function returns true if the floating point conditional branches and 475252723Sdim/// conditional moves which use condition code CC should be inverted. 476252723Sdimstatic bool invertFPCondCodeUser(Mips::CondCode CC) { 477221345Sdim if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 478221345Sdim return false; 479221345Sdim 480235633Sdim assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 481235633Sdim "Illegal Condition Code"); 482221345Sdim 483235633Sdim return true; 484221345Sdim} 485221345Sdim 486221345Sdim// Creates and returns an FPCmp node from a setcc node. 487221345Sdim// Returns Op if setcc is not a floating point comparison. 488252723Sdimstatic SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 489221345Sdim // must be a SETCC node 490221345Sdim if (Op.getOpcode() != ISD::SETCC) 491221345Sdim return Op; 492221345Sdim 493221345Sdim SDValue LHS = Op.getOperand(0); 494221345Sdim 495221345Sdim if (!LHS.getValueType().isFloatingPoint()) 496221345Sdim return Op; 497221345Sdim 498221345Sdim SDValue RHS = Op.getOperand(1); 499263509Sdim SDLoc DL(Op); 500221345Sdim 501221345Sdim // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 502221345Sdim // node if necessary. 503221345Sdim ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 504221345Sdim 505252723Sdim return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 506252723Sdim DAG.getConstant(condCodeToFCC(CC), MVT::i32)); 507221345Sdim} 508221345Sdim 509221345Sdim// Creates and returns a CMovFPT/F node. 510252723Sdimstatic SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 511263509Sdim SDValue False, SDLoc DL) { 512252723Sdim ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 513252723Sdim bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 514263509Sdim SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 515221345Sdim 516221345Sdim return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 517263509Sdim True.getValueType(), True, FCC0, False, Cond); 518221345Sdim} 519221345Sdim 520252723Sdimstatic SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 521235633Sdim TargetLowering::DAGCombinerInfo &DCI, 522245431Sdim const MipsSubtarget *Subtarget) { 523221345Sdim if (DCI.isBeforeLegalizeOps()) 524221345Sdim return SDValue(); 525221345Sdim 526235633Sdim SDValue SetCC = N->getOperand(0); 527221345Sdim 528235633Sdim if ((SetCC.getOpcode() != ISD::SETCC) || 529235633Sdim !SetCC.getOperand(0).getValueType().isInteger()) 530221345Sdim return SDValue(); 531221345Sdim 532235633Sdim SDValue False = N->getOperand(2); 533235633Sdim EVT FalseTy = False.getValueType(); 534221345Sdim 535235633Sdim if (!FalseTy.isInteger()) 536235633Sdim return SDValue(); 537235633Sdim 538235633Sdim ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 539235633Sdim 540235633Sdim if (!CN || CN->getZExtValue()) 541235633Sdim return SDValue(); 542235633Sdim 543263509Sdim const SDLoc DL(N); 544235633Sdim ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 545235633Sdim SDValue True = N->getOperand(1); 546245431Sdim 547235633Sdim SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 548235633Sdim SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 549245431Sdim 550235633Sdim return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 551221345Sdim} 552221345Sdim 553252723Sdimstatic SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 554226890Sdim TargetLowering::DAGCombinerInfo &DCI, 555245431Sdim const MipsSubtarget *Subtarget) { 556226890Sdim // Pattern match EXT. 557226890Sdim // $dst = and ((sra or srl) $src , pos), (2**size - 1) 558226890Sdim // => ext $dst, $src, size, pos 559263509Sdim if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert()) 560226890Sdim return SDValue(); 561226890Sdim 562226890Sdim SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 563235633Sdim unsigned ShiftRightOpc = ShiftRight.getOpcode(); 564235633Sdim 565226890Sdim // Op's first operand must be a shift right. 566235633Sdim if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 567226890Sdim return SDValue(); 568226890Sdim 569226890Sdim // The second operand of the shift must be an immediate. 570226890Sdim ConstantSDNode *CN; 571226890Sdim if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 572226890Sdim return SDValue(); 573226890Sdim 574235633Sdim uint64_t Pos = CN->getZExtValue(); 575226890Sdim uint64_t SMPos, SMSize; 576235633Sdim 577226890Sdim // Op's second operand must be a shifted mask. 578226890Sdim if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 579252723Sdim !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 580226890Sdim return SDValue(); 581226890Sdim 582226890Sdim // Return if the shifted mask does not start at bit 0 or the sum of its size 583226890Sdim // and Pos exceeds the word's size. 584235633Sdim EVT ValTy = N->getValueType(0); 585235633Sdim if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 586226890Sdim return SDValue(); 587226890Sdim 588263509Sdim return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy, 589235633Sdim ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 590226890Sdim DAG.getConstant(SMSize, MVT::i32)); 591226890Sdim} 592235633Sdim 593252723Sdimstatic SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 594226890Sdim TargetLowering::DAGCombinerInfo &DCI, 595245431Sdim const MipsSubtarget *Subtarget) { 596226890Sdim // Pattern match INS. 597226890Sdim // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 598235633Sdim // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 599226890Sdim // => ins $dst, $src, size, pos, $src1 600263509Sdim if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert()) 601226890Sdim return SDValue(); 602226890Sdim 603226890Sdim SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 604226890Sdim uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 605226890Sdim ConstantSDNode *CN; 606226890Sdim 607226890Sdim // See if Op's first operand matches (and $src1 , mask0). 608226890Sdim if (And0.getOpcode() != ISD::AND) 609226890Sdim return SDValue(); 610226890Sdim 611226890Sdim if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 612252723Sdim !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 613226890Sdim return SDValue(); 614226890Sdim 615226890Sdim // See if Op's second operand matches (and (shl $src, pos), mask1). 616226890Sdim if (And1.getOpcode() != ISD::AND) 617226890Sdim return SDValue(); 618235633Sdim 619226890Sdim if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 620252723Sdim !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 621226890Sdim return SDValue(); 622226890Sdim 623226890Sdim // The shift masks must have the same position and size. 624226890Sdim if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 625226890Sdim return SDValue(); 626226890Sdim 627226890Sdim SDValue Shl = And1.getOperand(0); 628226890Sdim if (Shl.getOpcode() != ISD::SHL) 629226890Sdim return SDValue(); 630226890Sdim 631226890Sdim if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 632226890Sdim return SDValue(); 633226890Sdim 634226890Sdim unsigned Shamt = CN->getZExtValue(); 635226890Sdim 636226890Sdim // Return if the shift amount and the first bit position of mask are not the 637235633Sdim // same. 638235633Sdim EVT ValTy = N->getValueType(0); 639235633Sdim if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 640226890Sdim return SDValue(); 641235633Sdim 642263509Sdim return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0), 643226890Sdim DAG.getConstant(SMPos0, MVT::i32), 644235633Sdim DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 645226890Sdim} 646235633Sdim 647252723Sdimstatic SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 648245431Sdim TargetLowering::DAGCombinerInfo &DCI, 649245431Sdim const MipsSubtarget *Subtarget) { 650245431Sdim // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 651245431Sdim 652245431Sdim if (DCI.isBeforeLegalizeOps()) 653245431Sdim return SDValue(); 654245431Sdim 655245431Sdim SDValue Add = N->getOperand(1); 656245431Sdim 657245431Sdim if (Add.getOpcode() != ISD::ADD) 658245431Sdim return SDValue(); 659245431Sdim 660245431Sdim SDValue Lo = Add.getOperand(1); 661245431Sdim 662245431Sdim if ((Lo.getOpcode() != MipsISD::Lo) || 663245431Sdim (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 664245431Sdim return SDValue(); 665245431Sdim 666245431Sdim EVT ValTy = N->getValueType(0); 667263509Sdim SDLoc DL(N); 668245431Sdim 669245431Sdim SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 670245431Sdim Add.getOperand(0)); 671245431Sdim return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 672245431Sdim} 673245431Sdim 674218893SdimSDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 675218893Sdim const { 676218893Sdim SelectionDAG &DAG = DCI.DAG; 677252723Sdim unsigned Opc = N->getOpcode(); 678218893Sdim 679252723Sdim switch (Opc) { 680218893Sdim default: break; 681221345Sdim case ISD::SDIVREM: 682221345Sdim case ISD::UDIVREM: 683252723Sdim return performDivRemCombine(N, DAG, DCI, Subtarget); 684235633Sdim case ISD::SELECT: 685252723Sdim return performSELECTCombine(N, DAG, DCI, Subtarget); 686226890Sdim case ISD::AND: 687252723Sdim return performANDCombine(N, DAG, DCI, Subtarget); 688226890Sdim case ISD::OR: 689252723Sdim return performORCombine(N, DAG, DCI, Subtarget); 690245431Sdim case ISD::ADD: 691252723Sdim return performADDCombine(N, DAG, DCI, Subtarget); 692218893Sdim } 693218893Sdim 694218893Sdim return SDValue(); 695218893Sdim} 696218893Sdim 697245431Sdimvoid 698245431SdimMipsTargetLowering::LowerOperationWrapper(SDNode *N, 699245431Sdim SmallVectorImpl<SDValue> &Results, 700245431Sdim SelectionDAG &DAG) const { 701245431Sdim SDValue Res = LowerOperation(SDValue(N, 0), DAG); 702245431Sdim 703245431Sdim for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 704245431Sdim Results.push_back(Res.getValue(I)); 705245431Sdim} 706245431Sdim 707245431Sdimvoid 708245431SdimMipsTargetLowering::ReplaceNodeResults(SDNode *N, 709245431Sdim SmallVectorImpl<SDValue> &Results, 710245431Sdim SelectionDAG &DAG) const { 711252723Sdim return LowerOperationWrapper(N, Results, DAG); 712245431Sdim} 713245431Sdim 714193323SedSDValue MipsTargetLowering:: 715207618SrdivackyLowerOperation(SDValue Op, SelectionDAG &DAG) const 716193323Sed{ 717218893Sdim switch (Op.getOpcode()) 718193323Sed { 719252723Sdim case ISD::BR_JT: return lowerBR_JT(Op, DAG); 720252723Sdim case ISD::BRCOND: return lowerBRCOND(Op, DAG); 721252723Sdim case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 722252723Sdim case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 723252723Sdim case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 724252723Sdim case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 725252723Sdim case ISD::JumpTable: return lowerJumpTable(Op, DAG); 726252723Sdim case ISD::SELECT: return lowerSELECT(Op, DAG); 727252723Sdim case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); 728252723Sdim case ISD::SETCC: return lowerSETCC(Op, DAG); 729252723Sdim case ISD::VASTART: return lowerVASTART(Op, DAG); 730252723Sdim case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 731252723Sdim case ISD::FABS: return lowerFABS(Op, DAG); 732252723Sdim case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 733252723Sdim case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 734252723Sdim case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 735252723Sdim case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 736252723Sdim case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 737252723Sdim case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 738252723Sdim case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 739252723Sdim case ISD::LOAD: return lowerLOAD(Op, DAG); 740252723Sdim case ISD::STORE: return lowerSTORE(Op, DAG); 741252723Sdim case ISD::ADD: return lowerADD(Op, DAG); 742263509Sdim case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 743193323Sed } 744193323Sed return SDValue(); 745193323Sed} 746193323Sed 747193323Sed//===----------------------------------------------------------------------===// 748193323Sed// Lower helper functions 749193323Sed//===----------------------------------------------------------------------===// 750193323Sed 751252723Sdim// addLiveIn - This helper function adds the specified physical register to the 752193323Sed// MachineFunction as a live in value. It also creates a corresponding 753193323Sed// virtual register for it. 754193323Sedstatic unsigned 755252723SdimaddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 756193323Sed{ 757193323Sed unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 758193323Sed MF.getRegInfo().addLiveIn(PReg, VReg); 759193323Sed return VReg; 760193323Sed} 761193323Sed 762263509Sdimstatic MachineBasicBlock *expandPseudoDIV(MachineInstr *MI, 763263509Sdim MachineBasicBlock &MBB, 764263509Sdim const TargetInstrInfo &TII, 765263509Sdim bool Is64Bit) { 766263509Sdim if (NoZeroDivCheck) 767263509Sdim return &MBB; 768263509Sdim 769263509Sdim // Insert instruction "teq $divisor_reg, $zero, 7". 770263509Sdim MachineBasicBlock::iterator I(MI); 771263509Sdim MachineInstrBuilder MIB; 772263509Sdim MachineOperand &Divisor = MI->getOperand(2); 773263509Sdim MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ)) 774263509Sdim .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) 775263509Sdim .addReg(Mips::ZERO).addImm(7); 776263509Sdim 777263509Sdim // Use the 32-bit sub-register if this is a 64-bit division. 778263509Sdim if (Is64Bit) 779263509Sdim MIB->getOperand(0).setSubReg(Mips::sub_32); 780263509Sdim 781263509Sdim // Clear Divisor's kill flag. 782263509Sdim Divisor.setIsKill(false); 783263509Sdim return &MBB; 784263509Sdim} 785263509Sdim 786223017SdimMachineBasicBlock * 787223017SdimMipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 788223017Sdim MachineBasicBlock *BB) const { 789223017Sdim switch (MI->getOpcode()) { 790252723Sdim default: 791252723Sdim llvm_unreachable("Unexpected instr type to insert"); 792223017Sdim case Mips::ATOMIC_LOAD_ADD_I8: 793252723Sdim return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 794223017Sdim case Mips::ATOMIC_LOAD_ADD_I16: 795252723Sdim return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 796223017Sdim case Mips::ATOMIC_LOAD_ADD_I32: 797252723Sdim return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 798235633Sdim case Mips::ATOMIC_LOAD_ADD_I64: 799252723Sdim return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 800193323Sed 801223017Sdim case Mips::ATOMIC_LOAD_AND_I8: 802252723Sdim return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 803223017Sdim case Mips::ATOMIC_LOAD_AND_I16: 804252723Sdim return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 805223017Sdim case Mips::ATOMIC_LOAD_AND_I32: 806252723Sdim return emitAtomicBinary(MI, BB, 4, Mips::AND); 807235633Sdim case Mips::ATOMIC_LOAD_AND_I64: 808252723Sdim return emitAtomicBinary(MI, BB, 8, Mips::AND64); 809193323Sed 810223017Sdim case Mips::ATOMIC_LOAD_OR_I8: 811252723Sdim return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 812223017Sdim case Mips::ATOMIC_LOAD_OR_I16: 813252723Sdim return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 814223017Sdim case Mips::ATOMIC_LOAD_OR_I32: 815252723Sdim return emitAtomicBinary(MI, BB, 4, Mips::OR); 816235633Sdim case Mips::ATOMIC_LOAD_OR_I64: 817252723Sdim return emitAtomicBinary(MI, BB, 8, Mips::OR64); 818193323Sed 819223017Sdim case Mips::ATOMIC_LOAD_XOR_I8: 820252723Sdim return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 821223017Sdim case Mips::ATOMIC_LOAD_XOR_I16: 822252723Sdim return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 823223017Sdim case Mips::ATOMIC_LOAD_XOR_I32: 824252723Sdim return emitAtomicBinary(MI, BB, 4, Mips::XOR); 825235633Sdim case Mips::ATOMIC_LOAD_XOR_I64: 826252723Sdim return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 827193323Sed 828223017Sdim case Mips::ATOMIC_LOAD_NAND_I8: 829252723Sdim return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 830223017Sdim case Mips::ATOMIC_LOAD_NAND_I16: 831252723Sdim return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 832223017Sdim case Mips::ATOMIC_LOAD_NAND_I32: 833252723Sdim return emitAtomicBinary(MI, BB, 4, 0, true); 834235633Sdim case Mips::ATOMIC_LOAD_NAND_I64: 835252723Sdim return emitAtomicBinary(MI, BB, 8, 0, true); 836193323Sed 837223017Sdim case Mips::ATOMIC_LOAD_SUB_I8: 838252723Sdim return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 839223017Sdim case Mips::ATOMIC_LOAD_SUB_I16: 840252723Sdim return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 841223017Sdim case Mips::ATOMIC_LOAD_SUB_I32: 842252723Sdim return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 843235633Sdim case Mips::ATOMIC_LOAD_SUB_I64: 844252723Sdim return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 845223017Sdim 846223017Sdim case Mips::ATOMIC_SWAP_I8: 847252723Sdim return emitAtomicBinaryPartword(MI, BB, 1, 0); 848223017Sdim case Mips::ATOMIC_SWAP_I16: 849252723Sdim return emitAtomicBinaryPartword(MI, BB, 2, 0); 850223017Sdim case Mips::ATOMIC_SWAP_I32: 851252723Sdim return emitAtomicBinary(MI, BB, 4, 0); 852235633Sdim case Mips::ATOMIC_SWAP_I64: 853252723Sdim return emitAtomicBinary(MI, BB, 8, 0); 854223017Sdim 855223017Sdim case Mips::ATOMIC_CMP_SWAP_I8: 856252723Sdim return emitAtomicCmpSwapPartword(MI, BB, 1); 857223017Sdim case Mips::ATOMIC_CMP_SWAP_I16: 858252723Sdim return emitAtomicCmpSwapPartword(MI, BB, 2); 859223017Sdim case Mips::ATOMIC_CMP_SWAP_I32: 860252723Sdim return emitAtomicCmpSwap(MI, BB, 4); 861235633Sdim case Mips::ATOMIC_CMP_SWAP_I64: 862252723Sdim return emitAtomicCmpSwap(MI, BB, 8); 863263509Sdim case Mips::PseudoSDIV: 864263509Sdim case Mips::PseudoUDIV: 865263509Sdim return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false); 866263509Sdim case Mips::PseudoDSDIV: 867263509Sdim case Mips::PseudoDUDIV: 868263509Sdim return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true); 869223017Sdim } 870193323Sed} 871193323Sed 872223017Sdim// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 873223017Sdim// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 874223017SdimMachineBasicBlock * 875252723SdimMipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 876223017Sdim unsigned Size, unsigned BinOpcode, 877223017Sdim bool Nand) const { 878235633Sdim assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 879223017Sdim 880223017Sdim MachineFunction *MF = BB->getParent(); 881223017Sdim MachineRegisterInfo &RegInfo = MF->getRegInfo(); 882235633Sdim const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 883223017Sdim const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 884252723Sdim DebugLoc DL = MI->getDebugLoc(); 885235633Sdim unsigned LL, SC, AND, NOR, ZERO, BEQ; 886223017Sdim 887235633Sdim if (Size == 4) { 888263509Sdim LL = Mips::LL; 889263509Sdim SC = Mips::SC; 890235633Sdim AND = Mips::AND; 891235633Sdim NOR = Mips::NOR; 892235633Sdim ZERO = Mips::ZERO; 893235633Sdim BEQ = Mips::BEQ; 894235633Sdim } 895235633Sdim else { 896263509Sdim LL = Mips::LLD; 897263509Sdim SC = Mips::SCD; 898235633Sdim AND = Mips::AND64; 899235633Sdim NOR = Mips::NOR64; 900235633Sdim ZERO = Mips::ZERO_64; 901235633Sdim BEQ = Mips::BEQ64; 902235633Sdim } 903235633Sdim 904226890Sdim unsigned OldVal = MI->getOperand(0).getReg(); 905223017Sdim unsigned Ptr = MI->getOperand(1).getReg(); 906223017Sdim unsigned Incr = MI->getOperand(2).getReg(); 907223017Sdim 908226890Sdim unsigned StoreVal = RegInfo.createVirtualRegister(RC); 909226890Sdim unsigned AndRes = RegInfo.createVirtualRegister(RC); 910226890Sdim unsigned Success = RegInfo.createVirtualRegister(RC); 911223017Sdim 912223017Sdim // insert new blocks after the current block 913223017Sdim const BasicBlock *LLVM_BB = BB->getBasicBlock(); 914223017Sdim MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 915223017Sdim MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 916223017Sdim MachineFunction::iterator It = BB; 917223017Sdim ++It; 918223017Sdim MF->insert(It, loopMBB); 919223017Sdim MF->insert(It, exitMBB); 920223017Sdim 921223017Sdim // Transfer the remainder of BB and its successor edges to exitMBB. 922223017Sdim exitMBB->splice(exitMBB->begin(), BB, 923263509Sdim llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 924223017Sdim exitMBB->transferSuccessorsAndUpdatePHIs(BB); 925223017Sdim 926223017Sdim // thisMBB: 927223017Sdim // ... 928223017Sdim // fallthrough --> loopMBB 929223017Sdim BB->addSuccessor(loopMBB); 930226890Sdim loopMBB->addSuccessor(loopMBB); 931226890Sdim loopMBB->addSuccessor(exitMBB); 932223017Sdim 933223017Sdim // loopMBB: 934223017Sdim // ll oldval, 0(ptr) 935226890Sdim // <binop> storeval, oldval, incr 936226890Sdim // sc success, storeval, 0(ptr) 937226890Sdim // beq success, $0, loopMBB 938223017Sdim BB = loopMBB; 939252723Sdim BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 940223017Sdim if (Nand) { 941226890Sdim // and andres, oldval, incr 942226890Sdim // nor storeval, $0, andres 943252723Sdim BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 944252723Sdim BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 945223017Sdim } else if (BinOpcode) { 946226890Sdim // <binop> storeval, oldval, incr 947252723Sdim BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 948223017Sdim } else { 949226890Sdim StoreVal = Incr; 950223017Sdim } 951252723Sdim BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 952252723Sdim BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 953223017Sdim 954263509Sdim MI->eraseFromParent(); // The instruction is gone now. 955223017Sdim 956226890Sdim return exitMBB; 957223017Sdim} 958223017Sdim 959223017SdimMachineBasicBlock * 960252723SdimMipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI, 961223017Sdim MachineBasicBlock *BB, 962223017Sdim unsigned Size, unsigned BinOpcode, 963223017Sdim bool Nand) const { 964223017Sdim assert((Size == 1 || Size == 2) && 965263509Sdim "Unsupported size for EmitAtomicBinaryPartial."); 966223017Sdim 967223017Sdim MachineFunction *MF = BB->getParent(); 968223017Sdim MachineRegisterInfo &RegInfo = MF->getRegInfo(); 969223017Sdim const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 970223017Sdim const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 971252723Sdim DebugLoc DL = MI->getDebugLoc(); 972223017Sdim 973223017Sdim unsigned Dest = MI->getOperand(0).getReg(); 974223017Sdim unsigned Ptr = MI->getOperand(1).getReg(); 975223017Sdim unsigned Incr = MI->getOperand(2).getReg(); 976223017Sdim 977226890Sdim unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 978226890Sdim unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 979223017Sdim unsigned Mask = RegInfo.createVirtualRegister(RC); 980223017Sdim unsigned Mask2 = RegInfo.createVirtualRegister(RC); 981226890Sdim unsigned NewVal = RegInfo.createVirtualRegister(RC); 982226890Sdim unsigned OldVal = RegInfo.createVirtualRegister(RC); 983223017Sdim unsigned Incr2 = RegInfo.createVirtualRegister(RC); 984226890Sdim unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 985226890Sdim unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 986226890Sdim unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 987226890Sdim unsigned AndRes = RegInfo.createVirtualRegister(RC); 988226890Sdim unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 989226890Sdim unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 990226890Sdim unsigned StoreVal = RegInfo.createVirtualRegister(RC); 991226890Sdim unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 992226890Sdim unsigned SrlRes = RegInfo.createVirtualRegister(RC); 993226890Sdim unsigned SllRes = RegInfo.createVirtualRegister(RC); 994226890Sdim unsigned Success = RegInfo.createVirtualRegister(RC); 995223017Sdim 996223017Sdim // insert new blocks after the current block 997223017Sdim const BasicBlock *LLVM_BB = BB->getBasicBlock(); 998223017Sdim MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 999226890Sdim MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1000223017Sdim MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1001223017Sdim MachineFunction::iterator It = BB; 1002223017Sdim ++It; 1003223017Sdim MF->insert(It, loopMBB); 1004226890Sdim MF->insert(It, sinkMBB); 1005223017Sdim MF->insert(It, exitMBB); 1006223017Sdim 1007223017Sdim // Transfer the remainder of BB and its successor edges to exitMBB. 1008223017Sdim exitMBB->splice(exitMBB->begin(), BB, 1009235633Sdim llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1010223017Sdim exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1011223017Sdim 1012226890Sdim BB->addSuccessor(loopMBB); 1013226890Sdim loopMBB->addSuccessor(loopMBB); 1014226890Sdim loopMBB->addSuccessor(sinkMBB); 1015226890Sdim sinkMBB->addSuccessor(exitMBB); 1016226890Sdim 1017223017Sdim // thisMBB: 1018226890Sdim // addiu masklsb2,$0,-4 # 0xfffffffc 1019226890Sdim // and alignedaddr,ptr,masklsb2 1020226890Sdim // andi ptrlsb2,ptr,3 1021226890Sdim // sll shiftamt,ptrlsb2,3 1022226890Sdim // ori maskupper,$0,255 # 0xff 1023226890Sdim // sll mask,maskupper,shiftamt 1024223017Sdim // nor mask2,$0,mask 1025226890Sdim // sll incr2,incr,shiftamt 1026223017Sdim 1027223017Sdim int64_t MaskImm = (Size == 1) ? 255 : 65535; 1028252723Sdim BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1029226890Sdim .addReg(Mips::ZERO).addImm(-4); 1030252723Sdim BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1031226890Sdim .addReg(Ptr).addReg(MaskLSB2); 1032252723Sdim BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1033263509Sdim if (Subtarget->isLittle()) { 1034263509Sdim BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1035263509Sdim } else { 1036263509Sdim unsigned Off = RegInfo.createVirtualRegister(RC); 1037263509Sdim BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1038263509Sdim .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1039263509Sdim BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1040263509Sdim } 1041252723Sdim BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1042226890Sdim .addReg(Mips::ZERO).addImm(MaskImm); 1043252723Sdim BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1044263509Sdim .addReg(MaskUpper).addReg(ShiftAmt); 1045252723Sdim BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1046263509Sdim BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1047223017Sdim 1048226890Sdim // atomic.load.binop 1049226890Sdim // loopMBB: 1050226890Sdim // ll oldval,0(alignedaddr) 1051226890Sdim // binop binopres,oldval,incr2 1052226890Sdim // and newval,binopres,mask 1053226890Sdim // and maskedoldval0,oldval,mask2 1054226890Sdim // or storeval,maskedoldval0,newval 1055226890Sdim // sc success,storeval,0(alignedaddr) 1056226890Sdim // beq success,$0,loopMBB 1057223017Sdim 1058226890Sdim // atomic.swap 1059223017Sdim // loopMBB: 1060226890Sdim // ll oldval,0(alignedaddr) 1061226890Sdim // and newval,incr2,mask 1062226890Sdim // and maskedoldval0,oldval,mask2 1063226890Sdim // or storeval,maskedoldval0,newval 1064226890Sdim // sc success,storeval,0(alignedaddr) 1065226890Sdim // beq success,$0,loopMBB 1066226890Sdim 1067223017Sdim BB = loopMBB; 1068263509Sdim BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1069223017Sdim if (Nand) { 1070226890Sdim // and andres, oldval, incr2 1071226890Sdim // nor binopres, $0, andres 1072226890Sdim // and newval, binopres, mask 1073252723Sdim BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1074252723Sdim BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1075226890Sdim .addReg(Mips::ZERO).addReg(AndRes); 1076252723Sdim BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1077223017Sdim } else if (BinOpcode) { 1078226890Sdim // <binop> binopres, oldval, incr2 1079226890Sdim // and newval, binopres, mask 1080252723Sdim BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1081252723Sdim BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1082263509Sdim } else { // atomic.swap 1083226890Sdim // and newval, incr2, mask 1084252723Sdim BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1085223017Sdim } 1086235633Sdim 1087252723Sdim BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1088226890Sdim .addReg(OldVal).addReg(Mask2); 1089252723Sdim BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1090226890Sdim .addReg(MaskedOldVal0).addReg(NewVal); 1091263509Sdim BuildMI(BB, DL, TII->get(Mips::SC), Success) 1092226890Sdim .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1093252723Sdim BuildMI(BB, DL, TII->get(Mips::BEQ)) 1094226890Sdim .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1095223017Sdim 1096226890Sdim // sinkMBB: 1097226890Sdim // and maskedoldval1,oldval,mask 1098226890Sdim // srl srlres,maskedoldval1,shiftamt 1099226890Sdim // sll sllres,srlres,24 1100226890Sdim // sra dest,sllres,24 1101226890Sdim BB = sinkMBB; 1102223017Sdim int64_t ShiftImm = (Size == 1) ? 24 : 16; 1103223017Sdim 1104252723Sdim BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1105226890Sdim .addReg(OldVal).addReg(Mask); 1106252723Sdim BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1107263509Sdim .addReg(MaskedOldVal1).addReg(ShiftAmt); 1108252723Sdim BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1109226890Sdim .addReg(SrlRes).addImm(ShiftImm); 1110252723Sdim BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1111226890Sdim .addReg(SllRes).addImm(ShiftImm); 1112226890Sdim 1113263509Sdim MI->eraseFromParent(); // The instruction is gone now. 1114223017Sdim 1115226890Sdim return exitMBB; 1116223017Sdim} 1117223017Sdim 1118263509SdimMachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI, 1119263509Sdim MachineBasicBlock *BB, 1120263509Sdim unsigned Size) const { 1121235633Sdim assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1122223017Sdim 1123223017Sdim MachineFunction *MF = BB->getParent(); 1124223017Sdim MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1125235633Sdim const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1126223017Sdim const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1127252723Sdim DebugLoc DL = MI->getDebugLoc(); 1128235633Sdim unsigned LL, SC, ZERO, BNE, BEQ; 1129223017Sdim 1130235633Sdim if (Size == 4) { 1131263509Sdim LL = Mips::LL; 1132263509Sdim SC = Mips::SC; 1133235633Sdim ZERO = Mips::ZERO; 1134235633Sdim BNE = Mips::BNE; 1135235633Sdim BEQ = Mips::BEQ; 1136263509Sdim } else { 1137263509Sdim LL = Mips::LLD; 1138263509Sdim SC = Mips::SCD; 1139235633Sdim ZERO = Mips::ZERO_64; 1140235633Sdim BNE = Mips::BNE64; 1141235633Sdim BEQ = Mips::BEQ64; 1142235633Sdim } 1143235633Sdim 1144223017Sdim unsigned Dest = MI->getOperand(0).getReg(); 1145223017Sdim unsigned Ptr = MI->getOperand(1).getReg(); 1146226890Sdim unsigned OldVal = MI->getOperand(2).getReg(); 1147226890Sdim unsigned NewVal = MI->getOperand(3).getReg(); 1148223017Sdim 1149226890Sdim unsigned Success = RegInfo.createVirtualRegister(RC); 1150223017Sdim 1151223017Sdim // insert new blocks after the current block 1152223017Sdim const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1153223017Sdim MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1154223017Sdim MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1155223017Sdim MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1156223017Sdim MachineFunction::iterator It = BB; 1157223017Sdim ++It; 1158223017Sdim MF->insert(It, loop1MBB); 1159223017Sdim MF->insert(It, loop2MBB); 1160223017Sdim MF->insert(It, exitMBB); 1161223017Sdim 1162223017Sdim // Transfer the remainder of BB and its successor edges to exitMBB. 1163223017Sdim exitMBB->splice(exitMBB->begin(), BB, 1164235633Sdim llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1165223017Sdim exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1166223017Sdim 1167223017Sdim // thisMBB: 1168223017Sdim // ... 1169223017Sdim // fallthrough --> loop1MBB 1170223017Sdim BB->addSuccessor(loop1MBB); 1171226890Sdim loop1MBB->addSuccessor(exitMBB); 1172226890Sdim loop1MBB->addSuccessor(loop2MBB); 1173226890Sdim loop2MBB->addSuccessor(loop1MBB); 1174226890Sdim loop2MBB->addSuccessor(exitMBB); 1175223017Sdim 1176223017Sdim // loop1MBB: 1177223017Sdim // ll dest, 0(ptr) 1178223017Sdim // bne dest, oldval, exitMBB 1179223017Sdim BB = loop1MBB; 1180252723Sdim BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1181252723Sdim BuildMI(BB, DL, TII->get(BNE)) 1182226890Sdim .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1183223017Sdim 1184223017Sdim // loop2MBB: 1185226890Sdim // sc success, newval, 0(ptr) 1186226890Sdim // beq success, $0, loop1MBB 1187223017Sdim BB = loop2MBB; 1188252723Sdim BuildMI(BB, DL, TII->get(SC), Success) 1189226890Sdim .addReg(NewVal).addReg(Ptr).addImm(0); 1190252723Sdim BuildMI(BB, DL, TII->get(BEQ)) 1191235633Sdim .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1192223017Sdim 1193263509Sdim MI->eraseFromParent(); // The instruction is gone now. 1194223017Sdim 1195226890Sdim return exitMBB; 1196223017Sdim} 1197223017Sdim 1198223017SdimMachineBasicBlock * 1199252723SdimMipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, 1200223017Sdim MachineBasicBlock *BB, 1201223017Sdim unsigned Size) const { 1202223017Sdim assert((Size == 1 || Size == 2) && 1203223017Sdim "Unsupported size for EmitAtomicCmpSwapPartial."); 1204223017Sdim 1205223017Sdim MachineFunction *MF = BB->getParent(); 1206223017Sdim MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1207223017Sdim const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1208223017Sdim const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1209252723Sdim DebugLoc DL = MI->getDebugLoc(); 1210223017Sdim 1211223017Sdim unsigned Dest = MI->getOperand(0).getReg(); 1212223017Sdim unsigned Ptr = MI->getOperand(1).getReg(); 1213226890Sdim unsigned CmpVal = MI->getOperand(2).getReg(); 1214226890Sdim unsigned NewVal = MI->getOperand(3).getReg(); 1215223017Sdim 1216226890Sdim unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1217226890Sdim unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1218223017Sdim unsigned Mask = RegInfo.createVirtualRegister(RC); 1219223017Sdim unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1220226890Sdim unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1221226890Sdim unsigned OldVal = RegInfo.createVirtualRegister(RC); 1222226890Sdim unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1223226890Sdim unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1224226890Sdim unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1225226890Sdim unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1226226890Sdim unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1227226890Sdim unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1228226890Sdim unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1229226890Sdim unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1230226890Sdim unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1231226890Sdim unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1232226890Sdim unsigned SllRes = RegInfo.createVirtualRegister(RC); 1233226890Sdim unsigned Success = RegInfo.createVirtualRegister(RC); 1234223017Sdim 1235223017Sdim // insert new blocks after the current block 1236223017Sdim const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1237223017Sdim MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1238223017Sdim MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1239226890Sdim MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1240223017Sdim MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1241223017Sdim MachineFunction::iterator It = BB; 1242223017Sdim ++It; 1243223017Sdim MF->insert(It, loop1MBB); 1244223017Sdim MF->insert(It, loop2MBB); 1245226890Sdim MF->insert(It, sinkMBB); 1246223017Sdim MF->insert(It, exitMBB); 1247223017Sdim 1248223017Sdim // Transfer the remainder of BB and its successor edges to exitMBB. 1249223017Sdim exitMBB->splice(exitMBB->begin(), BB, 1250235633Sdim llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1251223017Sdim exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1252223017Sdim 1253226890Sdim BB->addSuccessor(loop1MBB); 1254226890Sdim loop1MBB->addSuccessor(sinkMBB); 1255226890Sdim loop1MBB->addSuccessor(loop2MBB); 1256226890Sdim loop2MBB->addSuccessor(loop1MBB); 1257226890Sdim loop2MBB->addSuccessor(sinkMBB); 1258226890Sdim sinkMBB->addSuccessor(exitMBB); 1259226890Sdim 1260226890Sdim // FIXME: computation of newval2 can be moved to loop2MBB. 1261223017Sdim // thisMBB: 1262226890Sdim // addiu masklsb2,$0,-4 # 0xfffffffc 1263226890Sdim // and alignedaddr,ptr,masklsb2 1264226890Sdim // andi ptrlsb2,ptr,3 1265226890Sdim // sll shiftamt,ptrlsb2,3 1266226890Sdim // ori maskupper,$0,255 # 0xff 1267226890Sdim // sll mask,maskupper,shiftamt 1268223017Sdim // nor mask2,$0,mask 1269226890Sdim // andi maskedcmpval,cmpval,255 1270226890Sdim // sll shiftedcmpval,maskedcmpval,shiftamt 1271226890Sdim // andi maskednewval,newval,255 1272226890Sdim // sll shiftednewval,maskednewval,shiftamt 1273223017Sdim int64_t MaskImm = (Size == 1) ? 255 : 65535; 1274252723Sdim BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1275226890Sdim .addReg(Mips::ZERO).addImm(-4); 1276252723Sdim BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1277226890Sdim .addReg(Ptr).addReg(MaskLSB2); 1278252723Sdim BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1279263509Sdim if (Subtarget->isLittle()) { 1280263509Sdim BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1281263509Sdim } else { 1282263509Sdim unsigned Off = RegInfo.createVirtualRegister(RC); 1283263509Sdim BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1284263509Sdim .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1285263509Sdim BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1286263509Sdim } 1287252723Sdim BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1288226890Sdim .addReg(Mips::ZERO).addImm(MaskImm); 1289252723Sdim BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1290263509Sdim .addReg(MaskUpper).addReg(ShiftAmt); 1291252723Sdim BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1292252723Sdim BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1293226890Sdim .addReg(CmpVal).addImm(MaskImm); 1294252723Sdim BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1295263509Sdim .addReg(MaskedCmpVal).addReg(ShiftAmt); 1296252723Sdim BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1297226890Sdim .addReg(NewVal).addImm(MaskImm); 1298252723Sdim BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1299263509Sdim .addReg(MaskedNewVal).addReg(ShiftAmt); 1300223017Sdim 1301223017Sdim // loop1MBB: 1302226890Sdim // ll oldval,0(alginedaddr) 1303226890Sdim // and maskedoldval0,oldval,mask 1304226890Sdim // bne maskedoldval0,shiftedcmpval,sinkMBB 1305223017Sdim BB = loop1MBB; 1306263509Sdim BuildMI(BB, DL, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1307252723Sdim BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1308226890Sdim .addReg(OldVal).addReg(Mask); 1309252723Sdim BuildMI(BB, DL, TII->get(Mips::BNE)) 1310226890Sdim .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1311223017Sdim 1312223017Sdim // loop2MBB: 1313226890Sdim // and maskedoldval1,oldval,mask2 1314226890Sdim // or storeval,maskedoldval1,shiftednewval 1315226890Sdim // sc success,storeval,0(alignedaddr) 1316226890Sdim // beq success,$0,loop1MBB 1317223017Sdim BB = loop2MBB; 1318252723Sdim BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1319226890Sdim .addReg(OldVal).addReg(Mask2); 1320252723Sdim BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1321226890Sdim .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1322263509Sdim BuildMI(BB, DL, TII->get(Mips::SC), Success) 1323226890Sdim .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1324252723Sdim BuildMI(BB, DL, TII->get(Mips::BEQ)) 1325226890Sdim .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1326223017Sdim 1327226890Sdim // sinkMBB: 1328226890Sdim // srl srlres,maskedoldval0,shiftamt 1329226890Sdim // sll sllres,srlres,24 1330226890Sdim // sra dest,sllres,24 1331226890Sdim BB = sinkMBB; 1332223017Sdim int64_t ShiftImm = (Size == 1) ? 24 : 16; 1333223017Sdim 1334252723Sdim BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1335263509Sdim .addReg(MaskedOldVal0).addReg(ShiftAmt); 1336252723Sdim BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1337226890Sdim .addReg(SrlRes).addImm(ShiftImm); 1338252723Sdim BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1339226890Sdim .addReg(SllRes).addImm(ShiftImm); 1340226890Sdim 1341223017Sdim MI->eraseFromParent(); // The instruction is gone now. 1342223017Sdim 1343226890Sdim return exitMBB; 1344223017Sdim} 1345223017Sdim 1346223017Sdim//===----------------------------------------------------------------------===// 1347223017Sdim// Misc Lower Operation implementation 1348223017Sdim//===----------------------------------------------------------------------===// 1349252723SdimSDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1350252723Sdim SDValue Chain = Op.getOperand(0); 1351252723Sdim SDValue Table = Op.getOperand(1); 1352252723Sdim SDValue Index = Op.getOperand(2); 1353263509Sdim SDLoc DL(Op); 1354252723Sdim EVT PTy = getPointerTy(); 1355252723Sdim unsigned EntrySize = 1356252723Sdim DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout()); 1357252723Sdim 1358252723Sdim Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1359252723Sdim DAG.getConstant(EntrySize, PTy)); 1360252723Sdim SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1361252723Sdim 1362252723Sdim EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1363252723Sdim Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1364252723Sdim MachinePointerInfo::getJumpTable(), MemVT, false, false, 1365252723Sdim 0); 1366252723Sdim Chain = Addr.getValue(1); 1367252723Sdim 1368252723Sdim if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) { 1369252723Sdim // For PIC, the sequence is: 1370252723Sdim // BRIND(load(Jumptable + index) + RelocBase) 1371252723Sdim // RelocBase can be JumpTable, GOT or some sort of global base. 1372252723Sdim Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1373252723Sdim getPICJumpTableRelocBase(Table, DAG)); 1374252723Sdim } 1375252723Sdim 1376252723Sdim return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1377252723Sdim} 1378252723Sdim 1379263509SdimSDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 1380218893Sdim // The first operand is the chain, the second is the condition, the third is 1381193323Sed // the block to branch to if the condition is true. 1382193323Sed SDValue Chain = Op.getOperand(0); 1383193323Sed SDValue Dest = Op.getOperand(2); 1384263509Sdim SDLoc DL(Op); 1385193323Sed 1386252723Sdim SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1387221345Sdim 1388221345Sdim // Return if flag is not set by a floating point comparison. 1389221345Sdim if (CondRes.getOpcode() != MipsISD::FPCmp) 1390193323Sed return Op; 1391218893Sdim 1392193323Sed SDValue CCNode = CondRes.getOperand(2); 1393193323Sed Mips::CondCode CC = 1394193323Sed (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1395252723Sdim unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1396252723Sdim SDValue BrCode = DAG.getConstant(Opc, MVT::i32); 1397263509Sdim SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1398252723Sdim return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1399263509Sdim FCC0, Dest, CondRes); 1400193323Sed} 1401193323Sed 1402193323SedSDValue MipsTargetLowering:: 1403252723SdimlowerSELECT(SDValue Op, SelectionDAG &DAG) const 1404193323Sed{ 1405252723Sdim SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1406193323Sed 1407221345Sdim // Return if flag is not set by a floating point comparison. 1408221345Sdim if (Cond.getOpcode() != MipsISD::FPCmp) 1409221345Sdim return Op; 1410193323Sed 1411252723Sdim return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1412263509Sdim SDLoc(Op)); 1413193323Sed} 1414193323Sed 1415245431SdimSDValue MipsTargetLowering:: 1416252723SdimlowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1417245431Sdim{ 1418263509Sdim SDLoc DL(Op); 1419245431Sdim EVT Ty = Op.getOperand(0).getValueType(); 1420263509Sdim SDValue Cond = DAG.getNode(ISD::SETCC, DL, 1421263509Sdim getSetCCResultType(*DAG.getContext(), Ty), 1422245431Sdim Op.getOperand(0), Op.getOperand(1), 1423245431Sdim Op.getOperand(4)); 1424245431Sdim 1425245431Sdim return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1426245431Sdim Op.getOperand(3)); 1427245431Sdim} 1428245431Sdim 1429252723SdimSDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1430252723Sdim SDValue Cond = createFPCmp(DAG, Op); 1431235633Sdim 1432235633Sdim assert(Cond.getOpcode() == MipsISD::FPCmp && 1433235633Sdim "Floating point operand expected."); 1434235633Sdim 1435235633Sdim SDValue True = DAG.getConstant(1, MVT::i32); 1436235633Sdim SDValue False = DAG.getConstant(0, MVT::i32); 1437235633Sdim 1438263509Sdim return createCMovFP(DAG, Cond, True, False, SDLoc(Op)); 1439235633Sdim} 1440235633Sdim 1441252723SdimSDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1442207618Srdivacky SelectionDAG &DAG) const { 1443193323Sed // FIXME there isn't actually debug info here 1444263509Sdim SDLoc DL(Op); 1445263509Sdim EVT Ty = Op.getValueType(); 1446263509Sdim GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); 1447263509Sdim const GlobalValue *GV = N->getGlobal(); 1448193323Sed 1449226890Sdim if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1450245431Sdim const MipsTargetObjectFile &TLOF = 1451245431Sdim (const MipsTargetObjectFile&)getObjFileLowering(); 1452218893Sdim 1453193323Sed // %gp_rel relocation 1454218893Sdim if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1455252723Sdim SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0, 1456198090Srdivacky MipsII::MO_GPREL); 1457252723Sdim SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL, 1458245431Sdim DAG.getVTList(MVT::i32), &GA, 1); 1459245431Sdim SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1460252723Sdim return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode); 1461193323Sed } 1462245431Sdim 1463193323Sed // %hi/%lo relocation 1464263509Sdim return getAddrNonPIC(N, Ty, DAG); 1465193323Sed } 1466193323Sed 1467245431Sdim if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 1468263509Sdim return getAddrLocal(N, Ty, DAG, HasMips64); 1469245431Sdim 1470245431Sdim if (LargeGOT) 1471263509Sdim return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16, 1472263509Sdim MipsII::MO_GOT_LO16, DAG.getEntryNode(), 1473263509Sdim MachinePointerInfo::getGOT()); 1474245431Sdim 1475263509Sdim return getAddrGlobal(N, Ty, DAG, 1476263509Sdim HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16, 1477263509Sdim DAG.getEntryNode(), MachinePointerInfo::getGOT()); 1478193323Sed} 1479193323Sed 1480252723SdimSDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1481221345Sdim SelectionDAG &DAG) const { 1482263509Sdim BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); 1483263509Sdim EVT Ty = Op.getValueType(); 1484263509Sdim 1485245431Sdim if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1486263509Sdim return getAddrNonPIC(N, Ty, DAG); 1487221345Sdim 1488263509Sdim return getAddrLocal(N, Ty, DAG, HasMips64); 1489221345Sdim} 1490221345Sdim 1491193323SedSDValue MipsTargetLowering:: 1492252723SdimlowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1493193323Sed{ 1494235633Sdim // If the relocation model is PIC, use the General Dynamic TLS Model or 1495235633Sdim // Local Dynamic TLS model, otherwise use the Initial Exec or 1496235633Sdim // Local Exec TLS Model. 1497223017Sdim 1498223017Sdim GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1499263509Sdim SDLoc DL(GA); 1500223017Sdim const GlobalValue *GV = GA->getGlobal(); 1501223017Sdim EVT PtrVT = getPointerTy(); 1502223017Sdim 1503245431Sdim TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1504245431Sdim 1505245431Sdim if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1506245431Sdim // General Dynamic and Local Dynamic TLS Model. 1507245431Sdim unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1508245431Sdim : MipsII::MO_TLSGD; 1509245431Sdim 1510252723Sdim SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1511252723Sdim SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1512252723Sdim getGlobalReg(DAG, PtrVT), TGA); 1513235633Sdim unsigned PtrSize = PtrVT.getSizeInBits(); 1514235633Sdim IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1515223017Sdim 1516235633Sdim SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1517235633Sdim 1518223017Sdim ArgListTy Args; 1519223017Sdim ArgListEntry Entry; 1520223017Sdim Entry.Node = Argument; 1521235633Sdim Entry.Ty = PtrTy; 1522223017Sdim Args.push_back(Entry); 1523235633Sdim 1524245431Sdim TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1525235633Sdim false, false, false, false, 0, CallingConv::C, 1526252723Sdim /*IsTailCall=*/false, /*doesNotRet=*/false, 1527235633Sdim /*isReturnValueUsed=*/true, 1528252723Sdim TlsGetAddr, Args, DAG, DL); 1529245431Sdim std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1530223017Sdim 1531235633Sdim SDValue Ret = CallResult.first; 1532235633Sdim 1533245431Sdim if (model != TLSModel::LocalDynamic) 1534235633Sdim return Ret; 1535235633Sdim 1536252723Sdim SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1537235633Sdim MipsII::MO_DTPREL_HI); 1538252723Sdim SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1539252723Sdim SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1540235633Sdim MipsII::MO_DTPREL_LO); 1541252723Sdim SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1542252723Sdim SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1543252723Sdim return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1544224145Sdim } 1545224145Sdim 1546224145Sdim SDValue Offset; 1547245431Sdim if (model == TLSModel::InitialExec) { 1548224145Sdim // Initial Exec TLS Model 1549252723Sdim SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1550224145Sdim MipsII::MO_GOTTPREL); 1551252723Sdim TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1552235633Sdim TGA); 1553252723Sdim Offset = DAG.getLoad(PtrVT, DL, 1554224145Sdim DAG.getEntryNode(), TGA, MachinePointerInfo(), 1555235633Sdim false, false, false, 0); 1556223017Sdim } else { 1557224145Sdim // Local Exec TLS Model 1558245431Sdim assert(model == TLSModel::LocalExec); 1559252723Sdim SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1560224145Sdim MipsII::MO_TPREL_HI); 1561252723Sdim SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1562224145Sdim MipsII::MO_TPREL_LO); 1563252723Sdim SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1564252723Sdim SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1565252723Sdim Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1566224145Sdim } 1567223017Sdim 1568252723Sdim SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1569252723Sdim return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1570193323Sed} 1571193323Sed 1572193323SedSDValue MipsTargetLowering:: 1573252723SdimlowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1574193323Sed{ 1575263509Sdim JumpTableSDNode *N = cast<JumpTableSDNode>(Op); 1576263509Sdim EVT Ty = Op.getValueType(); 1577263509Sdim 1578245431Sdim if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1579263509Sdim return getAddrNonPIC(N, Ty, DAG); 1580193323Sed 1581263509Sdim return getAddrLocal(N, Ty, DAG, HasMips64); 1582193323Sed} 1583193323Sed 1584193323SedSDValue MipsTargetLowering:: 1585252723SdimlowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1586193323Sed{ 1587193323Sed // gp_rel relocation 1588218893Sdim // FIXME: we should reference the constant pool using small data sections, 1589221345Sdim // but the asm printer currently doesn't support this feature without 1590218893Sdim // hacking it. This feature should come soon so we can uncomment the 1591193323Sed // stuff below. 1592198090Srdivacky //if (IsInSmallSection(C->getType())) { 1593193323Sed // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1594193323Sed // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1595218893Sdim // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1596263509Sdim ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1597263509Sdim EVT Ty = Op.getValueType(); 1598199989Srdivacky 1599245431Sdim if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1600263509Sdim return getAddrNonPIC(N, Ty, DAG); 1601193323Sed 1602263509Sdim return getAddrLocal(N, Ty, DAG, HasMips64); 1603193323Sed} 1604193323Sed 1605252723SdimSDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1606207618Srdivacky MachineFunction &MF = DAG.getMachineFunction(); 1607207618Srdivacky MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1608207618Srdivacky 1609263509Sdim SDLoc DL(Op); 1610207618Srdivacky SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1611207618Srdivacky getPointerTy()); 1612203954Srdivacky 1613203954Srdivacky // vastart just stores the address of the VarArgsFrameIndex slot into the 1614203954Srdivacky // memory location argument. 1615203954Srdivacky const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1616252723Sdim return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1617235633Sdim MachinePointerInfo(SV), false, false, 0); 1618203954Srdivacky} 1619203954Srdivacky 1620263509Sdimstatic SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, 1621263509Sdim bool HasExtractInsert) { 1622235633Sdim EVT TyX = Op.getOperand(0).getValueType(); 1623235633Sdim EVT TyY = Op.getOperand(1).getValueType(); 1624235633Sdim SDValue Const1 = DAG.getConstant(1, MVT::i32); 1625235633Sdim SDValue Const31 = DAG.getConstant(31, MVT::i32); 1626263509Sdim SDLoc DL(Op); 1627235633Sdim SDValue Res; 1628235633Sdim 1629235633Sdim // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1630235633Sdim // to i32. 1631235633Sdim SDValue X = (TyX == MVT::f32) ? 1632235633Sdim DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1633235633Sdim DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1634235633Sdim Const1); 1635235633Sdim SDValue Y = (TyY == MVT::f32) ? 1636235633Sdim DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1637235633Sdim DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1638235633Sdim Const1); 1639235633Sdim 1640263509Sdim if (HasExtractInsert) { 1641235633Sdim // ext E, Y, 31, 1 ; extract bit31 of Y 1642235633Sdim // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1643235633Sdim SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1644235633Sdim Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1645235633Sdim } else { 1646235633Sdim // sll SllX, X, 1 1647235633Sdim // srl SrlX, SllX, 1 1648235633Sdim // srl SrlY, Y, 31 1649235633Sdim // sll SllY, SrlX, 31 1650235633Sdim // or Or, SrlX, SllY 1651235633Sdim SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1652235633Sdim SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1653235633Sdim SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1654235633Sdim SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1655235633Sdim Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1656235633Sdim } 1657235633Sdim 1658235633Sdim if (TyX == MVT::f32) 1659235633Sdim return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1660235633Sdim 1661235633Sdim SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1662235633Sdim Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1663235633Sdim return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1664223017Sdim} 1665223017Sdim 1666263509Sdimstatic SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, 1667263509Sdim bool HasExtractInsert) { 1668235633Sdim unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 1669235633Sdim unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 1670235633Sdim EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 1671235633Sdim SDValue Const1 = DAG.getConstant(1, MVT::i32); 1672263509Sdim SDLoc DL(Op); 1673223017Sdim 1674235633Sdim // Bitcast to integer nodes. 1675235633Sdim SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 1676235633Sdim SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 1677223017Sdim 1678263509Sdim if (HasExtractInsert) { 1679235633Sdim // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 1680235633Sdim // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 1681235633Sdim SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 1682235633Sdim DAG.getConstant(WidthY - 1, MVT::i32), Const1); 1683223017Sdim 1684235633Sdim if (WidthX > WidthY) 1685235633Sdim E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 1686235633Sdim else if (WidthY > WidthX) 1687235633Sdim E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 1688223017Sdim 1689235633Sdim SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1690235633Sdim DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 1691235633Sdim return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 1692235633Sdim } 1693235633Sdim 1694235633Sdim // (d)sll SllX, X, 1 1695235633Sdim // (d)srl SrlX, SllX, 1 1696235633Sdim // (d)srl SrlY, Y, width(Y)-1 1697235633Sdim // (d)sll SllY, SrlX, width(Y)-1 1698235633Sdim // or Or, SrlX, SllY 1699235633Sdim SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1700235633Sdim SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1701235633Sdim SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1702235633Sdim DAG.getConstant(WidthY - 1, MVT::i32)); 1703235633Sdim 1704235633Sdim if (WidthX > WidthY) 1705235633Sdim SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 1706235633Sdim else if (WidthY > WidthX) 1707235633Sdim SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 1708235633Sdim 1709235633Sdim SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1710235633Sdim DAG.getConstant(WidthX - 1, MVT::i32)); 1711235633Sdim SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 1712235633Sdim return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 1713223017Sdim} 1714223017Sdim 1715235633SdimSDValue 1716252723SdimMipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1717235633Sdim if (Subtarget->hasMips64()) 1718263509Sdim return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasExtractInsert()); 1719223017Sdim 1720263509Sdim return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasExtractInsert()); 1721235633Sdim} 1722223017Sdim 1723263509Sdimstatic SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, 1724263509Sdim bool HasExtractInsert) { 1725235633Sdim SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1726263509Sdim SDLoc DL(Op); 1727235633Sdim 1728235633Sdim // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1729235633Sdim // to i32. 1730235633Sdim SDValue X = (Op.getValueType() == MVT::f32) ? 1731235633Sdim DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1732235633Sdim DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1733235633Sdim Const1); 1734235633Sdim 1735235633Sdim // Clear MSB. 1736263509Sdim if (HasExtractInsert) 1737235633Sdim Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 1738235633Sdim DAG.getRegister(Mips::ZERO, MVT::i32), 1739235633Sdim DAG.getConstant(31, MVT::i32), Const1, X); 1740235633Sdim else { 1741235633Sdim SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1742235633Sdim Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1743235633Sdim } 1744235633Sdim 1745235633Sdim if (Op.getValueType() == MVT::f32) 1746235633Sdim return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 1747235633Sdim 1748235633Sdim SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1749235633Sdim Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1750235633Sdim return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1751223017Sdim} 1752223017Sdim 1753263509Sdimstatic SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, 1754263509Sdim bool HasExtractInsert) { 1755235633Sdim SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1756263509Sdim SDLoc DL(Op); 1757235633Sdim 1758235633Sdim // Bitcast to integer node. 1759235633Sdim SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 1760235633Sdim 1761235633Sdim // Clear MSB. 1762263509Sdim if (HasExtractInsert) 1763235633Sdim Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 1764235633Sdim DAG.getRegister(Mips::ZERO_64, MVT::i64), 1765235633Sdim DAG.getConstant(63, MVT::i32), Const1, X); 1766235633Sdim else { 1767235633Sdim SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 1768235633Sdim Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 1769235633Sdim } 1770235633Sdim 1771235633Sdim return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 1772235633Sdim} 1773235633Sdim 1774235633SdimSDValue 1775252723SdimMipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { 1776235633Sdim if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 1777263509Sdim return lowerFABS64(Op, DAG, Subtarget->hasExtractInsert()); 1778235633Sdim 1779263509Sdim return lowerFABS32(Op, DAG, Subtarget->hasExtractInsert()); 1780235633Sdim} 1781235633Sdim 1782223017SdimSDValue MipsTargetLowering:: 1783252723SdimlowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1784224145Sdim // check the depth 1785224145Sdim assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1786223017Sdim "Frame address can only be determined for current frame."); 1787223017Sdim 1788223017Sdim MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1789223017Sdim MFI->setFrameAddressIsTaken(true); 1790223017Sdim EVT VT = Op.getValueType(); 1791263509Sdim SDLoc DL(Op); 1792252723Sdim SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, 1793235633Sdim IsN64 ? Mips::FP_64 : Mips::FP, VT); 1794223017Sdim return FrameAddr; 1795223017Sdim} 1796223017Sdim 1797252723SdimSDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 1798245431Sdim SelectionDAG &DAG) const { 1799245431Sdim // check the depth 1800245431Sdim assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1801245431Sdim "Return address can be determined only for current frame."); 1802245431Sdim 1803245431Sdim MachineFunction &MF = DAG.getMachineFunction(); 1804245431Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 1805252723Sdim MVT VT = Op.getSimpleValueType(); 1806245431Sdim unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 1807245431Sdim MFI->setReturnAddressIsTaken(true); 1808245431Sdim 1809245431Sdim // Return RA, which contains the return address. Mark it an implicit live-in. 1810245431Sdim unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 1811263509Sdim return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 1812245431Sdim} 1813245431Sdim 1814252723Sdim// An EH_RETURN is the result of lowering llvm.eh.return which in turn is 1815252723Sdim// generated from __builtin_eh_return (offset, handler) 1816252723Sdim// The effect of this is to adjust the stack pointer by "offset" 1817252723Sdim// and then branch to "handler". 1818252723SdimSDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 1819252723Sdim const { 1820252723Sdim MachineFunction &MF = DAG.getMachineFunction(); 1821252723Sdim MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1822252723Sdim 1823252723Sdim MipsFI->setCallsEhReturn(); 1824252723Sdim SDValue Chain = Op.getOperand(0); 1825252723Sdim SDValue Offset = Op.getOperand(1); 1826252723Sdim SDValue Handler = Op.getOperand(2); 1827263509Sdim SDLoc DL(Op); 1828252723Sdim EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 1829252723Sdim 1830252723Sdim // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 1831252723Sdim // EH_RETURN nodes, so that instructions are emitted back-to-back. 1832252723Sdim unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1; 1833252723Sdim unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0; 1834252723Sdim Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 1835252723Sdim Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 1836252723Sdim return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 1837252723Sdim DAG.getRegister(OffsetReg, Ty), 1838252723Sdim DAG.getRegister(AddrReg, getPointerTy()), 1839252723Sdim Chain.getValue(1)); 1840226890Sdim} 1841226890Sdim 1842252723SdimSDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 1843245431Sdim SelectionDAG &DAG) const { 1844226890Sdim // FIXME: Need pseudo-fence for 'singlethread' fences 1845226890Sdim // FIXME: Set SType for weaker fences where supported/appropriate. 1846226890Sdim unsigned SType = 0; 1847263509Sdim SDLoc DL(Op); 1848252723Sdim return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 1849226890Sdim DAG.getConstant(SType, MVT::i32)); 1850226890Sdim} 1851226890Sdim 1852252723SdimSDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 1853245431Sdim SelectionDAG &DAG) const { 1854263509Sdim SDLoc DL(Op); 1855245431Sdim SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1856245431Sdim SDValue Shamt = Op.getOperand(2); 1857245431Sdim 1858245431Sdim // if shamt < 32: 1859245431Sdim // lo = (shl lo, shamt) 1860245431Sdim // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 1861245431Sdim // else: 1862245431Sdim // lo = 0 1863245431Sdim // hi = (shl lo, shamt[4:0]) 1864245431Sdim SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1865245431Sdim DAG.getConstant(-1, MVT::i32)); 1866245431Sdim SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 1867245431Sdim DAG.getConstant(1, MVT::i32)); 1868245431Sdim SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 1869245431Sdim Not); 1870245431Sdim SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 1871245431Sdim SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1872245431Sdim SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 1873245431Sdim SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1874245431Sdim DAG.getConstant(0x20, MVT::i32)); 1875245431Sdim Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1876245431Sdim DAG.getConstant(0, MVT::i32), ShiftLeftLo); 1877245431Sdim Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 1878245431Sdim 1879245431Sdim SDValue Ops[2] = {Lo, Hi}; 1880245431Sdim return DAG.getMergeValues(Ops, 2, DL); 1881245431Sdim} 1882245431Sdim 1883252723SdimSDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 1884245431Sdim bool IsSRA) const { 1885263509Sdim SDLoc DL(Op); 1886245431Sdim SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1887245431Sdim SDValue Shamt = Op.getOperand(2); 1888245431Sdim 1889245431Sdim // if shamt < 32: 1890245431Sdim // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 1891245431Sdim // if isSRA: 1892245431Sdim // hi = (sra hi, shamt) 1893245431Sdim // else: 1894245431Sdim // hi = (srl hi, shamt) 1895245431Sdim // else: 1896245431Sdim // if isSRA: 1897245431Sdim // lo = (sra hi, shamt[4:0]) 1898245431Sdim // hi = (sra hi, 31) 1899245431Sdim // else: 1900245431Sdim // lo = (srl hi, shamt[4:0]) 1901245431Sdim // hi = 0 1902245431Sdim SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1903245431Sdim DAG.getConstant(-1, MVT::i32)); 1904245431Sdim SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 1905245431Sdim DAG.getConstant(1, MVT::i32)); 1906245431Sdim SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 1907245431Sdim SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 1908245431Sdim SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1909245431Sdim SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 1910245431Sdim Hi, Shamt); 1911245431Sdim SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1912245431Sdim DAG.getConstant(0x20, MVT::i32)); 1913245431Sdim SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 1914245431Sdim DAG.getConstant(31, MVT::i32)); 1915245431Sdim Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 1916245431Sdim Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1917245431Sdim IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 1918245431Sdim ShiftRightHi); 1919245431Sdim 1920245431Sdim SDValue Ops[2] = {Lo, Hi}; 1921245431Sdim return DAG.getMergeValues(Ops, 2, DL); 1922245431Sdim} 1923245431Sdim 1924252723Sdimstatic SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 1925245431Sdim SDValue Chain, SDValue Src, unsigned Offset) { 1926245431Sdim SDValue Ptr = LD->getBasePtr(); 1927245431Sdim EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 1928245431Sdim EVT BasePtrVT = Ptr.getValueType(); 1929263509Sdim SDLoc DL(LD); 1930245431Sdim SDVTList VTList = DAG.getVTList(VT, MVT::Other); 1931245431Sdim 1932245431Sdim if (Offset) 1933245431Sdim Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 1934245431Sdim DAG.getConstant(Offset, BasePtrVT)); 1935245431Sdim 1936245431Sdim SDValue Ops[] = { Chain, Ptr, Src }; 1937245431Sdim return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 1938245431Sdim LD->getMemOperand()); 1939245431Sdim} 1940245431Sdim 1941245431Sdim// Expand an unaligned 32 or 64-bit integer load node. 1942252723SdimSDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 1943245431Sdim LoadSDNode *LD = cast<LoadSDNode>(Op); 1944245431Sdim EVT MemVT = LD->getMemoryVT(); 1945245431Sdim 1946245431Sdim // Return if load is aligned or if MemVT is neither i32 nor i64. 1947245431Sdim if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 1948245431Sdim ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 1949245431Sdim return SDValue(); 1950245431Sdim 1951245431Sdim bool IsLittle = Subtarget->isLittle(); 1952245431Sdim EVT VT = Op.getValueType(); 1953245431Sdim ISD::LoadExtType ExtType = LD->getExtensionType(); 1954245431Sdim SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 1955245431Sdim 1956245431Sdim assert((VT == MVT::i32) || (VT == MVT::i64)); 1957245431Sdim 1958245431Sdim // Expand 1959245431Sdim // (set dst, (i64 (load baseptr))) 1960245431Sdim // to 1961245431Sdim // (set tmp, (ldl (add baseptr, 7), undef)) 1962245431Sdim // (set dst, (ldr baseptr, tmp)) 1963245431Sdim if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 1964252723Sdim SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 1965245431Sdim IsLittle ? 7 : 0); 1966252723Sdim return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 1967245431Sdim IsLittle ? 0 : 7); 1968245431Sdim } 1969245431Sdim 1970252723Sdim SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 1971245431Sdim IsLittle ? 3 : 0); 1972252723Sdim SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 1973245431Sdim IsLittle ? 0 : 3); 1974245431Sdim 1975245431Sdim // Expand 1976245431Sdim // (set dst, (i32 (load baseptr))) or 1977245431Sdim // (set dst, (i64 (sextload baseptr))) or 1978245431Sdim // (set dst, (i64 (extload baseptr))) 1979245431Sdim // to 1980245431Sdim // (set tmp, (lwl (add baseptr, 3), undef)) 1981245431Sdim // (set dst, (lwr baseptr, tmp)) 1982245431Sdim if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 1983245431Sdim (ExtType == ISD::EXTLOAD)) 1984245431Sdim return LWR; 1985245431Sdim 1986245431Sdim assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 1987245431Sdim 1988245431Sdim // Expand 1989245431Sdim // (set dst, (i64 (zextload baseptr))) 1990245431Sdim // to 1991245431Sdim // (set tmp0, (lwl (add baseptr, 3), undef)) 1992245431Sdim // (set tmp1, (lwr baseptr, tmp0)) 1993245431Sdim // (set tmp2, (shl tmp1, 32)) 1994245431Sdim // (set dst, (srl tmp2, 32)) 1995263509Sdim SDLoc DL(LD); 1996245431Sdim SDValue Const32 = DAG.getConstant(32, MVT::i32); 1997245431Sdim SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 1998245431Sdim SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 1999245431Sdim SDValue Ops[] = { SRL, LWR.getValue(1) }; 2000245431Sdim return DAG.getMergeValues(Ops, 2, DL); 2001245431Sdim} 2002245431Sdim 2003252723Sdimstatic SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2004245431Sdim SDValue Chain, unsigned Offset) { 2005245431Sdim SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2006245431Sdim EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2007263509Sdim SDLoc DL(SD); 2008245431Sdim SDVTList VTList = DAG.getVTList(MVT::Other); 2009245431Sdim 2010245431Sdim if (Offset) 2011245431Sdim Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2012245431Sdim DAG.getConstant(Offset, BasePtrVT)); 2013245431Sdim 2014245431Sdim SDValue Ops[] = { Chain, Value, Ptr }; 2015245431Sdim return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2016245431Sdim SD->getMemOperand()); 2017245431Sdim} 2018245431Sdim 2019245431Sdim// Expand an unaligned 32 or 64-bit integer store node. 2020263509Sdimstatic SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2021263509Sdim bool IsLittle) { 2022245431Sdim SDValue Value = SD->getValue(), Chain = SD->getChain(); 2023245431Sdim EVT VT = Value.getValueType(); 2024245431Sdim 2025245431Sdim // Expand 2026245431Sdim // (store val, baseptr) or 2027245431Sdim // (truncstore val, baseptr) 2028245431Sdim // to 2029245431Sdim // (swl val, (add baseptr, 3)) 2030245431Sdim // (swr val, baseptr) 2031245431Sdim if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2032252723Sdim SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2033245431Sdim IsLittle ? 3 : 0); 2034252723Sdim return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2035245431Sdim } 2036245431Sdim 2037245431Sdim assert(VT == MVT::i64); 2038245431Sdim 2039245431Sdim // Expand 2040245431Sdim // (store val, baseptr) 2041245431Sdim // to 2042245431Sdim // (sdl val, (add baseptr, 7)) 2043245431Sdim // (sdr val, baseptr) 2044252723Sdim SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2045252723Sdim return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2046245431Sdim} 2047245431Sdim 2048263509Sdim// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2049263509Sdimstatic SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2050263509Sdim SDValue Val = SD->getValue(); 2051263509Sdim 2052263509Sdim if (Val.getOpcode() != ISD::FP_TO_SINT) 2053263509Sdim return SDValue(); 2054263509Sdim 2055263509Sdim EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2056263509Sdim SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2057263509Sdim Val.getOperand(0)); 2058263509Sdim 2059263509Sdim return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2060263509Sdim SD->getPointerInfo(), SD->isVolatile(), 2061263509Sdim SD->isNonTemporal(), SD->getAlignment()); 2062263509Sdim} 2063263509Sdim 2064263509SdimSDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2065263509Sdim StoreSDNode *SD = cast<StoreSDNode>(Op); 2066263509Sdim EVT MemVT = SD->getMemoryVT(); 2067263509Sdim 2068263509Sdim // Lower unaligned integer stores. 2069263509Sdim if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2070263509Sdim ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2071263509Sdim return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle()); 2072263509Sdim 2073263509Sdim return lowerFP_TO_SINT_STORE(SD, DAG); 2074263509Sdim} 2075263509Sdim 2076252723SdimSDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const { 2077245431Sdim if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 2078245431Sdim || cast<ConstantSDNode> 2079245431Sdim (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 2080245431Sdim || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 2081245431Sdim return SDValue(); 2082245431Sdim 2083245431Sdim // The pattern 2084245431Sdim // (add (frameaddr 0), (frame_to_args_offset)) 2085245431Sdim // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 2086245431Sdim // (add FrameObject, 0) 2087245431Sdim // where FrameObject is a fixed StackObject with offset 0 which points to 2088245431Sdim // the old stack pointer. 2089245431Sdim MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2090245431Sdim EVT ValTy = Op->getValueType(0); 2091245431Sdim int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2092245431Sdim SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 2093263509Sdim return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr, 2094245431Sdim DAG.getConstant(0, ValTy)); 2095245431Sdim} 2096245431Sdim 2097263509SdimSDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2098263509Sdim SelectionDAG &DAG) const { 2099263509Sdim EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2100263509Sdim SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2101263509Sdim Op.getOperand(0)); 2102263509Sdim return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2103263509Sdim} 2104263509Sdim 2105193323Sed//===----------------------------------------------------------------------===// 2106193323Sed// Calling Convention Implementation 2107193323Sed//===----------------------------------------------------------------------===// 2108193323Sed 2109193323Sed//===----------------------------------------------------------------------===// 2110218893Sdim// TODO: Implement a generic logic using tblgen that can support this. 2111193323Sed// Mips O32 ABI rules: 2112193323Sed// --- 2113193323Sed// i32 - Passed in A0, A1, A2, A3 and stack 2114218893Sdim// f32 - Only passed in f32 registers if no int reg has been used yet to hold 2115193323Sed// an argument. Otherwise, passed in A1, A2, A3 and stack. 2116218893Sdim// f64 - Only passed in two aliased f32 registers if no int reg has been used 2117218893Sdim// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2118193323Sed// not used, it must be shadowed. If only A3 is avaiable, shadow it and 2119193323Sed// go to stack. 2120223017Sdim// 2121223017Sdim// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2122193323Sed//===----------------------------------------------------------------------===// 2123193323Sed 2124263509Sdimstatic bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, 2125263509Sdim CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, 2126263509Sdim CCState &State, const uint16_t *F64Regs) { 2127193323Sed 2128263509Sdim static const unsigned IntRegsSize = 4, FloatRegsSize = 2; 2129193323Sed 2130263509Sdim static const uint16_t IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; 2131263509Sdim static const uint16_t F32Regs[] = { Mips::F12, Mips::F14 }; 2132193323Sed 2133245431Sdim // Do not process byval args here. 2134245431Sdim if (ArgFlags.isByVal()) 2135245431Sdim return true; 2136193323Sed 2137203954Srdivacky // Promote i8 and i16 2138203954Srdivacky if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2139203954Srdivacky LocVT = MVT::i32; 2140203954Srdivacky if (ArgFlags.isSExt()) 2141203954Srdivacky LocInfo = CCValAssign::SExt; 2142203954Srdivacky else if (ArgFlags.isZExt()) 2143203954Srdivacky LocInfo = CCValAssign::ZExt; 2144203954Srdivacky else 2145203954Srdivacky LocInfo = CCValAssign::AExt; 2146203954Srdivacky } 2147203954Srdivacky 2148221345Sdim unsigned Reg; 2149221345Sdim 2150223017Sdim // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2151223017Sdim // is true: function is vararg, argument is 3rd or higher, there is previous 2152223017Sdim // argument which is not f32 or f64. 2153223017Sdim bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2154223017Sdim || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2155223017Sdim unsigned OrigAlign = ArgFlags.getOrigAlign(); 2156223017Sdim bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2157223017Sdim 2158223017Sdim if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2159221345Sdim Reg = State.AllocateReg(IntRegs, IntRegsSize); 2160223017Sdim // If this is the first part of an i64 arg, 2161223017Sdim // the allocated register must be either A0 or A2. 2162223017Sdim if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2163223017Sdim Reg = State.AllocateReg(IntRegs, IntRegsSize); 2164221345Sdim LocVT = MVT::i32; 2165223017Sdim } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2166223017Sdim // Allocate int register and shadow next int register. If first 2167223017Sdim // available register is Mips::A1 or Mips::A3, shadow it too. 2168221345Sdim Reg = State.AllocateReg(IntRegs, IntRegsSize); 2169221345Sdim if (Reg == Mips::A1 || Reg == Mips::A3) 2170221345Sdim Reg = State.AllocateReg(IntRegs, IntRegsSize); 2171221345Sdim State.AllocateReg(IntRegs, IntRegsSize); 2172221345Sdim LocVT = MVT::i32; 2173223017Sdim } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2174223017Sdim // we are guaranteed to find an available float register 2175223017Sdim if (ValVT == MVT::f32) { 2176223017Sdim Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2177223017Sdim // Shadow int register 2178223017Sdim State.AllocateReg(IntRegs, IntRegsSize); 2179223017Sdim } else { 2180223017Sdim Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2181223017Sdim // Shadow int registers 2182223017Sdim unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2183223017Sdim if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2184223017Sdim State.AllocateReg(IntRegs, IntRegsSize); 2185223017Sdim State.AllocateReg(IntRegs, IntRegsSize); 2186223017Sdim } 2187221345Sdim } else 2188221345Sdim llvm_unreachable("Cannot handle this ValVT."); 2189203954Srdivacky 2190245431Sdim if (!Reg) { 2191245431Sdim unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2192245431Sdim OrigAlign); 2193221345Sdim State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2194245431Sdim } else 2195221345Sdim State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2196203954Srdivacky 2197245431Sdim return false; 2198203954Srdivacky} 2199203954Srdivacky 2200263509Sdimstatic bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, 2201263509Sdim MVT LocVT, CCValAssign::LocInfo LocInfo, 2202263509Sdim ISD::ArgFlagsTy ArgFlags, CCState &State) { 2203263509Sdim static const uint16_t F64Regs[] = { Mips::D6, Mips::D7 }; 2204263509Sdim 2205263509Sdim return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2206263509Sdim} 2207263509Sdim 2208263509Sdimstatic bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, 2209263509Sdim MVT LocVT, CCValAssign::LocInfo LocInfo, 2210263509Sdim ISD::ArgFlagsTy ArgFlags, CCState &State) { 2211263509Sdim static const uint16_t F64Regs[] = { Mips::D12_64, Mips::D14_64 }; 2212263509Sdim 2213263509Sdim return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); 2214263509Sdim} 2215263509Sdim 2216235633Sdim#include "MipsGenCallingConv.inc" 2217235633Sdim 2218193323Sed//===----------------------------------------------------------------------===// 2219198090Srdivacky// Call Calling Convention Implementation 2220193323Sed//===----------------------------------------------------------------------===// 2221193323Sed 2222226890Sdim// Return next O32 integer argument register. 2223226890Sdimstatic unsigned getNextIntArgReg(unsigned Reg) { 2224226890Sdim assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2225226890Sdim return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2226226890Sdim} 2227226890Sdim 2228245431SdimSDValue 2229245431SdimMipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2230263509Sdim SDValue Chain, SDValue Arg, SDLoc DL, 2231245431Sdim bool IsTailCall, SelectionDAG &DAG) const { 2232245431Sdim if (!IsTailCall) { 2233245431Sdim SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 2234245431Sdim DAG.getIntPtrConstant(Offset)); 2235245431Sdim return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2236245431Sdim false, 0); 2237235633Sdim } 2238235633Sdim 2239245431Sdim MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2240245431Sdim int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2241245431Sdim SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2242245431Sdim return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2243245431Sdim /*isVolatile=*/ true, false, 0); 2244235633Sdim} 2245235633Sdim 2246252723Sdimvoid MipsTargetLowering:: 2247252723SdimgetOpndList(SmallVectorImpl<SDValue> &Ops, 2248252723Sdim std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2249252723Sdim bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2250252723Sdim CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 2251252723Sdim // Insert node "GP copy globalreg" before call to function. 2252252723Sdim // 2253252723Sdim // R_MIPS_CALL* operators (emitted when non-internal functions are called 2254252723Sdim // in PIC mode) allow symbols to be resolved via lazy binding. 2255252723Sdim // The lazy binding stub requires GP to point to the GOT. 2256252723Sdim if (IsPICCall && !InternalLinkage) { 2257252723Sdim unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 2258252723Sdim EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2259252723Sdim RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2260252723Sdim } 2261252723Sdim 2262252723Sdim // Build a sequence of copy-to-reg nodes chained together with token 2263252723Sdim // chain and flag operands which copy the outgoing args into registers. 2264252723Sdim // The InFlag in necessary since all emitted instructions must be 2265252723Sdim // stuck together. 2266252723Sdim SDValue InFlag; 2267252723Sdim 2268252723Sdim for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2269252723Sdim Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2270252723Sdim RegsToPass[i].second, InFlag); 2271252723Sdim InFlag = Chain.getValue(1); 2272252723Sdim } 2273252723Sdim 2274252723Sdim // Add argument registers to the end of the list so that they are 2275252723Sdim // known live into the call. 2276252723Sdim for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2277252723Sdim Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2278252723Sdim RegsToPass[i].second.getValueType())); 2279252723Sdim 2280252723Sdim // Add a register mask operand representing the call-preserved registers. 2281252723Sdim const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2282252723Sdim const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); 2283252723Sdim assert(Mask && "Missing call preserved mask for calling convention"); 2284263509Sdim if (Subtarget->inMips16HardFloat()) { 2285263509Sdim if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2286263509Sdim llvm::StringRef Sym = G->getGlobal()->getName(); 2287263509Sdim Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2288263509Sdim if (F->hasFnAttribute("__Mips16RetHelper")) { 2289263509Sdim Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2290263509Sdim } 2291263509Sdim } 2292263509Sdim } 2293252723Sdim Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2294252723Sdim 2295252723Sdim if (InFlag.getNode()) 2296252723Sdim Ops.push_back(InFlag); 2297252723Sdim} 2298252723Sdim 2299198090Srdivacky/// LowerCall - functions arguments are copied from virtual regs to 2300193323Sed/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2301198090SrdivackySDValue 2302245431SdimMipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2303207618Srdivacky SmallVectorImpl<SDValue> &InVals) const { 2304245431Sdim SelectionDAG &DAG = CLI.DAG; 2305263509Sdim SDLoc DL = CLI.DL; 2306263509Sdim SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2307263509Sdim SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2308263509Sdim SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2309245431Sdim SDValue Chain = CLI.Chain; 2310245431Sdim SDValue Callee = CLI.Callee; 2311252723Sdim bool &IsTailCall = CLI.IsTailCall; 2312245431Sdim CallingConv::ID CallConv = CLI.CallConv; 2313252723Sdim bool IsVarArg = CLI.IsVarArg; 2314198090Srdivacky 2315193323Sed MachineFunction &MF = DAG.getMachineFunction(); 2316193323Sed MachineFrameInfo *MFI = MF.getFrameInfo(); 2317223017Sdim const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2318263509Sdim MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 2319198090Srdivacky bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2320193323Sed 2321193323Sed // Analyze operands of the call, assigning locations to each operand. 2322193323Sed SmallVector<CCValAssign, 16> ArgLocs; 2323252723Sdim CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2324235633Sdim getTargetMachine(), ArgLocs, *DAG.getContext()); 2325263509Sdim MipsCC::SpecialCallingConvType SpecialCallingConv = 2326263509Sdim getSpecialCallingConv(Callee); 2327263509Sdim MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo, 2328263509Sdim SpecialCallingConv); 2329193323Sed 2330252723Sdim MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, 2331263509Sdim Subtarget->mipsSEUsesSoftFloat(), 2332252723Sdim Callee.getNode(), CLI.Args); 2333218893Sdim 2334193323Sed // Get a count of how many bytes are to be pushed on the stack. 2335223017Sdim unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2336193323Sed 2337245431Sdim // Check if it's really possible to do a tail call. 2338252723Sdim if (IsTailCall) 2339252723Sdim IsTailCall = 2340252723Sdim isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset, 2341245431Sdim *MF.getInfo<MipsFunctionInfo>()); 2342245431Sdim 2343252723Sdim if (IsTailCall) 2344245431Sdim ++NumTailCalls; 2345245431Sdim 2346226890Sdim // Chain is the output chain of the last Load/Store or CopyToReg node. 2347226890Sdim // ByValChain is the output chain of the last Memcpy node created for copying 2348226890Sdim // byval arguments to the stack. 2349245431Sdim unsigned StackAlignment = TFL->getStackAlignment(); 2350245431Sdim NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2351226890Sdim SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2352223017Sdim 2353252723Sdim if (!IsTailCall) 2354263509Sdim Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2355223017Sdim 2356252723Sdim SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, 2357245431Sdim IsN64 ? Mips::SP_64 : Mips::SP, 2358245431Sdim getPointerTy()); 2359224145Sdim 2360193323Sed // With EABI is it possible to have 16 args on registers. 2361252723Sdim std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2362193323Sed SmallVector<SDValue, 8> MemOpChains; 2363245431Sdim MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2364193323Sed 2365193323Sed // Walk the register/memloc assignments, inserting copies/loads. 2366193323Sed for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2367210299Sed SDValue Arg = OutVals[i]; 2368193323Sed CCValAssign &VA = ArgLocs[i]; 2369235633Sdim MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2370235633Sdim ISD::ArgFlagsTy Flags = Outs[i].Flags; 2371193323Sed 2372235633Sdim // ByVal Arg. 2373235633Sdim if (Flags.isByVal()) { 2374235633Sdim assert(Flags.getByValSize() && 2375235633Sdim "ByVal args of size 0 should have been ignored by front-end."); 2376245431Sdim assert(ByValArg != MipsCCInfo.byval_end()); 2377252723Sdim assert(!IsTailCall && 2378245431Sdim "Do not tail-call optimize if there is a byval argument."); 2379252723Sdim passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2380245431Sdim MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); 2381245431Sdim ++ByValArg; 2382235633Sdim continue; 2383235633Sdim } 2384235633Sdim 2385193323Sed // Promote the value if needed. 2386193323Sed switch (VA.getLocInfo()) { 2387198090Srdivacky default: llvm_unreachable("Unknown loc info!"); 2388218893Sdim case CCValAssign::Full: 2389235633Sdim if (VA.isRegLoc()) { 2390235633Sdim if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2391252723Sdim (ValVT == MVT::f64 && LocVT == MVT::i64) || 2392252723Sdim (ValVT == MVT::i64 && LocVT == MVT::f64)) 2393252723Sdim Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2394235633Sdim else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2395252723Sdim SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2396221345Sdim Arg, DAG.getConstant(0, MVT::i32)); 2397252723Sdim SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2398221345Sdim Arg, DAG.getConstant(1, MVT::i32)); 2399221345Sdim if (!Subtarget->isLittle()) 2400221345Sdim std::swap(Lo, Hi); 2401235633Sdim unsigned LocRegLo = VA.getLocReg(); 2402226890Sdim unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2403226890Sdim RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2404226890Sdim RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2405193323Sed continue; 2406218893Sdim } 2407193323Sed } 2408193323Sed break; 2409193323Sed case CCValAssign::SExt: 2410252723Sdim Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2411193323Sed break; 2412193323Sed case CCValAssign::ZExt: 2413252723Sdim Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2414193323Sed break; 2415193323Sed case CCValAssign::AExt: 2416252723Sdim Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2417193323Sed break; 2418193323Sed } 2419218893Sdim 2420218893Sdim // Arguments that can be passed on register must be kept at 2421193323Sed // RegsToPass vector 2422193323Sed if (VA.isRegLoc()) { 2423193323Sed RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2424193323Sed continue; 2425193323Sed } 2426218893Sdim 2427193323Sed // Register can't get to this point... 2428193323Sed assert(VA.isMemLoc()); 2429218893Sdim 2430218893Sdim // emit ISD::STORE whichs stores the 2431193323Sed // parameter value to a stack Location 2432245431Sdim MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2433252723Sdim Chain, Arg, DL, IsTailCall, DAG)); 2434193323Sed } 2435193323Sed 2436193323Sed // Transform all store nodes into one single node because all store 2437193323Sed // nodes are independent of each other. 2438218893Sdim if (!MemOpChains.empty()) 2439252723Sdim Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2440193323Sed &MemOpChains[0], MemOpChains.size()); 2441193323Sed 2442193323Sed // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2443218893Sdim // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2444218893Sdim // node so that legalize doesn't hack it. 2445235633Sdim bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2446252723Sdim bool GlobalOrExternal = false, InternalLinkage = false; 2447221345Sdim SDValue CalleeLo; 2448263509Sdim EVT Ty = Callee.getValueType(); 2449221345Sdim 2450221345Sdim if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2451245431Sdim if (IsPICCall) { 2452263509Sdim const GlobalValue *Val = G->getGlobal(); 2453263509Sdim InternalLinkage = Val->hasInternalLinkage(); 2454252723Sdim 2455252723Sdim if (InternalLinkage) 2456263509Sdim Callee = getAddrLocal(G, Ty, DAG, HasMips64); 2457245431Sdim else if (LargeGOT) 2458263509Sdim Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16, 2459263509Sdim MipsII::MO_CALL_LO16, Chain, 2460263509Sdim FuncInfo->callPtrInfo(Val)); 2461245431Sdim else 2462263509Sdim Callee = getAddrGlobal(G, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2463263509Sdim FuncInfo->callPtrInfo(Val)); 2464245431Sdim } else 2465252723Sdim Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0, 2466245431Sdim MipsII::MO_NO_FLAG); 2467235633Sdim GlobalOrExternal = true; 2468221345Sdim } 2469221345Sdim else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2470263509Sdim const char *Sym = S->getSymbol(); 2471263509Sdim 2472245431Sdim if (!IsN64 && !IsPIC) // !N64 && static 2473263509Sdim Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 2474245431Sdim MipsII::MO_NO_FLAG); 2475245431Sdim else if (LargeGOT) 2476263509Sdim Callee = getAddrGlobalLargeGOT(S, Ty, DAG, MipsII::MO_CALL_HI16, 2477263509Sdim MipsII::MO_CALL_LO16, Chain, 2478263509Sdim FuncInfo->callPtrInfo(Sym)); 2479252723Sdim else // N64 || PIC 2480263509Sdim Callee = getAddrGlobal(S, Ty, DAG, MipsII::MO_GOT_CALL, Chain, 2481263509Sdim FuncInfo->callPtrInfo(Sym)); 2482245431Sdim 2483235633Sdim GlobalOrExternal = true; 2484221345Sdim } 2485193323Sed 2486252723Sdim SmallVector<SDValue, 8> Ops(1, Chain); 2487218893Sdim SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2488193323Sed 2489252723Sdim getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2490252723Sdim CLI, Callee, Chain); 2491193323Sed 2492252723Sdim if (IsTailCall) 2493252723Sdim return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size()); 2494245431Sdim 2495252723Sdim Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size()); 2496252723Sdim SDValue InFlag = Chain.getValue(1); 2497235633Sdim 2498203954Srdivacky // Create the CALLSEQ_END node. 2499245431Sdim Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2500263509Sdim DAG.getIntPtrConstant(0, true), InFlag, DL); 2501203954Srdivacky InFlag = Chain.getValue(1); 2502203954Srdivacky 2503193323Sed // Handle result values, copying them out of physregs into vregs that we 2504193323Sed // return. 2505252723Sdim return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, 2506252723Sdim Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy); 2507193323Sed} 2508193323Sed 2509198090Srdivacky/// LowerCallResult - Lower the result values of a call into the 2510198090Srdivacky/// appropriate copies out of appropriate physical registers. 2511198090SrdivackySDValue 2512198090SrdivackyMipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2513252723Sdim CallingConv::ID CallConv, bool IsVarArg, 2514198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 2515263509Sdim SDLoc DL, SelectionDAG &DAG, 2516252723Sdim SmallVectorImpl<SDValue> &InVals, 2517252723Sdim const SDNode *CallNode, 2518252723Sdim const Type *RetTy) const { 2519193323Sed // Assign locations to each value returned by this call. 2520193323Sed SmallVector<CCValAssign, 16> RVLocs; 2521252723Sdim CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2522245431Sdim getTargetMachine(), RVLocs, *DAG.getContext()); 2523263509Sdim MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2524193323Sed 2525263509Sdim MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(), 2526252723Sdim CallNode, RetTy); 2527193323Sed 2528193323Sed // Copy all of the result registers out of their specified physreg. 2529193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) { 2530252723Sdim SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2531252723Sdim RVLocs[i].getLocVT(), InFlag); 2532252723Sdim Chain = Val.getValue(1); 2533252723Sdim InFlag = Val.getValue(2); 2534252723Sdim 2535252723Sdim if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2536252723Sdim Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val); 2537252723Sdim 2538252723Sdim InVals.push_back(Val); 2539193323Sed } 2540193323Sed 2541198090Srdivacky return Chain; 2542193323Sed} 2543193323Sed 2544193323Sed//===----------------------------------------------------------------------===// 2545198090Srdivacky// Formal Arguments Calling Convention Implementation 2546193323Sed//===----------------------------------------------------------------------===// 2547218893Sdim/// LowerFormalArguments - transform physical registers into virtual registers 2548203954Srdivacky/// and generate load operations for arguments places on the stack. 2549198090SrdivackySDValue 2550198090SrdivackyMipsTargetLowering::LowerFormalArguments(SDValue Chain, 2551221345Sdim CallingConv::ID CallConv, 2552252723Sdim bool IsVarArg, 2553235633Sdim const SmallVectorImpl<ISD::InputArg> &Ins, 2554263509Sdim SDLoc DL, SelectionDAG &DAG, 2555221345Sdim SmallVectorImpl<SDValue> &InVals) 2556207618Srdivacky const { 2557193323Sed MachineFunction &MF = DAG.getMachineFunction(); 2558193323Sed MachineFrameInfo *MFI = MF.getFrameInfo(); 2559193323Sed MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2560193323Sed 2561207618Srdivacky MipsFI->setVarArgsFrameIndex(0); 2562193323Sed 2563203954Srdivacky // Used with vargs to acumulate store chains. 2564203954Srdivacky std::vector<SDValue> OutChains; 2565203954Srdivacky 2566193323Sed // Assign locations to all of the incoming arguments. 2567193323Sed SmallVector<CCValAssign, 16> ArgLocs; 2568252723Sdim CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2569235633Sdim getTargetMachine(), ArgLocs, *DAG.getContext()); 2570263509Sdim MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2571252723Sdim Function::const_arg_iterator FuncArg = 2572252723Sdim DAG.getMachineFunction().getFunction()->arg_begin(); 2573263509Sdim bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat(); 2574193323Sed 2575252723Sdim MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg); 2576245431Sdim MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 2577245431Sdim MipsCCInfo.hasByValArg()); 2578193323Sed 2579245431Sdim unsigned CurArgIdx = 0; 2580245431Sdim MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2581193323Sed 2582245431Sdim for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2583193323Sed CCValAssign &VA = ArgLocs[i]; 2584245431Sdim std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 2585245431Sdim CurArgIdx = Ins[i].OrigArgIndex; 2586235633Sdim EVT ValVT = VA.getValVT(); 2587235633Sdim ISD::ArgFlagsTy Flags = Ins[i].Flags; 2588235633Sdim bool IsRegLoc = VA.isRegLoc(); 2589193323Sed 2590235633Sdim if (Flags.isByVal()) { 2591235633Sdim assert(Flags.getByValSize() && 2592235633Sdim "ByVal args of size 0 should have been ignored by front-end."); 2593245431Sdim assert(ByValArg != MipsCCInfo.byval_end()); 2594252723Sdim copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 2595245431Sdim MipsCCInfo, *ByValArg); 2596245431Sdim ++ByValArg; 2597235633Sdim continue; 2598235633Sdim } 2599235633Sdim 2600193323Sed // Arguments stored on registers 2601235633Sdim if (IsRegLoc) { 2602263509Sdim MVT RegVT = VA.getLocVT(); 2603223017Sdim unsigned ArgReg = VA.getLocReg(); 2604263509Sdim const TargetRegisterClass *RC = getRegClassFor(RegVT); 2605193323Sed 2606218893Sdim // Transform the arguments stored on 2607193323Sed // physical registers into virtual ones 2608252723Sdim unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2609252723Sdim SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 2610218893Sdim 2611218893Sdim // If this is an 8 or 16-bit value, it has been passed promoted 2612218893Sdim // to 32 bits. Insert an assert[sz]ext to capture this, then 2613193323Sed // truncate to the right size. 2614193323Sed if (VA.getLocInfo() != CCValAssign::Full) { 2615193323Sed unsigned Opcode = 0; 2616193323Sed if (VA.getLocInfo() == CCValAssign::SExt) 2617193323Sed Opcode = ISD::AssertSext; 2618193323Sed else if (VA.getLocInfo() == CCValAssign::ZExt) 2619193323Sed Opcode = ISD::AssertZext; 2620193323Sed if (Opcode) 2621252723Sdim ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, 2622235633Sdim DAG.getValueType(ValVT)); 2623252723Sdim ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue); 2624193323Sed } 2625193323Sed 2626252723Sdim // Handle floating point arguments passed in integer registers and 2627252723Sdim // long double arguments passed in floating point registers. 2628235633Sdim if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 2629252723Sdim (RegVT == MVT::i64 && ValVT == MVT::f64) || 2630252723Sdim (RegVT == MVT::f64 && ValVT == MVT::i64)) 2631252723Sdim ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 2632235633Sdim else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 2633252723Sdim unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 2634235633Sdim getNextIntArgReg(ArgReg), RC); 2635252723Sdim SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 2636235633Sdim if (!Subtarget->isLittle()) 2637235633Sdim std::swap(ArgValue, ArgValue2); 2638252723Sdim ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 2639235633Sdim ArgValue, ArgValue2); 2640193323Sed } 2641193323Sed 2642198090Srdivacky InVals.push_back(ArgValue); 2643193323Sed } else { // VA.isRegLoc() 2644193323Sed 2645193323Sed // sanity check 2646193323Sed assert(VA.isMemLoc()); 2647203954Srdivacky 2648218893Sdim // The stack pointer offset is relative to the caller stack frame. 2649245431Sdim int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2650223017Sdim VA.getLocMemOffset(), true); 2651193323Sed 2652193323Sed // Create load nodes to retrieve arguments from the stack 2653245431Sdim SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2654263509Sdim SDValue Load = DAG.getLoad(ValVT, DL, Chain, FIN, 2655263509Sdim MachinePointerInfo::getFixedStack(FI), 2656263509Sdim false, false, false, 0); 2657263509Sdim InVals.push_back(Load); 2658263509Sdim OutChains.push_back(Load.getValue(1)); 2659193323Sed } 2660193323Sed } 2661193323Sed 2662193323Sed // The mips ABIs for returning structs by value requires that we copy 2663193323Sed // the sret argument into $v0 for the return. Save the argument into 2664193323Sed // a virtual register so that we can access it from the return points. 2665193323Sed if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2666193323Sed unsigned Reg = MipsFI->getSRetReturnReg(); 2667193323Sed if (!Reg) { 2668245431Sdim Reg = MF.getRegInfo(). 2669245431Sdim createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32)); 2670193323Sed MipsFI->setSRetReturnReg(Reg); 2671193323Sed } 2672252723Sdim SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]); 2673252723Sdim Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 2674193323Sed } 2675193323Sed 2676252723Sdim if (IsVarArg) 2677252723Sdim writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG); 2678235633Sdim 2679218893Sdim // All stores are grouped in one node to allow the matching between 2680203954Srdivacky // the size of Ins and InVals. This only happens when on varg functions 2681203954Srdivacky if (!OutChains.empty()) { 2682203954Srdivacky OutChains.push_back(Chain); 2683252723Sdim Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2684203954Srdivacky &OutChains[0], OutChains.size()); 2685203954Srdivacky } 2686203954Srdivacky 2687198090Srdivacky return Chain; 2688193323Sed} 2689193323Sed 2690193323Sed//===----------------------------------------------------------------------===// 2691193323Sed// Return Value Calling Convention Implementation 2692193323Sed//===----------------------------------------------------------------------===// 2693193323Sed 2694245431Sdimbool 2695245431SdimMipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 2696252723Sdim MachineFunction &MF, bool IsVarArg, 2697245431Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 2698245431Sdim LLVMContext &Context) const { 2699245431Sdim SmallVector<CCValAssign, 16> RVLocs; 2700252723Sdim CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), 2701245431Sdim RVLocs, Context); 2702245431Sdim return CCInfo.CheckReturn(Outs, RetCC_Mips); 2703245431Sdim} 2704245431Sdim 2705198090SrdivackySDValue 2706198090SrdivackyMipsTargetLowering::LowerReturn(SDValue Chain, 2707252723Sdim CallingConv::ID CallConv, bool IsVarArg, 2708198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 2709210299Sed const SmallVectorImpl<SDValue> &OutVals, 2710263509Sdim SDLoc DL, SelectionDAG &DAG) const { 2711193323Sed // CCValAssign - represent the assignment of 2712193323Sed // the return value to a location 2713193323Sed SmallVector<CCValAssign, 16> RVLocs; 2714252723Sdim MachineFunction &MF = DAG.getMachineFunction(); 2715193323Sed 2716193323Sed // CCState - Info about the registers and stack slot. 2717252723Sdim CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs, 2718252723Sdim *DAG.getContext()); 2719263509Sdim MipsCC MipsCCInfo(CallConv, IsO32, Subtarget->isFP64bit(), CCInfo); 2720193323Sed 2721252723Sdim // Analyze return values. 2722263509Sdim MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(), 2723252723Sdim MF.getFunction()->getReturnType()); 2724193323Sed 2725193323Sed SDValue Flag; 2726252723Sdim SmallVector<SDValue, 4> RetOps(1, Chain); 2727193323Sed 2728193323Sed // Copy the result values into the output registers. 2729193323Sed for (unsigned i = 0; i != RVLocs.size(); ++i) { 2730252723Sdim SDValue Val = OutVals[i]; 2731193323Sed CCValAssign &VA = RVLocs[i]; 2732193323Sed assert(VA.isRegLoc() && "Can only return in registers!"); 2733193323Sed 2734252723Sdim if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2735252723Sdim Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val); 2736193323Sed 2737252723Sdim Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 2738252723Sdim 2739252723Sdim // Guarantee that all emitted copies are stuck together with flags. 2740193323Sed Flag = Chain.getValue(1); 2741252723Sdim RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 2742193323Sed } 2743193323Sed 2744193323Sed // The mips ABIs for returning structs by value requires that we copy 2745193323Sed // the sret argument into $v0 for the return. We saved the argument into 2746193323Sed // a virtual register in the entry block, so now we copy the value out 2747193323Sed // and into $v0. 2748252723Sdim if (MF.getFunction()->hasStructRetAttr()) { 2749193323Sed MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2750193323Sed unsigned Reg = MipsFI->getSRetReturnReg(); 2751193323Sed 2752218893Sdim if (!Reg) 2753198090Srdivacky llvm_unreachable("sret virtual register not created in the entry block"); 2754252723Sdim SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 2755245431Sdim unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0; 2756193323Sed 2757252723Sdim Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 2758193323Sed Flag = Chain.getValue(1); 2759252723Sdim RetOps.push_back(DAG.getRegister(V0, getPointerTy())); 2760193323Sed } 2761193323Sed 2762252723Sdim RetOps[0] = Chain; // Update chain. 2763252723Sdim 2764252723Sdim // Add the flag if we have it. 2765193323Sed if (Flag.getNode()) 2766252723Sdim RetOps.push_back(Flag); 2767245431Sdim 2768252723Sdim // Return on Mips is always a "jr $ra" 2769252723Sdim return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size()); 2770193323Sed} 2771193323Sed 2772193323Sed//===----------------------------------------------------------------------===// 2773193323Sed// Mips Inline Assembly Support 2774193323Sed//===----------------------------------------------------------------------===// 2775193323Sed 2776193323Sed/// getConstraintType - Given a constraint letter, return the type of 2777193323Sed/// constraint it is for this target. 2778193323SedMipsTargetLowering::ConstraintType MipsTargetLowering:: 2779218893SdimgetConstraintType(const std::string &Constraint) const 2780193323Sed{ 2781263509Sdim // Mips specific constraints 2782193323Sed // GCC config/mips/constraints.md 2783193323Sed // 2784218893Sdim // 'd' : An address register. Equivalent to r 2785218893Sdim // unless generating MIPS16 code. 2786218893Sdim // 'y' : Equivalent to r; retained for 2787218893Sdim // backwards compatibility. 2788245431Sdim // 'c' : A register suitable for use in an indirect 2789245431Sdim // jump. This will always be $25 for -mabicalls. 2790245431Sdim // 'l' : The lo register. 1 word storage. 2791245431Sdim // 'x' : The hilo register pair. Double word storage. 2792193323Sed if (Constraint.size() == 1) { 2793193323Sed switch (Constraint[0]) { 2794193323Sed default : break; 2795218893Sdim case 'd': 2796218893Sdim case 'y': 2797193323Sed case 'f': 2798245431Sdim case 'c': 2799245431Sdim case 'l': 2800245431Sdim case 'x': 2801193323Sed return C_RegisterClass; 2802252723Sdim case 'R': 2803252723Sdim return C_Memory; 2804193323Sed } 2805193323Sed } 2806193323Sed return TargetLowering::getConstraintType(Constraint); 2807193323Sed} 2808193323Sed 2809218893Sdim/// Examine constraint type and operand type and determine a weight value. 2810218893Sdim/// This object must already have been set up with the operand type 2811218893Sdim/// and the current alternative constraint selected. 2812218893SdimTargetLowering::ConstraintWeight 2813218893SdimMipsTargetLowering::getSingleConstraintMatchWeight( 2814218893Sdim AsmOperandInfo &info, const char *constraint) const { 2815218893Sdim ConstraintWeight weight = CW_Invalid; 2816218893Sdim Value *CallOperandVal = info.CallOperandVal; 2817218893Sdim // If we don't have a value, we can't do a match, 2818218893Sdim // but allow it at the lowest weight. 2819218893Sdim if (CallOperandVal == NULL) 2820218893Sdim return CW_Default; 2821226890Sdim Type *type = CallOperandVal->getType(); 2822218893Sdim // Look at the constraint type. 2823218893Sdim switch (*constraint) { 2824218893Sdim default: 2825218893Sdim weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2826218893Sdim break; 2827218893Sdim case 'd': 2828218893Sdim case 'y': 2829218893Sdim if (type->isIntegerTy()) 2830218893Sdim weight = CW_Register; 2831218893Sdim break; 2832263509Sdim case 'f': // FPU or MSA register 2833263509Sdim if (Subtarget->hasMSA() && type->isVectorTy() && 2834263509Sdim cast<VectorType>(type)->getBitWidth() == 128) 2835218893Sdim weight = CW_Register; 2836263509Sdim else if (type->isFloatTy()) 2837263509Sdim weight = CW_Register; 2838218893Sdim break; 2839245431Sdim case 'c': // $25 for indirect jumps 2840245431Sdim case 'l': // lo register 2841245431Sdim case 'x': // hilo register pair 2842263509Sdim if (type->isIntegerTy()) 2843245431Sdim weight = CW_SpecificReg; 2844263509Sdim break; 2845245431Sdim case 'I': // signed 16 bit immediate 2846245431Sdim case 'J': // integer zero 2847245431Sdim case 'K': // unsigned 16 bit immediate 2848245431Sdim case 'L': // signed 32 bit immediate where lower 16 bits are 0 2849245431Sdim case 'N': // immediate in the range of -65535 to -1 (inclusive) 2850245431Sdim case 'O': // signed 15 bit immediate (+- 16383) 2851245431Sdim case 'P': // immediate in the range of 65535 to 1 (inclusive) 2852245431Sdim if (isa<ConstantInt>(CallOperandVal)) 2853245431Sdim weight = CW_Constant; 2854245431Sdim break; 2855252723Sdim case 'R': 2856252723Sdim weight = CW_Memory; 2857252723Sdim break; 2858218893Sdim } 2859218893Sdim return weight; 2860218893Sdim} 2861218893Sdim 2862263509Sdim/// This is a helper function to parse a physical register string and split it 2863263509Sdim/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag 2864263509Sdim/// that is returned indicates whether parsing was successful. The second flag 2865263509Sdim/// is true if the numeric part exists. 2866263509Sdimstatic std::pair<bool, bool> 2867263509SdimparsePhysicalReg(const StringRef &C, std::string &Prefix, 2868263509Sdim unsigned long long &Reg) { 2869263509Sdim if (C.front() != '{' || C.back() != '}') 2870263509Sdim return std::make_pair(false, false); 2871263509Sdim 2872263509Sdim // Search for the first numeric character. 2873263509Sdim StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1; 2874263509Sdim I = std::find_if(B, E, std::ptr_fun(isdigit)); 2875263509Sdim 2876263509Sdim Prefix.assign(B, I - B); 2877263509Sdim 2878263509Sdim // The second flag is set to false if no numeric characters were found. 2879263509Sdim if (I == E) 2880263509Sdim return std::make_pair(true, false); 2881263509Sdim 2882263509Sdim // Parse the numeric characters. 2883263509Sdim return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg), 2884263509Sdim true); 2885263509Sdim} 2886263509Sdim 2887263509Sdimstd::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: 2888263509SdimparseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const { 2889263509Sdim const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2890263509Sdim const TargetRegisterClass *RC; 2891263509Sdim std::string Prefix; 2892263509Sdim unsigned long long Reg; 2893263509Sdim 2894263509Sdim std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg); 2895263509Sdim 2896263509Sdim if (!R.first) 2897263509Sdim return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2898263509Sdim 2899263509Sdim if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo. 2900263509Sdim // No numeric characters follow "hi" or "lo". 2901263509Sdim if (R.second) 2902263509Sdim return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2903263509Sdim 2904263509Sdim RC = TRI->getRegClass(Prefix == "hi" ? 2905263509Sdim Mips::HI32RegClassID : Mips::LO32RegClassID); 2906263509Sdim return std::make_pair(*(RC->begin()), RC); 2907263509Sdim } else if (Prefix.compare(0, 4, "$msa") == 0) { 2908263509Sdim // Parse $msa(ir|csr|access|save|modify|request|map|unmap) 2909263509Sdim 2910263509Sdim // No numeric characters follow the name. 2911263509Sdim if (R.second) 2912263509Sdim return std::make_pair((unsigned)0, (const TargetRegisterClass *)0); 2913263509Sdim 2914263509Sdim Reg = StringSwitch<unsigned long long>(Prefix) 2915263509Sdim .Case("$msair", Mips::MSAIR) 2916263509Sdim .Case("$msacsr", Mips::MSACSR) 2917263509Sdim .Case("$msaaccess", Mips::MSAAccess) 2918263509Sdim .Case("$msasave", Mips::MSASave) 2919263509Sdim .Case("$msamodify", Mips::MSAModify) 2920263509Sdim .Case("$msarequest", Mips::MSARequest) 2921263509Sdim .Case("$msamap", Mips::MSAMap) 2922263509Sdim .Case("$msaunmap", Mips::MSAUnmap) 2923263509Sdim .Default(0); 2924263509Sdim 2925263509Sdim if (!Reg) 2926263509Sdim return std::make_pair((unsigned)0, (const TargetRegisterClass *)0); 2927263509Sdim 2928263509Sdim RC = TRI->getRegClass(Mips::MSACtrlRegClassID); 2929263509Sdim return std::make_pair(Reg, RC); 2930263509Sdim } 2931263509Sdim 2932263509Sdim if (!R.second) 2933263509Sdim return std::make_pair((unsigned)0, (const TargetRegisterClass*)0); 2934263509Sdim 2935263509Sdim if (Prefix == "$f") { // Parse $f0-$f31. 2936263509Sdim // If the size of FP registers is 64-bit or Reg is an even number, select 2937263509Sdim // the 64-bit register class. Otherwise, select the 32-bit register class. 2938263509Sdim if (VT == MVT::Other) 2939263509Sdim VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; 2940263509Sdim 2941263509Sdim RC = getRegClassFor(VT); 2942263509Sdim 2943263509Sdim if (RC == &Mips::AFGR64RegClass) { 2944263509Sdim assert(Reg % 2 == 0); 2945263509Sdim Reg >>= 1; 2946263509Sdim } 2947263509Sdim } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7. 2948263509Sdim RC = TRI->getRegClass(Mips::FCCRegClassID); 2949263509Sdim else if (Prefix == "$w") { // Parse $w0-$w31. 2950263509Sdim RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); 2951263509Sdim } else { // Parse $0-$31. 2952263509Sdim assert(Prefix == "$"); 2953263509Sdim RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); 2954263509Sdim } 2955263509Sdim 2956263509Sdim assert(Reg < RC->getNumRegs()); 2957263509Sdim return std::make_pair(*(RC->begin() + Reg), RC); 2958263509Sdim} 2959263509Sdim 2960224145Sdim/// Given a register class constraint, like 'r', if this corresponds directly 2961224145Sdim/// to an LLVM register class, return a register of 0 and the register class 2962224145Sdim/// pointer. 2963193323Sedstd::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2964263509SdimgetRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const 2965193323Sed{ 2966193323Sed if (Constraint.size() == 1) { 2967193323Sed switch (Constraint[0]) { 2968224145Sdim case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2969224145Sdim case 'y': // Same as 'r'. Exists for compatibility. 2970193323Sed case 'r': 2971245431Sdim if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 2972245431Sdim if (Subtarget->inMips16Mode()) 2973245431Sdim return std::make_pair(0U, &Mips::CPU16RegsRegClass); 2974263509Sdim return std::make_pair(0U, &Mips::GPR32RegClass); 2975245431Sdim } 2976245431Sdim if (VT == MVT::i64 && !HasMips64) 2977263509Sdim return std::make_pair(0U, &Mips::GPR32RegClass); 2978245431Sdim if (VT == MVT::i64 && HasMips64) 2979263509Sdim return std::make_pair(0U, &Mips::GPR64RegClass); 2980245431Sdim // This will generate an error message 2981245431Sdim return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2982263509Sdim case 'f': // FPU or MSA register 2983263509Sdim if (VT == MVT::v16i8) 2984263509Sdim return std::make_pair(0U, &Mips::MSA128BRegClass); 2985263509Sdim else if (VT == MVT::v8i16 || VT == MVT::v8f16) 2986263509Sdim return std::make_pair(0U, &Mips::MSA128HRegClass); 2987263509Sdim else if (VT == MVT::v4i32 || VT == MVT::v4f32) 2988263509Sdim return std::make_pair(0U, &Mips::MSA128WRegClass); 2989263509Sdim else if (VT == MVT::v2i64 || VT == MVT::v2f64) 2990263509Sdim return std::make_pair(0U, &Mips::MSA128DRegClass); 2991263509Sdim else if (VT == MVT::f32) 2992245431Sdim return std::make_pair(0U, &Mips::FGR32RegClass); 2993263509Sdim else if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 2994235633Sdim if (Subtarget->isFP64bit()) 2995245431Sdim return std::make_pair(0U, &Mips::FGR64RegClass); 2996245431Sdim return std::make_pair(0U, &Mips::AFGR64RegClass); 2997235633Sdim } 2998245431Sdim break; 2999245431Sdim case 'c': // register suitable for indirect jump 3000245431Sdim if (VT == MVT::i32) 3001263509Sdim return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 3002245431Sdim assert(VT == MVT::i64 && "Unexpected type."); 3003263509Sdim return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 3004245431Sdim case 'l': // register suitable for indirect jump 3005245431Sdim if (VT == MVT::i32) 3006263509Sdim return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass); 3007263509Sdim return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass); 3008245431Sdim case 'x': // register suitable for indirect jump 3009245431Sdim // Fixme: Not triggering the use of both hi and low 3010245431Sdim // This will generate an error message 3011245431Sdim return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 3012193323Sed } 3013193323Sed } 3014263509Sdim 3015263509Sdim std::pair<unsigned, const TargetRegisterClass *> R; 3016263509Sdim R = parseRegForInlineAsmConstraint(Constraint, VT); 3017263509Sdim 3018263509Sdim if (R.second) 3019263509Sdim return R; 3020263509Sdim 3021193323Sed return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3022193323Sed} 3023193323Sed 3024245431Sdim/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3025245431Sdim/// vector. If it is invalid, don't add anything to Ops. 3026245431Sdimvoid MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 3027245431Sdim std::string &Constraint, 3028245431Sdim std::vector<SDValue>&Ops, 3029245431Sdim SelectionDAG &DAG) const { 3030245431Sdim SDValue Result(0, 0); 3031245431Sdim 3032245431Sdim // Only support length 1 constraints for now. 3033245431Sdim if (Constraint.length() > 1) return; 3034245431Sdim 3035245431Sdim char ConstraintLetter = Constraint[0]; 3036245431Sdim switch (ConstraintLetter) { 3037245431Sdim default: break; // This will fall through to the generic implementation 3038245431Sdim case 'I': // Signed 16 bit constant 3039245431Sdim // If this fails, the parent routine will give an error 3040245431Sdim if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3041245431Sdim EVT Type = Op.getValueType(); 3042245431Sdim int64_t Val = C->getSExtValue(); 3043245431Sdim if (isInt<16>(Val)) { 3044245431Sdim Result = DAG.getTargetConstant(Val, Type); 3045245431Sdim break; 3046245431Sdim } 3047245431Sdim } 3048245431Sdim return; 3049245431Sdim case 'J': // integer zero 3050245431Sdim if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3051245431Sdim EVT Type = Op.getValueType(); 3052245431Sdim int64_t Val = C->getZExtValue(); 3053245431Sdim if (Val == 0) { 3054245431Sdim Result = DAG.getTargetConstant(0, Type); 3055245431Sdim break; 3056245431Sdim } 3057245431Sdim } 3058245431Sdim return; 3059245431Sdim case 'K': // unsigned 16 bit immediate 3060245431Sdim if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3061245431Sdim EVT Type = Op.getValueType(); 3062245431Sdim uint64_t Val = (uint64_t)C->getZExtValue(); 3063245431Sdim if (isUInt<16>(Val)) { 3064245431Sdim Result = DAG.getTargetConstant(Val, Type); 3065245431Sdim break; 3066245431Sdim } 3067245431Sdim } 3068245431Sdim return; 3069245431Sdim case 'L': // signed 32 bit immediate where lower 16 bits are 0 3070245431Sdim if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3071245431Sdim EVT Type = Op.getValueType(); 3072245431Sdim int64_t Val = C->getSExtValue(); 3073245431Sdim if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 3074245431Sdim Result = DAG.getTargetConstant(Val, Type); 3075245431Sdim break; 3076245431Sdim } 3077245431Sdim } 3078245431Sdim return; 3079245431Sdim case 'N': // immediate in the range of -65535 to -1 (inclusive) 3080245431Sdim if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3081245431Sdim EVT Type = Op.getValueType(); 3082245431Sdim int64_t Val = C->getSExtValue(); 3083245431Sdim if ((Val >= -65535) && (Val <= -1)) { 3084245431Sdim Result = DAG.getTargetConstant(Val, Type); 3085245431Sdim break; 3086245431Sdim } 3087245431Sdim } 3088245431Sdim return; 3089245431Sdim case 'O': // signed 15 bit immediate 3090245431Sdim if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3091245431Sdim EVT Type = Op.getValueType(); 3092245431Sdim int64_t Val = C->getSExtValue(); 3093245431Sdim if ((isInt<15>(Val))) { 3094245431Sdim Result = DAG.getTargetConstant(Val, Type); 3095245431Sdim break; 3096245431Sdim } 3097245431Sdim } 3098245431Sdim return; 3099245431Sdim case 'P': // immediate in the range of 1 to 65535 (inclusive) 3100245431Sdim if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3101245431Sdim EVT Type = Op.getValueType(); 3102245431Sdim int64_t Val = C->getSExtValue(); 3103245431Sdim if ((Val <= 65535) && (Val >= 1)) { 3104245431Sdim Result = DAG.getTargetConstant(Val, Type); 3105245431Sdim break; 3106245431Sdim } 3107245431Sdim } 3108245431Sdim return; 3109245431Sdim } 3110245431Sdim 3111245431Sdim if (Result.getNode()) { 3112245431Sdim Ops.push_back(Result); 3113245431Sdim return; 3114245431Sdim } 3115245431Sdim 3116245431Sdim TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3117245431Sdim} 3118245431Sdim 3119263509Sdimbool MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, 3120263509Sdim Type *Ty) const { 3121252723Sdim // No global is ever allowed as a base. 3122252723Sdim if (AM.BaseGV) 3123252723Sdim return false; 3124252723Sdim 3125252723Sdim switch (AM.Scale) { 3126252723Sdim case 0: // "r+i" or just "i", depending on HasBaseReg. 3127252723Sdim break; 3128252723Sdim case 1: 3129252723Sdim if (!AM.HasBaseReg) // allow "r+i". 3130252723Sdim break; 3131252723Sdim return false; // disallow "r+r" or "r+r+i". 3132252723Sdim default: 3133252723Sdim return false; 3134252723Sdim } 3135252723Sdim 3136252723Sdim return true; 3137252723Sdim} 3138252723Sdim 3139252723Sdimbool 3140193323SedMipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3141193323Sed // The Mips target isn't yet aware of offsets. 3142193323Sed return false; 3143193323Sed} 3144198892Srdivacky 3145245431SdimEVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3146252723Sdim unsigned SrcAlign, 3147252723Sdim bool IsMemset, bool ZeroMemset, 3148245431Sdim bool MemcpyStrSrc, 3149245431Sdim MachineFunction &MF) const { 3150245431Sdim if (Subtarget->hasMips64()) 3151245431Sdim return MVT::i64; 3152245431Sdim 3153245431Sdim return MVT::i32; 3154245431Sdim} 3155245431Sdim 3156198892Srdivackybool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3157198892Srdivacky if (VT != MVT::f32 && VT != MVT::f64) 3158198892Srdivacky return false; 3159218893Sdim if (Imm.isNegZero()) 3160218893Sdim return false; 3161198892Srdivacky return Imm.isZero(); 3162198892Srdivacky} 3163235633Sdim 3164235633Sdimunsigned MipsTargetLowering::getJumpTableEncoding() const { 3165235633Sdim if (IsN64) 3166235633Sdim return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3167235633Sdim 3168235633Sdim return TargetLowering::getJumpTableEncoding(); 3169235633Sdim} 3170245431Sdim 3171252723Sdim/// This function returns true if CallSym is a long double emulation routine. 3172252723Sdimstatic bool isF128SoftLibCall(const char *CallSym) { 3173252723Sdim const char *const LibCalls[] = 3174252723Sdim {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2", 3175252723Sdim "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi", 3176252723Sdim "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf", 3177252723Sdim "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2", 3178252723Sdim "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3", 3179252723Sdim "__trunctfdf2", "__trunctfsf2", "__unordtf2", 3180252723Sdim "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl", 3181252723Sdim "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl", 3182252723Sdim "truncl"}; 3183245431Sdim 3184263509Sdim const char *const *End = LibCalls + array_lengthof(LibCalls); 3185245431Sdim 3186252723Sdim // Check that LibCalls is sorted alphabetically. 3187252723Sdim MipsTargetLowering::LTStr Comp; 3188245431Sdim 3189252723Sdim#ifndef NDEBUG 3190263509Sdim for (const char *const *I = LibCalls; I < End - 1; ++I) 3191252723Sdim assert(Comp(*I, *(I + 1))); 3192252723Sdim#endif 3193252723Sdim 3194252723Sdim return std::binary_search(LibCalls, End, CallSym, Comp); 3195252723Sdim} 3196252723Sdim 3197252723Sdim/// This function returns true if Ty is fp128 or i128 which was originally a 3198252723Sdim/// fp128. 3199252723Sdimstatic bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) { 3200252723Sdim if (Ty->isFP128Ty()) 3201252723Sdim return true; 3202252723Sdim 3203252723Sdim const ExternalSymbolSDNode *ES = 3204252723Sdim dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode); 3205252723Sdim 3206252723Sdim // If the Ty is i128 and the function being called is a long double emulation 3207252723Sdim // routine, then the original type is f128. 3208252723Sdim return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol())); 3209252723Sdim} 3210252723Sdim 3211263509SdimMipsTargetLowering::MipsCC::SpecialCallingConvType 3212263509Sdim MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const { 3213263509Sdim MipsCC::SpecialCallingConvType SpecialCallingConv = 3214263509Sdim MipsCC::NoSpecialCallingConv;; 3215263509Sdim if (Subtarget->inMips16HardFloat()) { 3216263509Sdim if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3217263509Sdim llvm::StringRef Sym = G->getGlobal()->getName(); 3218263509Sdim Function *F = G->getGlobal()->getParent()->getFunction(Sym); 3219263509Sdim if (F->hasFnAttribute("__Mips16RetHelper")) { 3220263509Sdim SpecialCallingConv = MipsCC::Mips16RetHelperConv; 3221263509Sdim } 3222263509Sdim } 3223263509Sdim } 3224263509Sdim return SpecialCallingConv; 3225263509Sdim} 3226263509Sdim 3227263509SdimMipsTargetLowering::MipsCC::MipsCC( 3228263509Sdim CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info, 3229263509Sdim MipsCC::SpecialCallingConvType SpecialCallingConv_) 3230263509Sdim : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_), 3231263509Sdim SpecialCallingConv(SpecialCallingConv_){ 3232245431Sdim // Pre-allocate reserved argument area. 3233252723Sdim CCInfo.AllocateStack(reservedArgArea(), 1); 3234245431Sdim} 3235245431Sdim 3236263509Sdim 3237245431Sdimvoid MipsTargetLowering::MipsCC:: 3238252723SdimanalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args, 3239252723Sdim bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, 3240252723Sdim std::vector<ArgListEntry> &FuncArgs) { 3241252723Sdim assert((CallConv != CallingConv::Fast || !IsVarArg) && 3242252723Sdim "CallingConv::Fast shouldn't be used for vararg functions."); 3243252723Sdim 3244245431Sdim unsigned NumOpnds = Args.size(); 3245252723Sdim llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn(); 3246245431Sdim 3247245431Sdim for (unsigned I = 0; I != NumOpnds; ++I) { 3248245431Sdim MVT ArgVT = Args[I].VT; 3249245431Sdim ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3250245431Sdim bool R; 3251245431Sdim 3252245431Sdim if (ArgFlags.isByVal()) { 3253245431Sdim handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3254245431Sdim continue; 3255245431Sdim } 3256245431Sdim 3257252723Sdim if (IsVarArg && !Args[I].IsFixed) 3258245431Sdim R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3259252723Sdim else { 3260252723Sdim MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode, 3261252723Sdim IsSoftFloat); 3262252723Sdim R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo); 3263252723Sdim } 3264245431Sdim 3265245431Sdim if (R) { 3266245431Sdim#ifndef NDEBUG 3267245431Sdim dbgs() << "Call operand #" << I << " has unhandled type " 3268245431Sdim << EVT(ArgVT).getEVTString(); 3269245431Sdim#endif 3270245431Sdim llvm_unreachable(0); 3271245431Sdim } 3272245431Sdim } 3273245431Sdim} 3274245431Sdim 3275245431Sdimvoid MipsTargetLowering::MipsCC:: 3276252723SdimanalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args, 3277252723Sdim bool IsSoftFloat, Function::const_arg_iterator FuncArg) { 3278245431Sdim unsigned NumArgs = Args.size(); 3279252723Sdim llvm::CCAssignFn *FixedFn = fixedArgFn(); 3280252723Sdim unsigned CurArgIdx = 0; 3281245431Sdim 3282245431Sdim for (unsigned I = 0; I != NumArgs; ++I) { 3283245431Sdim MVT ArgVT = Args[I].VT; 3284245431Sdim ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3285252723Sdim std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx); 3286252723Sdim CurArgIdx = Args[I].OrigArgIndex; 3287245431Sdim 3288245431Sdim if (ArgFlags.isByVal()) { 3289245431Sdim handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3290245431Sdim continue; 3291245431Sdim } 3292245431Sdim 3293252723Sdim MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat); 3294252723Sdim 3295252723Sdim if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo)) 3296245431Sdim continue; 3297245431Sdim 3298245431Sdim#ifndef NDEBUG 3299245431Sdim dbgs() << "Formal Arg #" << I << " has unhandled type " 3300245431Sdim << EVT(ArgVT).getEVTString(); 3301245431Sdim#endif 3302245431Sdim llvm_unreachable(0); 3303245431Sdim } 3304245431Sdim} 3305245431Sdim 3306252723Sdimtemplate<typename Ty> 3307252723Sdimvoid MipsTargetLowering::MipsCC:: 3308252723SdimanalyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 3309252723Sdim const SDNode *CallNode, const Type *RetTy) const { 3310252723Sdim CCAssignFn *Fn; 3311252723Sdim 3312252723Sdim if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode)) 3313252723Sdim Fn = RetCC_F128Soft; 3314252723Sdim else 3315252723Sdim Fn = RetCC_Mips; 3316252723Sdim 3317252723Sdim for (unsigned I = 0, E = RetVals.size(); I < E; ++I) { 3318252723Sdim MVT VT = RetVals[I].VT; 3319252723Sdim ISD::ArgFlagsTy Flags = RetVals[I].Flags; 3320252723Sdim MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat); 3321252723Sdim 3322252723Sdim if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) { 3323252723Sdim#ifndef NDEBUG 3324252723Sdim dbgs() << "Call result #" << I << " has unhandled type " 3325252723Sdim << EVT(VT).getEVTString() << '\n'; 3326252723Sdim#endif 3327252723Sdim llvm_unreachable(0); 3328252723Sdim } 3329252723Sdim } 3330252723Sdim} 3331252723Sdim 3332252723Sdimvoid MipsTargetLowering::MipsCC:: 3333252723SdimanalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat, 3334252723Sdim const SDNode *CallNode, const Type *RetTy) const { 3335252723Sdim analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy); 3336252723Sdim} 3337252723Sdim 3338252723Sdimvoid MipsTargetLowering::MipsCC:: 3339252723SdimanalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat, 3340252723Sdim const Type *RetTy) const { 3341252723Sdim analyzeReturn(Outs, IsSoftFloat, 0, RetTy); 3342252723Sdim} 3343252723Sdim 3344263509Sdimvoid MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, 3345263509Sdim MVT LocVT, 3346263509Sdim CCValAssign::LocInfo LocInfo, 3347263509Sdim ISD::ArgFlagsTy ArgFlags) { 3348245431Sdim assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); 3349245431Sdim 3350245431Sdim struct ByValArgInfo ByVal; 3351252723Sdim unsigned RegSize = regSize(); 3352245431Sdim unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 3353245431Sdim unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 3354245431Sdim RegSize * 2); 3355245431Sdim 3356252723Sdim if (useRegsForByval()) 3357245431Sdim allocateRegs(ByVal, ByValSize, Align); 3358245431Sdim 3359245431Sdim // Allocate space on caller's stack. 3360245431Sdim ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 3361245431Sdim Align); 3362245431Sdim CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, 3363245431Sdim LocInfo)); 3364245431Sdim ByValArgs.push_back(ByVal); 3365245431Sdim} 3366245431Sdim 3367252723Sdimunsigned MipsTargetLowering::MipsCC::numIntArgRegs() const { 3368252723Sdim return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs); 3369252723Sdim} 3370252723Sdim 3371252723Sdimunsigned MipsTargetLowering::MipsCC::reservedArgArea() const { 3372252723Sdim return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0; 3373252723Sdim} 3374252723Sdim 3375252723Sdimconst uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const { 3376252723Sdim return IsO32 ? O32IntRegs : Mips64IntRegs; 3377252723Sdim} 3378252723Sdim 3379252723Sdimllvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const { 3380252723Sdim if (CallConv == CallingConv::Fast) 3381252723Sdim return CC_Mips_FastCC; 3382252723Sdim 3383263509Sdim if (SpecialCallingConv == Mips16RetHelperConv) 3384263509Sdim return CC_Mips16RetHelper; 3385263509Sdim return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN; 3386252723Sdim} 3387252723Sdim 3388252723Sdimllvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const { 3389263509Sdim return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg; 3390252723Sdim} 3391252723Sdim 3392252723Sdimconst uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const { 3393252723Sdim return IsO32 ? O32IntRegs : Mips64DPRegs; 3394252723Sdim} 3395252723Sdim 3396245431Sdimvoid MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, 3397245431Sdim unsigned ByValSize, 3398245431Sdim unsigned Align) { 3399252723Sdim unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs(); 3400252723Sdim const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs(); 3401245431Sdim assert(!(ByValSize % RegSize) && !(Align % RegSize) && 3402245431Sdim "Byval argument's size and alignment should be a multiple of" 3403245431Sdim "RegSize."); 3404245431Sdim 3405245431Sdim ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); 3406245431Sdim 3407245431Sdim // If Align > RegSize, the first arg register must be even. 3408245431Sdim if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { 3409245431Sdim CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); 3410245431Sdim ++ByVal.FirstIdx; 3411245431Sdim } 3412245431Sdim 3413245431Sdim // Mark the registers allocated. 3414245431Sdim for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); 3415245431Sdim ByValSize -= RegSize, ++I, ++ByVal.NumRegs) 3416245431Sdim CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3417245431Sdim} 3418245431Sdim 3419252723SdimMVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy, 3420252723Sdim const SDNode *CallNode, 3421252723Sdim bool IsSoftFloat) const { 3422252723Sdim if (IsSoftFloat || IsO32) 3423252723Sdim return VT; 3424252723Sdim 3425252723Sdim // Check if the original type was fp128. 3426252723Sdim if (originalTypeIsF128(OrigTy, CallNode)) { 3427252723Sdim assert(VT == MVT::i64); 3428252723Sdim return MVT::f64; 3429252723Sdim } 3430252723Sdim 3431252723Sdim return VT; 3432252723Sdim} 3433252723Sdim 3434245431Sdimvoid MipsTargetLowering:: 3435263509SdimcopyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, 3436245431Sdim SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3437245431Sdim SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3438245431Sdim const MipsCC &CC, const ByValArgInfo &ByVal) const { 3439245431Sdim MachineFunction &MF = DAG.getMachineFunction(); 3440245431Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 3441245431Sdim unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); 3442245431Sdim unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3443245431Sdim int FrameObjOffset; 3444245431Sdim 3445245431Sdim if (RegAreaSize) 3446245431Sdim FrameObjOffset = (int)CC.reservedArgArea() - 3447245431Sdim (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); 3448245431Sdim else 3449245431Sdim FrameObjOffset = ByVal.Address; 3450245431Sdim 3451245431Sdim // Create frame object. 3452245431Sdim EVT PtrTy = getPointerTy(); 3453245431Sdim int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3454245431Sdim SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3455245431Sdim InVals.push_back(FIN); 3456245431Sdim 3457245431Sdim if (!ByVal.NumRegs) 3458245431Sdim return; 3459245431Sdim 3460245431Sdim // Copy arg registers. 3461252723Sdim MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); 3462245431Sdim const TargetRegisterClass *RC = getRegClassFor(RegTy); 3463245431Sdim 3464245431Sdim for (unsigned I = 0; I < ByVal.NumRegs; ++I) { 3465245431Sdim unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; 3466252723Sdim unsigned VReg = addLiveIn(MF, ArgReg, RC); 3467245431Sdim unsigned Offset = I * CC.regSize(); 3468245431Sdim SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3469245431Sdim DAG.getConstant(Offset, PtrTy)); 3470245431Sdim SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3471245431Sdim StorePtr, MachinePointerInfo(FuncArg, Offset), 3472245431Sdim false, false, 0); 3473245431Sdim OutChains.push_back(Store); 3474245431Sdim } 3475245431Sdim} 3476245431Sdim 3477245431Sdim// Copy byVal arg to registers and stack. 3478245431Sdimvoid MipsTargetLowering:: 3479263509SdimpassByValArg(SDValue Chain, SDLoc DL, 3480252723Sdim std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 3481263509Sdim SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3482245431Sdim MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 3483245431Sdim const MipsCC &CC, const ByValArgInfo &ByVal, 3484245431Sdim const ISD::ArgFlagsTy &Flags, bool isLittle) const { 3485245431Sdim unsigned ByValSize = Flags.getByValSize(); 3486245431Sdim unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 3487245431Sdim unsigned RegSize = CC.regSize(); 3488245431Sdim unsigned Alignment = std::min(Flags.getByValAlign(), RegSize); 3489245431Sdim EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8); 3490245431Sdim 3491245431Sdim if (ByVal.NumRegs) { 3492245431Sdim const uint16_t *ArgRegs = CC.intArgRegs(); 3493245431Sdim bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize); 3494245431Sdim unsigned I = 0; 3495245431Sdim 3496245431Sdim // Copy words to registers. 3497245431Sdim for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) { 3498245431Sdim SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3499245431Sdim DAG.getConstant(Offset, PtrTy)); 3500245431Sdim SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3501245431Sdim MachinePointerInfo(), false, false, false, 3502245431Sdim Alignment); 3503245431Sdim MemOpChains.push_back(LoadVal.getValue(1)); 3504245431Sdim unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3505245431Sdim RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3506245431Sdim } 3507245431Sdim 3508245431Sdim // Return if the struct has been fully copied. 3509245431Sdim if (ByValSize == Offset) 3510245431Sdim return; 3511245431Sdim 3512245431Sdim // Copy the remainder of the byval argument with sub-word loads and shifts. 3513245431Sdim if (LeftoverBytes) { 3514245431Sdim assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) && 3515245431Sdim "Size of the remainder should be smaller than RegSize."); 3516245431Sdim SDValue Val; 3517245431Sdim 3518245431Sdim for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0; 3519245431Sdim Offset < ByValSize; LoadSize /= 2) { 3520245431Sdim unsigned RemSize = ByValSize - Offset; 3521245431Sdim 3522245431Sdim if (RemSize < LoadSize) 3523245431Sdim continue; 3524245431Sdim 3525245431Sdim // Load subword. 3526245431Sdim SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3527245431Sdim DAG.getConstant(Offset, PtrTy)); 3528245431Sdim SDValue LoadVal = 3529245431Sdim DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, 3530245431Sdim MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 3531245431Sdim false, false, Alignment); 3532245431Sdim MemOpChains.push_back(LoadVal.getValue(1)); 3533245431Sdim 3534245431Sdim // Shift the loaded value. 3535245431Sdim unsigned Shamt; 3536245431Sdim 3537245431Sdim if (isLittle) 3538245431Sdim Shamt = TotalSizeLoaded; 3539245431Sdim else 3540245431Sdim Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8; 3541245431Sdim 3542245431Sdim SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3543245431Sdim DAG.getConstant(Shamt, MVT::i32)); 3544245431Sdim 3545245431Sdim if (Val.getNode()) 3546245431Sdim Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3547245431Sdim else 3548245431Sdim Val = Shift; 3549245431Sdim 3550245431Sdim Offset += LoadSize; 3551245431Sdim TotalSizeLoaded += LoadSize; 3552245431Sdim Alignment = std::min(Alignment, LoadSize); 3553245431Sdim } 3554245431Sdim 3555245431Sdim unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3556245431Sdim RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3557245431Sdim return; 3558245431Sdim } 3559245431Sdim } 3560245431Sdim 3561245431Sdim // Copy remainder of byval arg to it with memcpy. 3562245431Sdim unsigned MemCpySize = ByValSize - Offset; 3563245431Sdim SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3564245431Sdim DAG.getConstant(Offset, PtrTy)); 3565245431Sdim SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3566245431Sdim DAG.getIntPtrConstant(ByVal.Address)); 3567263509Sdim Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy), 3568263509Sdim Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, 3569245431Sdim MachinePointerInfo(0), MachinePointerInfo(0)); 3570245431Sdim MemOpChains.push_back(Chain); 3571245431Sdim} 3572245431Sdim 3573263509Sdimvoid MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3574263509Sdim const MipsCC &CC, SDValue Chain, 3575263509Sdim SDLoc DL, SelectionDAG &DAG) const { 3576245431Sdim unsigned NumRegs = CC.numIntArgRegs(); 3577245431Sdim const uint16_t *ArgRegs = CC.intArgRegs(); 3578245431Sdim const CCState &CCInfo = CC.getCCInfo(); 3579245431Sdim unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); 3580245431Sdim unsigned RegSize = CC.regSize(); 3581252723Sdim MVT RegTy = MVT::getIntegerVT(RegSize * 8); 3582245431Sdim const TargetRegisterClass *RC = getRegClassFor(RegTy); 3583245431Sdim MachineFunction &MF = DAG.getMachineFunction(); 3584245431Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 3585245431Sdim MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3586245431Sdim 3587245431Sdim // Offset of the first variable argument from stack pointer. 3588245431Sdim int VaArgOffset; 3589245431Sdim 3590245431Sdim if (NumRegs == Idx) 3591245431Sdim VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); 3592245431Sdim else 3593263509Sdim VaArgOffset = (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); 3594245431Sdim 3595245431Sdim // Record the frame index of the first variable argument 3596245431Sdim // which is a value necessary to VASTART. 3597245431Sdim int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3598245431Sdim MipsFI->setVarArgsFrameIndex(FI); 3599245431Sdim 3600245431Sdim // Copy the integer registers that have not been used for argument passing 3601245431Sdim // to the argument register save area. For O32, the save area is allocated 3602245431Sdim // in the caller's stack frame, while for N32/64, it is allocated in the 3603245431Sdim // callee's stack frame. 3604245431Sdim for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { 3605252723Sdim unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3606245431Sdim SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3607245431Sdim FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3608245431Sdim SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 3609245431Sdim SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3610245431Sdim MachinePointerInfo(), false, false, 0); 3611245431Sdim cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0); 3612245431Sdim OutChains.push_back(Store); 3613245431Sdim } 3614245431Sdim} 3615