Searched refs:Op0 (Results 26 - 50 of 60) sorted by relevance

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/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.cpp786 uint32_t Op0 = 3, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; local
792 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
814 uint32_t Op0 = (Bits >> 14) & 0x3; local
822 if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
827 assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
/freebsd-9.3-release/contrib/llvm/lib/AsmParser/
H A DLLParser.cpp3421 Value *Op0;
3423 if (ParseTypeAndValue(Op0, Loc, PFS)) return true;
3425 if (BasicBlock *BB = dyn_cast<BasicBlock>(Op0)) {
3430 if (Op0->getType() != Type::getInt1Ty(Context))
3439 Inst = BranchInst::Create(Op1, Op2, Op0);
3757 Value *Op0, *Op1, *Op2;
3758 if (ParseTypeAndValue(Op0, Loc, PFS) ||
3765 if (const char *Reason = SelectInst::areInvalidOperands(Op0, Op1, Op2))
3768 Inst = SelectInst::Create(Op0, Op1, Op2);
3794 Value *Op0, *Op
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp2055 SDValue Op0 = Node->getOperand(0);
2057 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2058 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2063 User->getOperand(0) == Op0 &&
2167 SDValue Op0 = Node->getOperand(0);
2168 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2169 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2252 SDValue Op0,
2255 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2275 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBi
[all...]
H A DDAGCombiner.cpp310 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1);
2664 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); local
2667 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2693 Op0 == Op1 && LL.getValueType().isInteger() &&
2694 Op0 == ISD::SETNE && ((cast<ConstantSDNode>(LR)->isNullValue() &&
2711 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
3203 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); local
3206 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3234 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
4720 SDValue Op0
6922 SDValue Op0 = N1.getOperand(0); local
6969 SDValue Op0 = TheXor->getOperand(0); local
7193 SDValue Op0 = Use->getOperand(0), Op1 = Use->getOperand(1); local
10884 isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) argument
[all...]
H A DLegalizeVectorTypes.cpp138 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); local
142 Op0.getValueType(), Op0, Op1, Op2);
169 SDValue Op0 = GetScalarizedVector(N->getOperand(0)); local
171 Op0, DAG.getValueType(NewVT),
172 DAG.getValueType(Op0.getValueType()),
1058 SDValue Op0 = Inputs[InputUsed[0]]; local
1063 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
/freebsd-9.3-release/contrib/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp2019 GenericValue Op0 = getOperandValue(CE->getOperand(0), SF); local
2024 case Instruction::Add: Dest.IntVal = Op0.IntVal + Op1.IntVal; break;
2025 case Instruction::Sub: Dest.IntVal = Op0.IntVal - Op1.IntVal; break;
2026 case Instruction::Mul: Dest.IntVal = Op0.IntVal * Op1.IntVal; break;
2027 case Instruction::FAdd: executeFAddInst(Dest, Op0, Op1, Ty); break;
2028 case Instruction::FSub: executeFSubInst(Dest, Op0, Op1, Ty); break;
2029 case Instruction::FMul: executeFMulInst(Dest, Op0, Op1, Ty); break;
2030 case Instruction::FDiv: executeFDivInst(Dest, Op0, Op1, Ty); break;
2031 case Instruction::FRem: executeFRemInst(Dest, Op0, Op1, Ty); break;
2032 case Instruction::SDiv: Dest.IntVal = Op0
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp488 Value *Op0 = CI->getArgOperand(0); local
489 Type *IntPtr = TD.getIntPtrType(Op0->getType());
493 Ops[0] = Op0;
/freebsd-9.3-release/contrib/llvm/lib/IR/
H A DAutoUpgrade.cpp294 Value *Op0 = CI->getArgOperand(0); local
315 Rep = Builder.CreateShuffleVector(Op0, Op0, ConstantVector::get(Idxs));
H A DInstructions.cpp62 const char *SelectInst::areInvalidOperands(Value *Op0, Value *Op1, Value *Op2) { argument
66 if (VectorType *VT = dyn_cast<VectorType>(Op0->getType())) {
68 if (VT->getElementType() != Type::getInt1Ty(Op0->getContext()))
76 } else if (Op0->getType() != Type::getInt1Ty(Op0->getContext())) {
1972 Value *Op0 = BO->getOperand(0); local
1974 if (isConstantAllOnes(Op0)) return Op1;
1977 return Op0;
/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h725 void InitOperands(SDUse *Ops, const SDValue &Op0) {
727 Ops[0].setInitial(Op0);
734 void InitOperands(SDUse *Ops, const SDValue &Op0, const SDValue &Op1) {
736 Ops[0].setInitial(Op0);
745 void InitOperands(SDUse *Ops, const SDValue &Op0, const SDValue &Op1,
748 Ops[0].setInitial(Op0);
759 void InitOperands(SDUse *Ops, const SDValue &Op0, const SDValue &Op1,
762 Ops[0].setInitial(Op0);
/freebsd-9.3-release/contrib/llvm/lib/Analysis/
H A DConstantFolding.cpp557 /// SymbolicallyEvaluateBinop - One of Op0/Op1 is a constant expression.
561 static Constant *SymbolicallyEvaluateBinop(unsigned Opc, Constant *Op0, argument
571 unsigned BitWidth = DL->getTypeSizeInBits(Op0->getType()->getScalarType());
574 ComputeMaskedBits(Op0, KnownZero0, KnownOne0, DL);
577 // All the bits of Op0 that the 'and' could be masking are already zero.
578 return Op0;
588 return ConstantInt::get(Op0->getType(), KnownOne);
598 if (IsConstantOffsetFromGlobal(Op0, GV1, Offs1, *DL))
601 unsigned OpSize = DL->getTypeSizeInBits(Op0->getType());
606 return ConstantInt::get(Op0
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H A DValueTracking.cpp47 static void ComputeMaskedBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW, argument
52 if (ConstantInt *CLHS = dyn_cast<ConstantInt>(Op0)) {
82 llvm::ComputeMaskedBits(Op0, LHSKnownZero, LHSKnownOne, TD, Depth+1);
133 static void ComputeMaskedBitsMul(Value *Op0, Value *Op1, bool NSW, argument
139 ComputeMaskedBits(Op0, KnownZero2, KnownOne2, TD, Depth+1);
147 if (Op0 == Op1) {
162 isKnownNonZero(Op0, TD, Depth)) ||
1352 Value *Op0 = I->getOperand(0); local
1358 // Turn Op0 << Op1 into Op0 *
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/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp401 SDValue Op0 = N->getOperand(0); local
406 CurDAG->ComputeMaskedBits(Op0, LKZ, LKO);
413 unsigned Op0Opc = Op0.getOpcode();
422 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
423 Op0.getOperand(0).getOpcode() == ISD::SRL) {
426 std::swap(Op0, Op1);
434 std::swap(Op0, Op1);
461 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
/freebsd-9.3-release/contrib/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp902 Value *Op0 = ICI->getOperand(0), *Op1 = ICI->getOperand(1); local
911 Value *Sh = ConstantInt::get(Op0->getType(),
912 Op0->getType()->getScalarSizeInBits()-1);
913 Value *In = Builder->CreateAShr(Op0, Sh, Op0->getName()+".lobit");
929 ComputeMaskedBits(Op0, KnownZero, KnownOne);
981 Op0->getType() == CI.getType()) {
986 Value *In = Builder->CreateAShr(Op0, VSh, Op0->getName()+".lobit");
H A DInstCombine.h165 Instruction *FoldShiftByConstant(Value *Op0, ConstantInt *Op1,
H A DInstCombineCalls.cpp598 Value *Op0 = Builder->CreateBitCast(II->getArgOperand(0), local
602 Value *Result = UndefValue::get(Op0->getType());
617 Builder->CreateExtractElement(Idx < 16 ? Op0 : Op1,
/freebsd-9.3-release/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1190 // Return true if it is better to swap comparison operands Op0 and Op1.
1192 static bool shouldSwapCmpOperands(SDValue Op0, SDValue Op1, argument
1195 if (Op0.getValueType() == MVT::f128)
1212 if ((isNaturalMemoryOperand(Op0, ICmpType) && Op0.hasOneUse()) &&
1462 unsigned Extend, SDValue Op0, SDValue Op1,
1464 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
1466 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
1473 // half of a GR128 pair. Op0 an
1461 lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL, unsigned Extend, SDValue Op0, SDValue Op1, SDValue &Hi, SDValue &Lo) argument
1477 lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT, unsigned Extend, unsigned Opcode, SDValue Op0, SDValue Op1, SDValue &Even, SDValue &Odd) argument
1853 SDValue Op0 = Op.getOperand(0); local
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp3888 SDValue Op0 = SVOp->getOperand(0); local
3898 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3901 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
5758 SDValue Op0 = In.getOperand(0); local
5762 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5767 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
6837 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2), local
6845 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
9260 SDValue Op0 local
9654 EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SelectionDAG &DAG) const argument
9705 SDValue Op0 = And.getOperand(0); local
9774 translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0, SDValue &Op1) argument
9848 SDValue Op0 = Op.getOperand(0); local
9883 SDValue Op0 = Op.getOperand(0); local
10086 SDValue Op0 = Op.getOperand(0); local
13138 SDValue Op0 = Op.getOperand(0); local
17964 SDValue Op0 = N0.getOperand(0); local
18985 SDValue Op0 = N->getOperand(0); local
19083 SDValue Op0 = N->getOperand(0); local
19097 SDValue Op0 = N->getOperand(0); local
[all...]
H A DX86ISelLowering.h976 /// Emit nodes that will be selected as "test Op0,Op0", or something
978 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
980 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
982 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
H A DX86MCInstLower.cpp263 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg(); local
268 if (Op0 == X86::AX && Op1 == X86::AL)
272 if (Op0 == X86::EAX && Op1 == X86::AX)
276 if (Op0 == X86::RAX && Op1 == X86::EAX)
H A DX86FastISel.cpp957 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, argument
959 unsigned Op0Reg = getRegForValue(Op0);
964 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext()));
999 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0.
1055 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); local
1057 std::swap(Op0, Op1);
1059 // Emit a compare of Op0/Op1.
1060 if (!X86FastEmitCompare(Op0, Op1, VT))
1140 bool SwapArgs; // false -> compare Op0, Op
1176 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); local
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2520 SDValue Op0, Op1; local
2549 Op0 = RHS;
2551 Op0 = LHS;
2593 Op0 = LHS;
2599 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC));
2615 Op0 = RHS;
2617 Op0 = LHS;
2624 Op0 = LHS;
2688 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGT));
2697 DAG.getNode(Opcode, DL, VT, Op0, Op
4269 SDValue Op0 = V1.getOperand(0); local
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Bitcode/Reader/
H A DBitcodeReader.cpp1407 Constant *Op0 = ValueList.getConstantFwdRef(Record[1], OpTy);
1410 V = ConstantExpr::getExtractElement(Op0, Op1);
1417 Constant *Op0 = ValueList.getConstantFwdRef(Record[0], OpTy);
1422 V = ConstantExpr::getInsertElement(Op0, Op1, Op2);
1429 Constant *Op0 = ValueList.getConstantFwdRef(Record[0], OpTy);
1434 V = ConstantExpr::getShuffleVector(Op0, Op1, Op2);
1443 Constant *Op0 = ValueList.getConstantFwdRef(Record[1], OpTy);
1448 V = ConstantExpr::getShuffleVector(Op0, Op1, Op2);
1457 Constant *Op0 = ValueList.getConstantFwdRef(Record[1], OpTy);
1461 V = ConstantExpr::getFCmp(Record[3], Op0, Op
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1526 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, local
1531 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
4175 SDValue Op0 = Op.getOperand(0); local
4204 TmpOp0 = Op0;
4207 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4213 TmpOp0 = Op0;
4216 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4241 AndOp = Op0;
4242 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4251 Op0
5480 SDValue Op0 = Op.getOperand(0); local
5741 SDValue Op0; local
8953 SDValue Op0 = N->getOperand(0); local
9285 SDValue Op0 = N->getOperand(0); local
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp2424 SDValue Op0, Op1; local
2429 if (SelectDirectAddr(Op, Op0)) {
2430 OutOps.push_back(Op0);
2434 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
2435 OutOps.push_back(Op0);

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