Searched refs:i32 (Results 126 - 138 of 138) sorted by relevance
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.h | 121 /// The CMPB instruction (takes two operands of i32 or i64). 246 /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the 248 /// implement truncation of i32 or i64 to i1. 418 /// operand #2 constant i32 0 or 1, to indicate whether needs to patch 419 /// the most significant bit for signed i32 458 /// i32. 464 /// or i32. 672 return MVT::i32; 881 /// register X1 to i32 by referencing its sub-register R1.
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeFloatTypes.cpp | 12 // "soft float". For example, turning f32 arithmetic into operations using i32. 563 assert(N->getOperand(1 + Offset).getValueType() == MVT::i32 && 905 // a larger type, eg: fp -> i32. Even if it is legal, no libcall may exactly 1607 // When promoting partial word types to i32 we must honor the signedness, 1609 if (SrcVT.bitsLE(MVT::i32)) { 1612 MVT::i32, Src); 1650 case MVT::i32:
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H A D | DAGCombiner.cpp | 1252 /// i32 since i16 instructions are longer. 1320 /// i32 since i16 instructions are longer. 3710 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 4814 // (i64 zero_extend (and (srl (i32 (trunc i64:x)), K)), KMask) 5494 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 5547 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 5767 assert(N->getOpcode() == ISD::OR && VT == MVT::i32 && 5768 "MatchBSwapHWordOrAndAnd: expecting i32"); 5813 if (VT != MVT::i32) 6834 /// i32 va [all...] |
H A D | SelectionDAG.cpp | 4038 case ISD::SEXTLOAD: // e.g. i16->i32 = '17' bits known. 4041 case ISD::ZEXTLOAD: // e.g. i16->i32 = '16' bits known. 4461 if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) 4552 else if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) 5912 MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; 7460 SDValue Ops[] = { Chain, Ptr, SV, getTargetConstant(Align, dl, MVT::i32) }; 8229 SDValue SRIdxVal = getTargetConstant(SRIdx, DL, MVT::i32); 8239 SDValue SRIdxVal = getTargetConstant(SRIdx, DL, MVT::i32); 9349 // %s = shufflevector <8 x i32> %op, <8 x i32> unde [all...] |
H A D | SelectionDAGISel.cpp | 2074 Ops.push_back(CurDAG->getTargetConstant(NewFlags, DL, MVT::i32));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 167 /// i32, corresponds to X86::PEXTRB. 171 /// i32, corresponds to X86::PEXTRW. 1014 return VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || 1170 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 1205 /// from i32 to i8 but not from i32 to i16.
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H A D | X86InstrInfo.cpp | 6666 case MVT::i32:
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/freebsd-13-stable/sys/contrib/openzfs/cmd/zpool/ |
H A D | zpool_main.c | 9507 uint32_t i32; local 9550 (void) nvpair_value_int32(nvp, (void *)&i32); 9551 printf(gettext("0x%x"), i32); 9555 (void) nvpair_value_uint32(nvp, &i32); 9556 printf(gettext("0x%x"), i32);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.cpp | 748 Register NewLoopCount = TII->createVR(MF, MVT::i32); 2017 } else if (VT == MVT::i32 || VT == MVT::f32) { 2676 case MVT::i32:
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDILCFGStructurizer.cpp | 1232 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 365 /// TODO: Let fence operands be of i32 type and remove this. 848 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep 944 /// turns into 4 EVT::i32 values with both PPC and X86. 1484 /// Example: (i16 (trunc (i32 (load x))) -> i16 load x 2440 /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 2493 /// %E = zext i8 %L to i32 2563 /// b = trunc i64 a to i32 2565 /// d = trunc i64 c to i32 2567 /// b = load i32* addr1 2568 /// d = load i32* addr [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenDAGPatterns.cpp | 285 // { iPTR } * { i32 } -> { i32 } 286 // { iPTR } * { i32 i64 } -> { iPTR } 288 // { iPTR i32 } * { i32 } -> { i32 } 289 // { iPTR i32 } * { i32 i64 } -> { i32 i64 } 290 // { iPTR i32 } * { i3 [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineScheduler.cpp | 2802 for (unsigned VT = MVT::i32; VT > (unsigned)MVT::i1; --VT) {
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