Lines Matching refs:i32
1252 /// i32 since i16 instructions are longer.
1320 /// i32 since i16 instructions are longer.
3710 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
4814 // (i64 zero_extend (and (srl (i32 (trunc i64:x)), K)), KMask)
5494 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
5547 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
5767 assert(N->getOpcode() == ISD::OR && VT == MVT::i32 &&
5768 "MatchBSwapHWordOrAndAnd: expecting i32");
5813 if (VT != MVT::i32)
6834 /// i32 val = ...
6840 /// *((i32)p) = val;
6843 /// i32 val = ...
6849 /// *((i32)p) = BSWAP(val);
6866 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
6997 /// i32 val = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24)
6999 /// i32 val = *((i32)a)
7002 /// i32 val = (a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]
7004 /// i32 val = BSWAP(*((i32)a))
7012 /// t25: i32 = add t4, Constant:i32<2>
7016 /// t29: i32 = zero_extend t28
7017 /// t32: i32 = shl t29, Constant:i8<8>
7018 /// t33: i32 = or t23, t32
7027 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
7116 // patterns to a couple of i32 loads on 32 bit targets.
7994 // (srl (mul (zext i32:$a to i64), (zext i32:$a to i64)), 32) -> (mulhu $a, $b)
7995 // (sra (mul (sext i32:$a to i64), (sext i32:$a to i64)), 32) -> (mulhs $a, $b)
8455 // %b = and i32 %a, 2
8456 // %c = srl i32 %b, 1
8457 // brcond i32 %c ...
8791 // i32 X > -1 ? C1 : -1 --> (X >>s 31) | C1
10049 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
10054 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
10055 // bits, just sext from i32.
10059 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
10060 // bits, just truncate to i32.
10225 // sext i32 (0 - (zext i8 X to i32)) to i64 --> 0 - (zext i8 X to i64)
10234 // sext i32 ((zext i8 X to i32) + (-1)) to i64 --> (zext i8 X to i64) + (-1)
10539 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
11213 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
11214 // i32 y = TRUNCATE(i64 x)
11217 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
14069 // %b = and i32 %a, 2
14070 // %c = srl i32 %b, 1
14071 // brcond i32 %c ...
14076 // %b = and i32 %a, 2
15205 /// i = load i32
15206 /// f = bitcast i32 i to float
15515 V.getValueType() != MVT::i32 &&
15584 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
16938 if ((isTypeLegal(MVT::i32) && !LegalOperations && ST->isSimple()) ||
16939 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
16943 MVT::i32);
16960 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
16965 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, SDLoc(CFP), MVT::i32);
16966 SDValue Hi = DAG.getConstant(Val >> 32, SDLoc(CFP), MVT::i32);
17232 /// (store (or (zext (bitcast F to i32) to i64),
17237 /// For pair of {i32, i32}, i64 store --> two i32 stores.
17238 /// For pair of {i32, i16}, i64 store --> two i32 stores.
17239 /// For pair of {i16, i16}, i32 store --> two i16 stores.
17240 /// For pair of {i16, i8}, i32 store --> two i16 stores.
17764 // extract_elt (v2i32 (bitcast i64:x)), BCTruncElt -> i32 (trunc i64:x)
17773 // trunc i64 X to i32
18516 // t10: i32 = extract_vector_elt t1, Constant:i64<0>
18517 // t11: i32 = extract_vector_elt t2, Constant:i64<0>
18518 // t12: i32 = extract_vector_elt t3, Constant:i64<0>
18519 // t13: i32 = extract_vector_elt t1, Constant:i64<1>