Searched refs:getRegClass (Results 76 - 100 of 192) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNNSAReassign.cpp195 if (MRI->getRegClass(Reg) != &AMDGPU::VGPR_32RegClass || Op.getSubReg())
H A DSIInstrInfo.h827 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
1035 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1041 return RI.getRegClass(TID.OpInfo[OpNum].RegClass);
1062 auto *RC = MRI.getRegClass(P.Reg);
H A DSIFoldOperands.cpp256 const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg());
653 const TargetRegisterClass *DestRC = MRI->getRegClass(DestReg);
657 const TargetRegisterClass * SrcRC = MRI->getRegClass(SrcReg);
874 TRI->getRegClass(FoldDesc.OpInfo[0].RegClass);
879 const TargetRegisterClass *UseRC = MRI->getRegClass(UseReg);
H A DAMDGPUMachineCFGStructurizer.cpp1409 MRI->createVirtualRegister(MRI->getRegClass(DestReg));
1934 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg);
2001 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg);
2061 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
2177 MRI->getRegClass(CurrentBackedgeReg);
2314 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn);
2451 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest);
2741 MRI->createVirtualRegister(MRI->getRegClass(InReg));
2742 Register NewInReg = MRI->createVirtualRegister(MRI->getRegClass(InReg));
H A DR600MachineScheduler.cpp215 return MRI->getRegClass(Reg) == RC;
H A DSIFormMemoryClauses.cpp162 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp123 const TargetRegisterClass *RC = TII->getRegClass(MID, OpIdx, TRI, MF);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp38 assert(RBGPR.covers(*TRI.getRegClass(X86::GR64RegClassID)) &&
H A DX86SpeculativeLoadHardening.cpp847 return TII.getRegClass(MCID, Index, &TII.getRegisterInfo(), MF);
1662 auto *OpRC = MRI->getRegClass(OpReg);
1869 auto *RC = MRI->getRegClass(Reg);
1917 auto *RC = MRI->getRegClass(Reg);
1967 auto *DefRC = MRI->getRegClass(OldDefReg);
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h219 return shouldTrackSubRegLiveness(*getRegClass(VReg));
580 /// constrainRegClass(ToReg, getRegClass(FromReg))
583 /// *MRI.getRegClass(FromReg), MRI)
631 const TargetRegisterClass *getRegClass(Register Reg) const { function in class:llvm::MachineRegisterInfo
647 /// the select pass, using getRegClass is safe.
1180 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineSink.cpp231 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
232 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
685 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
H A DRegAllocPBQP.cpp604 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
756 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
882 const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg));
H A DTwoAddressInstructionPass.cpp1211 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1334 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1405 const TargetRegisterClass *RC = MRI->getRegClass(RegB);
1408 assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
1414 assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
H A DRegisterCoalescer.cpp458 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
460 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
465 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
466 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
875 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
1292 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
1333 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
1816 auto SrcRC = MRI->getRegClass(CP.getSrcReg());
1817 auto DstRC = MRI->getRegClass(CP.getDstReg());
3938 << TRI->getRegClassName(MRI->getRegClass(Re
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H A DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp699 const TargetRegisterClass *RC = MRI->getRegClass(R);
842 const TargetRegisterClass *RC = MRI->getRegClass(DR);
1000 const TargetRegisterClass *RC = MRI->getRegClass(DefR);
H A DHexagonStoreWidening.cpp443 const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI, *MF);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp427 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);
428 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID);
429 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp88 const MCRegisterClass &RC = MRI.getRegClass(RCE.RegisterClassID);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp288 MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI, MF));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMIPeephole.cpp104 if (MRI->getRegClass(Reg) == &BPF::GPRRegClass)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp286 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
579 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
1646 const TargetRegisterClass *RC = MRI->getRegClass(vr);
1665 const TargetRegisterClass *RC = TRI->getRegClass(i);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyAsmPrinter.cpp59 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp172 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
173 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
464 const TargetRegisterClass *RC = MRI.getRegClass(RegC);
1110 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1143 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
1201 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
1202 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
1204 MRI.getRegClass(FirstRe
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp911 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
919 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
927 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
937 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
945 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
953 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
961 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
972 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
980 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
988 return RegIdx.RegInfo->getRegClass(ClassI
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