/freebsd-13-stable/sys/arm/freescale/imx/ |
H A D | imx_iomux.c | 114 WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val) function 143 WR4(sc, reg, val); 165 WR4(sc, cfg->mux_reg, cfg->mux_val | sion); 168 WR4(sc, cfg->padconf_reg, cfg->padconf_val); 289 WR4(iomux_sc, regaddr, val); 306 WR4(iomux_sc, regaddr, val);
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H A D | imx6_src.c | 66 WR4(struct src_softc *sc, bus_size_t off, uint32_t val) function 83 WR4(src_sc, SRC_SCR, reg);
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H A D | imx_spi.c | 162 WR4(struct spi_softc *sc, bus_size_t offset, uint32_t value) function 242 WR4(sc, ECSPI_CTLREG, sc->ctlreg); 258 WR4(sc, ECSPI_CFGREG, reg); 265 WR4(sc, ECSPI_DMAREG, reg); 289 WR4(sc, ECSPI_TXDATA, sc->txbuf[sc->txidx++]); 312 WR4(sc, ECSPI_STATREG, status); /* Clear w1c bits. */ 360 WR4(sc, ECSPI_INTREG, sc->intreg); 397 WR4(sc, ECSPI_INTREG, sc->intreg); 450 WR4(sc, ECSPI_CTLREG, 0); 560 WR4(s [all...] |
/freebsd-13-stable/sys/arm/nvidia/ |
H A D | tegra_mc.c | 99 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro 150 WR4(sc, MC_INTSTATUS, stat); 184 WR4(sc, MC_INTSTATUS, stat); 192 WR4(sc, MC_INTMASK, 0); 193 WR4(sc, MC_INTSTATUS, MC_INT_INT_MASK); 263 WR4(sc, MC_INTMASK, MC_INT_INT_MASK);
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H A D | tegra_usbphy.c | 311 #define WR4(sc, offs, val) \ macro 338 WR4(sc, CTRL_USB_HOSTPC1_DEVLC, val); 358 WR4(sc, IF_USB_SUSP_CTRL, val); 362 WR4(sc, UTMIP_TX_CFG0, val); 369 WR4(sc, UTMIP_HSRX_CFG0, val); 374 WR4(sc, UTMIP_HSRX_CFG1, val); 379 WR4(sc, UTMIP_DEBOUNCE_CFG0, val); 383 WR4(sc, UTMIP_MISC_CFG0, val); 389 WR4(sc, IF_USB_SUSP_CTRL, val); 393 WR4(s [all...] |
H A D | tegra_lic.c | 67 #define WR4(_sc, _b, _r, _v) bus_write_4((_sc)->mem_res[_b], (_r), (_v)) macro 231 WR4(sc, i, LIC_CPU_IER_CLR, 0xFFFFFFFF); 232 WR4(sc, i, LIC_CPU_IEP_CLASS, 0);
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/freebsd-13-stable/sys/dev/sdhci/ |
H A D | fsl_sdhci.c | 199 WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val) function 400 WR4(sc, SDHC_PROT_CTRL, val32); 418 WR4(sc, off & ~3, val32); 458 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 459 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); 478 WR4(sc, USDHC_MIX_CONTROL, val32); 489 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 497 WR4(sc, off & ~3, val32); 510 WR4(sc, off, val); 594 WR4(s [all...] |
H A D | sdhci_fsl_fdt.c | 57 #define WR4 (sc->write) macro 179 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN); 210 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 337 WR4(sc, SDHCI_FSL_PROT_CTRL, val32); 348 WR4(sc, off & ~3, val32); 377 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 384 WR4(sc, off & ~3, val32); 413 WR4(sc, off, val); 537 WR4(sc, SDHCI_FSL_PROT_CTRL, val | buf_order); 544 WR4(s [all...] |
H A D | sdhci.c | 91 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) macro 335 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 336 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 571 WR4(slot, SDHCI_BUFFER, data); 585 WR4(slot, SDHCI_BUFFER, data); 658 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 659 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 1250 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); 1398 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); 1399 WR4(slo [all...] |
/freebsd-13-stable/sys/arm/allwinner/ |
H A D | aw_thermal.c | 380 #define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) macro 407 WR4(sc, THS_CALIB0, calib[0]); 409 WR4(sc, THS_CALIB1, calib[1]); 412 WR4(sc, THS_CTRL1, ADC_CALI_EN); 413 WR4(sc, THS_CTRL0, sc->conf->adc_acquire_time); 414 WR4(sc, THS_CTRL2, sc->conf->adc_acquire_time << SENSOR_ACQ1_SHIFT); 417 WR4(sc, THS_INTC, sc->conf->thermal_per << THS_THERMAL_PER_SHIFT); 420 WR4(sc, THS_FILTER, sc->conf->filter); 423 WR4(sc, THS_INTS, RD4(sc, THS_INTS)); 424 WR4(s [all...] |
H A D | if_awg.c | 77 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val)) macro 244 WR4(sc, EMAC_MII_CMD, 272 WR4(sc, EMAC_MII_DATA, val); 273 WR4(sc, EMAC_MII_CMD, 339 WR4(sc, EMAC_BASIC_CTL_0, val); 345 WR4(sc, EMAC_RX_CTL_0, val); 353 WR4(sc, EMAC_TX_FLOW_CTL, val); 449 WR4(sc, EMAC_ADDR_HIGH(0), machi); 450 WR4(sc, EMAC_ADDR_LOW(0), maclo); 453 WR4(s [all...] |
/freebsd-13-stable/sys/arm/mv/ |
H A D | mv_thermal.c | 128 #define WR4(sc, reg, val) \ macro 170 WR4(sc, CONTROL0, reg); 186 WR4(sc, CONTROL0, reg); 192 WR4(sc, CONTROL0, reg); 233 WR4(sc, CONTROL0, reg); 249 WR4(sc, CONTROL1, reg); 254 WR4(sc, CONTROL0, reg);
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H A D | mv_ap806_sei.c | 92 #define WR4(sc, reg, val) bus_write_4((sc)->mem_res, (reg), (val)) macro 108 WR4(sc, GICP_SEMR(sisrc->irq), tmp); 117 WR4(sc, GICP_SECR(sisrc->irq), GICP_SECR_BIT(sisrc->irq)); 336 WR4(sc, GICP_SEMR0, 0xFFFFFFFF); 337 WR4(sc, GICP_SEMR1, 0xFFFFFFFF);
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H A D | mv_cp110_clock.c | 140 #define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val)) macro 296 WR4(sc, addr, val); 322 WR4(sc, addr, reg);
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/freebsd-13-stable/sys/arm64/rockchip/ |
H A D | rk_pcie_phy.c | 101 #define WR4(sc, reg, mask, val) \ macro 110 WR4(sc, GRF_SOC_CON8, 0x7FF, 116 WR4(sc, GRF_SOC_CON8, 1, 1); 119 WR4(sc, GRF_SOC_CON8, 1, 0); 129 WR4(sc, GRF_SOC_CON8, 0x3FF, reg << 1); 158 WR4(sc, GRF_SOC_CON_5_PCIE, CON_5_PCIE_IDLE_OFF(i), 0); 221 WR4(sc, GRF_SOC_CON_5_PCIE,
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/freebsd-13-stable/sys/arm/nvidia/tegra124/ |
H A D | tegra124_pmc.c | 137 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro 209 WR4(sc, PMC_PWRGATE_TOGGLE, 236 WR4(sc, PMC_GPU_RG_CNTRL, 0); 250 WR4(sc, PMC_REMOVE_CLAMPING_CMD, PMC_REMOVE_CLAMPING_CMD_PARTID(swid)); 516 WR4(sc, PMC_CNTRL, reg); 524 WR4(sc, PMC_CNTRL, reg); 529 WR4(sc, PMC_CNTRL, reg); 537 WR4(sc, PMC_IO_DPD_STATUS, reg); 541 WR4(sc, PMC_IO_DPD2_STATUS, reg);
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H A D | tegra124_clk_super.c | 213 WR4(sc, sc->base_reg, reg); 217 WR4(sc, sc->base_reg, reg); 224 WR4(sc, sc->base_reg, reg);
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/freebsd-13-stable/sys/dev/tpm/ |
H A D | tpm20.h | 167 WR4(struct tpm_sc *sc, bus_size_t off, uint32_t val) function 176 WR4(sc, off, RD4(sc, off) & val); 188 WR4(sc, off, RD4(sc, off) | val);
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H A D | tpm_crb.c | 293 WR4(sc, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CMD); 301 WR4(sc, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CLEAR); 333 WR4(sc, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CLEAR); 371 WR4(sc, TPM_CRB_CTRL_START, TPM_CRB_CTRL_START_CMD);
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/freebsd-13-stable/sys/mips/mediatek/ |
H A D | mtk_xhci.c | 252 #define WR4(_sc, _reg, _val) bus_write_4((_sc)->sc_io_res, (_reg), (_val)) macro 254 WR4((_sc), (_reg), (RD4((_sc), (_reg)) & ~(_clr)) | (_set)) 283 WR4(sc, USB_HDMA_CFG, USB_HDMA_CFG_MT7621_VAL); 284 WR4(sc, U3_LTSSM_TIMING_PARAM3, U3_LTSSM_TIMING_VAL); 285 WR4(sc, SYNC_HS_EOF, SYNC_HS_EOF_VAL); 286 WR4(sc, USB_IP_SPAR0, USB_IP_SPAR0_VAL);
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/freebsd-13-stable/sys/riscv/riscv/ |
H A D | plic.c | 105 #define WR4(sc, reg, val) \ macro 191 WR4(sc, PLIC_PRIORITY(src->irq), 0); 203 WR4(sc, PLIC_PRIORITY(src->irq), 1); 300 WR4(sc, PLIC_PRIORITY(irq), 0); 365 WR4(sc, PLIC_THRESHOLD(sc, cpu), 0); 397 WR4(sc, PLIC_CLAIM(sc, cpu), src->irq); 432 WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg); 449 WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg);
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/freebsd-13-stable/sys/arm64/rockchip/clk/ |
H A D | rk_clk_fract.c | 41 #define WR4(_clk, off, val) \ macro 176 WR4(clk, sc->gate_offset, val); 255 WR4(clk, sc->offset, sc->numerator << 16 | sc->denominator);
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/freebsd-13-stable/sys/dev/mwl/ |
H A D | mwlhal.c | 223 WR4(struct mwl_hal_priv *mh, bus_size_t off, uint32_t val) function 493 WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE, 509 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0); 513 WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, mask); 530 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY); 2176 WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1); 2353 WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr); 2356 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL); 2442 WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET); 2453 WR4(m [all...] |
/freebsd-13-stable/sys/arm/ti/ |
H A D | ti_sdhci.c | 158 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) function 275 WR4(sc, off & ~3, val32); 303 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 317 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 324 WR4(sc, off & ~3, val32); 333 WR4(sc, off, val);
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/freebsd-13-stable/sys/dev/extres/clk/ |
H A D | clk_mux.c | 43 #define WR4(_clk, off, val) \ macro
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