Lines Matching refs:WR4
77 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
244 WR4(sc, EMAC_MII_CMD,
272 WR4(sc, EMAC_MII_DATA, val);
273 WR4(sc, EMAC_MII_CMD,
339 WR4(sc, EMAC_BASIC_CTL_0, val);
345 WR4(sc, EMAC_RX_CTL_0, val);
353 WR4(sc, EMAC_TX_FLOW_CTL, val);
449 WR4(sc, EMAC_ADDR_HIGH(0), machi);
450 WR4(sc, EMAC_ADDR_LOW(0), maclo);
453 WR4(sc, EMAC_RX_HASH_0, hash[1]);
454 WR4(sc, EMAC_RX_HASH_1, hash[0]);
457 WR4(sc, EMAC_RX_FRM_FLT, val);
470 WR4(sc, EMAC_BASIC_CTL_1, val);
491 WR4(sc, EMAC_TX_CTL_0, tx);
492 WR4(sc, EMAC_RX_CTL_0, rx);
543 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN);
550 WR4(sc, EMAC_INT_EN, 0);
572 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME);
576 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD);
590 WR4(sc, EMAC_TX_CTL_1, val);
597 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN);
601 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN);
938 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr);
939 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr);
953 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START);
1329 WR4(sc, EMAC_INT_STA, val);
1371 WR4(sc, EMAC_INT_STA, val);
1857 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);