1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD$");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/rman.h>
40#include <sys/lock.h>
41#include <sys/mutex.h>
42
43#include <machine/bus.h>
44#include <machine/resource.h>
45#include <machine/intr.h>
46
47#include <dev/extres/clk/clk_fixed.h>
48#include <dev/extres/clk/clk_gate.h>
49#include <dev/extres/syscon/syscon.h>
50
51#include <dev/ofw/ofw_bus.h>
52#include <dev/ofw/ofw_bus_subr.h>
53
54#include <arm/mv/mv_cp110_clock.h>
55
56#include "clkdev_if.h"
57#include "syscon_if.h"
58
59/* Clocks */
60static struct clk_fixed_def cp110_clk_pll_0 = {
61	.clkdef.id = CP110_PLL_0,
62	.freq = 1000000000,
63};
64
65static const char *clk_parents_0[] = {"cp110-pll0-0"};
66static const char *clk_parents_1[] = {"cp110-pll0-1"};
67
68static struct clk_fixed_def cp110_clk_ppv2_core = {
69	.clkdef.id = CP110_PPV2_CORE,
70	.clkdef.parent_cnt = 1,
71	.mult = 1,
72	.div = 3,
73};
74
75static struct clk_fixed_def cp110_clk_x2core = {
76	.clkdef.id = CP110_X2CORE,
77	.clkdef.parent_cnt = 1,
78	.mult = 1,
79	.div = 2,
80};
81
82static const char *core_parents_0[] = {"cp110-x2core-0"};
83static const char *core_parents_1[] = {"cp110-x2core-1"};
84
85static struct clk_fixed_def cp110_clk_core = {
86	.clkdef.id = CP110_CORE,
87	.clkdef.parent_cnt = 1,
88	.mult = 1,
89	.div = 2,
90};
91
92static struct clk_fixed_def cp110_clk_sdio = {
93	.clkdef.id = CP110_SDIO,
94	.clkdef.parent_cnt = 1,
95	.mult = 2,
96	.div = 5,
97};
98
99/* Gates */
100
101static struct cp110_gate cp110_gates[] = {
102	CCU_GATE(CP110_GATE_AUDIO, "cp110-gate-audio", 0)
103	CCU_GATE(CP110_GATE_COMM_UNIT, "cp110-gate-comm_unit", 1)
104	/* CCU_GATE(CP110_GATE_NAND, "cp110-gate-nand", 2) */
105	CCU_GATE(CP110_GATE_PPV2, "cp110-gate-ppv2", 3)
106	CCU_GATE(CP110_GATE_SDIO, "cp110-gate-sdio", 4)
107	CCU_GATE(CP110_GATE_MG, "cp110-gate-mg", 5)
108	CCU_GATE(CP110_GATE_MG_CORE, "cp110-gate-mg_core", 6)
109	CCU_GATE(CP110_GATE_XOR1, "cp110-gate-xor1", 7)
110	CCU_GATE(CP110_GATE_XOR0, "cp110-gate-xor0", 8)
111	CCU_GATE(CP110_GATE_GOP_DP, "cp110-gate-gop_dp", 9)
112	CCU_GATE(CP110_GATE_PCIE_X1_0, "cp110-gate-pcie_x10", 11)
113	CCU_GATE(CP110_GATE_PCIE_X1_1, "cp110-gate-pcie_x11", 12)
114	CCU_GATE(CP110_GATE_PCIE_X4, "cp110-gate-pcie_x4", 13)
115	CCU_GATE(CP110_GATE_PCIE_XOR, "cp110-gate-pcie_xor", 14)
116	CCU_GATE(CP110_GATE_SATA, "cp110-gate-sata", 15)
117	CCU_GATE(CP110_GATE_SATA_USB, "cp110-gate-sata_usb", 16)
118	CCU_GATE(CP110_GATE_MAIN, "cp110-gate-main", 17)
119	CCU_GATE(CP110_GATE_SDMMC_GOP, "cp110-gate-sdmmc_gop", 18)
120	CCU_GATE(CP110_GATE_SLOW_IO, "cp110-gate-slow_io", 21)
121	CCU_GATE(CP110_GATE_USB3H0, "cp110-gate-usb3h0", 22)
122	CCU_GATE(CP110_GATE_USB3H1, "cp110-gate-usb3h1", 23)
123	CCU_GATE(CP110_GATE_USB3DEV, "cp110-gate-usb3dev", 24)
124	CCU_GATE(CP110_GATE_EIP150, "cp110-gate-eip150", 25)
125	CCU_GATE(CP110_GATE_EIP197, "cp110-gate-eip197", 26)
126};
127
128struct mv_cp110_clock_softc {
129	device_t		dev;
130	struct syscon		*syscon;
131	struct mtx		mtx;
132};
133
134static struct ofw_compat_data compat_data[] = {
135	{"marvell,cp110-clock", 1},
136	{NULL,             0}
137};
138
139#define	RD4(sc, reg)		SYSCON_READ_4((sc)->syscon, (reg))
140#define	WR4(sc, reg, val)	SYSCON_WRITE_4((sc)->syscon, (reg), (val))
141
142static char *
143mv_cp110_clock_name(device_t dev, const char *name)
144{
145	char *clkname = NULL;
146	int unit;
147
148	unit = device_get_unit(dev);
149	if (asprintf(&clkname, M_DEVBUF, "%s-%d", name, unit) <= 0)
150		panic("Cannot generate unique clock name for %s\n", name);
151	return (clkname);
152}
153
154static int
155mv_cp110_clock_probe(device_t dev)
156{
157
158	if (!ofw_bus_status_okay(dev))
159		return (ENXIO);
160
161	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
162		return (ENXIO);
163
164	device_set_desc(dev, "Marvell CP110 Clock Controller");
165	return (BUS_PROBE_DEFAULT);
166}
167
168static int
169cp110_ofw_map(struct clkdom *clkdom, uint32_t ncells,
170    phandle_t *cells, struct clknode **clk)
171{
172	int id = 0;
173
174	if (ncells != 2)
175		return (ENXIO);
176
177	id = cells[1];
178	if (cells[0] == 1)
179		id += CP110_MAX_CLOCK;
180
181	*clk = clknode_find_by_id(clkdom, id);
182
183	return (0);
184}
185
186static int
187mv_cp110_clock_attach(device_t dev)
188{
189	struct mv_cp110_clock_softc *sc;
190	struct clkdom *clkdom;
191	struct clk_gate_def def;
192	char *pll0_name;
193	int unit, i;
194
195	sc = device_get_softc(dev);
196	sc->dev = dev;
197
198	if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 ||
199	    sc->syscon == NULL) {
200		device_printf(dev, "cannot get syscon for device\n");
201		return (ENXIO);
202	}
203
204	unit = device_get_unit(dev);
205	if (unit > 1) {
206		device_printf(dev, "Bogus cp110-system-controller unit %d\n", unit);
207		return (ENXIO);
208	}
209
210	mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
211
212	clkdom = clkdom_create(dev);
213	clkdom_set_ofw_mapper(clkdom, cp110_ofw_map);
214
215	pll0_name = mv_cp110_clock_name(dev, "cp110-pll0");
216	cp110_clk_pll_0.clkdef.name = pll0_name;
217	clknode_fixed_register(clkdom, &cp110_clk_pll_0);
218
219	cp110_clk_ppv2_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-ppv2");
220	cp110_clk_ppv2_core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1;
221	clknode_fixed_register(clkdom, &cp110_clk_ppv2_core);
222
223	cp110_clk_x2core.clkdef.name = mv_cp110_clock_name(dev, "cp110-x2core");
224	cp110_clk_x2core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1;
225	clknode_fixed_register(clkdom, &cp110_clk_x2core);
226
227	cp110_clk_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-core");
228	cp110_clk_core.clkdef.parent_names = (unit == 0) ? core_parents_0 : core_parents_1;
229	clknode_fixed_register(clkdom, &cp110_clk_core);
230
231	/* NAND missing */
232
233	cp110_clk_sdio.clkdef.name = mv_cp110_clock_name(dev, "cp110-sdio");
234	cp110_clk_sdio.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1;
235	clknode_fixed_register(clkdom, &cp110_clk_sdio);
236
237	for (i = 0; i < nitems(cp110_gates); i++) {
238		if (cp110_gates[i].name == NULL)
239			continue;
240
241		memset(&def, 0, sizeof(def));
242		def.clkdef.id = CP110_MAX_CLOCK + i;
243		def.clkdef.name = mv_cp110_clock_name(dev, cp110_gates[i].name);
244		def.clkdef.parent_cnt = 1;
245		def.offset = CP110_CLOCK_GATING_OFFSET;
246		def.shift = cp110_gates[i].shift;
247		def.mask = 1;
248		def.on_value = 1;
249		def.off_value = 0;
250
251		switch (i) {
252		case CP110_GATE_MG:
253		case CP110_GATE_GOP_DP:
254		case CP110_GATE_PPV2:
255			def.clkdef.parent_names = &cp110_clk_ppv2_core.clkdef.name;
256			break;
257		case CP110_GATE_SDIO:
258			def.clkdef.parent_names = &cp110_clk_sdio.clkdef.name;
259			break;
260		case CP110_GATE_MAIN:
261		case CP110_GATE_PCIE_XOR:
262		case CP110_GATE_PCIE_X4:
263		case CP110_GATE_EIP150:
264		case CP110_GATE_EIP197:
265			def.clkdef.parent_names = &cp110_clk_x2core.clkdef.name;
266			break;
267		default:
268			def.clkdef.parent_names = &cp110_clk_core.clkdef.name;
269			break;
270		}
271
272		clknode_gate_register(clkdom, &def);
273	}
274
275	clkdom_finit(clkdom);
276
277	if (bootverbose)
278		clkdom_dump(clkdom);
279
280	return (0);
281}
282
283static int
284mv_cp110_clock_detach(device_t dev)
285{
286
287	return (EBUSY);
288}
289
290static int
291mv_cp110_clock_write_4(device_t dev, bus_addr_t addr, uint32_t val)
292{
293	struct mv_cp110_clock_softc *sc;
294
295	sc = device_get_softc(dev);
296	WR4(sc, addr, val);
297	return (0);
298}
299
300static int
301mv_cp110_clock_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
302{
303	struct mv_cp110_clock_softc *sc;
304
305	sc = device_get_softc(dev);
306
307	*val = RD4(sc, addr);
308	return (0);
309}
310
311static int
312mv_cp110_clock_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set)
313{
314	struct mv_cp110_clock_softc *sc;
315	uint32_t reg;
316
317	sc = device_get_softc(dev);
318
319	reg = RD4(sc, addr);
320	reg &= ~clr;
321	reg |= set;
322	WR4(sc, addr, reg);
323
324	return (0);
325}
326
327static void
328mv_cp110_clock_device_lock(device_t dev)
329{
330	struct mv_cp110_clock_softc *sc;
331
332	sc = device_get_softc(dev);
333	mtx_lock(&sc->mtx);
334}
335
336static void
337mv_cp110_clock_device_unlock(device_t dev)
338{
339	struct mv_cp110_clock_softc *sc;
340
341	sc = device_get_softc(dev);
342	mtx_unlock(&sc->mtx);
343}
344
345static device_method_t mv_cp110_clock_methods[] = {
346	/* Device interface */
347	DEVMETHOD(device_probe,		mv_cp110_clock_probe),
348	DEVMETHOD(device_attach,	mv_cp110_clock_attach),
349	DEVMETHOD(device_detach,	mv_cp110_clock_detach),
350
351	/* clkdev interface */
352	DEVMETHOD(clkdev_write_4,	mv_cp110_clock_write_4),
353	DEVMETHOD(clkdev_read_4,	mv_cp110_clock_read_4),
354	DEVMETHOD(clkdev_modify_4,	mv_cp110_clock_modify_4),
355	DEVMETHOD(clkdev_device_lock,	mv_cp110_clock_device_lock),
356	DEVMETHOD(clkdev_device_unlock,	mv_cp110_clock_device_unlock),
357
358	DEVMETHOD_END
359};
360
361static devclass_t mv_cp110_clock_devclass;
362
363static driver_t mv_cp110_clock_driver = {
364	"mv_cp110_clock",
365	mv_cp110_clock_methods,
366	sizeof(struct mv_cp110_clock_softc),
367};
368
369EARLY_DRIVER_MODULE(mv_cp110_clock, simplebus, mv_cp110_clock_driver,
370    mv_cp110_clock_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE);
371