1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2020 Alstom Group. 5 * Copyright (c) 2020 Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* eSDHC controller driver for NXP QorIQ Layerscape SoCs. */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD$"); 33 34#include <sys/param.h> 35#include <sys/endian.h> 36#include <sys/kernel.h> 37#include <sys/module.h> 38#include <sys/rman.h> 39#include <sys/sysctl.h> 40#include <sys/taskqueue.h> 41 42#include <machine/bus.h> 43#include <machine/resource.h> 44 45#include <dev/extres/clk/clk.h> 46#include <dev/mmc/bridge.h> 47#include <dev/mmc/mmcbrvar.h> 48#include <dev/ofw/ofw_bus.h> 49#include <dev/ofw/ofw_bus_subr.h> 50#include <dev/sdhci/sdhci.h> 51#include <dev/sdhci/sdhci_fdt_gpio.h> 52 53#include "mmcbr_if.h" 54#include "sdhci_if.h" 55 56#define RD4 (sc->read) 57#define WR4 (sc->write) 58 59#define SDHCI_FSL_PRES_STATE 0x24 60#define SDHCI_FSL_PRES_SDSTB (1 << 3) 61#define SDHCI_FSL_PRES_COMPAT_MASK 0x000f0f07 62 63#define SDHCI_FSL_PROT_CTRL 0x28 64#define SDHCI_FSL_PROT_CTRL_WIDTH_1BIT (0 << 1) 65#define SDHCI_FSL_PROT_CTRL_WIDTH_4BIT (1 << 1) 66#define SDHCI_FSL_PROT_CTRL_WIDTH_8BIT (2 << 1) 67#define SDHCI_FSL_PROT_CTRL_WIDTH_MASK (3 << 1) 68#define SDHCI_FSL_PROT_CTRL_BYTE_SWAP (0 << 4) 69#define SDHCI_FSL_PROT_CTRL_BYTE_NATIVE (2 << 4) 70#define SDHCI_FSL_PROT_CTRL_BYTE_MASK (3 << 4) 71#define SDHCI_FSL_PROT_CTRL_DMA_MASK (3 << 8) 72 73#define SDHCI_FSL_SYS_CTRL 0x2c 74#define SDHCI_FSL_CLK_IPGEN (1 << 0) 75#define SDHCI_FSL_CLK_SDCLKEN (1 << 3) 76#define SDHCI_FSL_CLK_DIVIDER_MASK 0x000000f0 77#define SDHCI_FSL_CLK_DIVIDER_SHIFT 4 78#define SDHCI_FSL_CLK_PRESCALE_MASK 0x0000ff00 79#define SDHCI_FSL_CLK_PRESCALE_SHIFT 8 80 81#define SDHCI_FSL_WTMK_LVL 0x44 82#define SDHCI_FSL_WTMK_RD_512B (0 << 0) 83#define SDHCI_FSL_WTMK_WR_512B (0 << 15) 84 85#define SDHCI_FSL_HOST_VERSION 0xfc 86#define SDHCI_FSL_CAPABILITIES2 0x114 87 88#define SDHCI_FSL_ESDHC_CTRL 0x40c 89#define SDHCI_FSL_ESDHC_CTRL_SNOOP (1 << 6) 90#define SDHCI_FSL_ESDHC_CTRL_CLK_DIV2 (1 << 19) 91 92struct sdhci_fsl_fdt_softc { 93 device_t dev; 94 const struct sdhci_fsl_fdt_soc_data *soc_data; 95 struct resource *mem_res; 96 struct resource *irq_res; 97 void *irq_cookie; 98 uint32_t baseclk_hz; 99 struct sdhci_fdt_gpio *gpio; 100 struct sdhci_slot slot; 101 bool slot_init_done; 102 uint32_t cmd_and_mode; 103 uint16_t sdclk_bits; 104 105 uint32_t (* read)(struct sdhci_fsl_fdt_softc *, bus_size_t); 106 void (* write)(struct sdhci_fsl_fdt_softc *, bus_size_t, uint32_t); 107}; 108 109struct sdhci_fsl_fdt_soc_data { 110 int quirks; 111}; 112 113static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1046a_soc_data = { 114 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_BROKEN_AUTO_STOP 115}; 116 117static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_gen_data = { 118 .quirks = 0, 119}; 120 121static const struct ofw_compat_data sdhci_fsl_fdt_compat_data[] = { 122 {"fsl,ls1046a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1046a_soc_data}, 123 {"fsl,esdhc", (uintptr_t)&sdhci_fsl_fdt_gen_data}, 124 {NULL, 0} 125}; 126 127static uint32_t 128read_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off) 129{ 130 131 return (be32toh(bus_read_4(sc->mem_res, off))); 132} 133 134static void 135write_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val) 136{ 137 138 bus_write_4(sc->mem_res, off, htobe32(val)); 139} 140 141static uint32_t 142read_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off) 143{ 144 145 return (bus_read_4(sc->mem_res, off)); 146} 147 148static void 149write_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val) 150{ 151 152 bus_write_4(sc->mem_res, off, val); 153} 154 155 156static uint16_t 157sdhci_fsl_fdt_get_clock(struct sdhci_fsl_fdt_softc *sc) 158{ 159 uint16_t val; 160 161 val = sc->sdclk_bits | SDHCI_CLOCK_INT_EN; 162 if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB) 163 val |= SDHCI_CLOCK_INT_STABLE; 164 if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN) 165 val |= SDHCI_CLOCK_CARD_EN; 166 167 return (val); 168} 169 170static void 171fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc *sc, uint16_t val) 172{ 173 uint32_t div, freq, prescale, val32; 174 175 sc->sdclk_bits = val & SDHCI_DIVIDERS_MASK; 176 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 177 178 if ((val & SDHCI_CLOCK_CARD_EN) == 0) { 179 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN); 180 return; 181 } 182 183 div = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) | 184 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) << 185 SDHCI_DIVIDER_MASK_LEN; 186 if (div == 0) 187 freq = sc->baseclk_hz; 188 else 189 freq = sc->baseclk_hz / (2 * div); 190 191 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16); ) 192 prescale <<= 1; 193 for (div = 1; freq < sc->baseclk_hz / (prescale * div); ) 194 ++div; 195 196#ifdef DEBUG 197 device_printf(sc->dev, 198 "Desired SD/MMC freq: %d, actual: %d; base %d prescale %d divisor %d\n", 199 freq, sc->baseclk_hz / (prescale * div), 200 sc->baseclk_hz, prescale, div); 201#endif 202 203 prescale >>= 1; 204 div -= 1; 205 206 val32 &= ~(SDHCI_FSL_CLK_DIVIDER_MASK | SDHCI_FSL_CLK_PRESCALE_MASK); 207 val32 |= div << SDHCI_FSL_CLK_DIVIDER_SHIFT; 208 val32 |= prescale << SDHCI_FSL_CLK_PRESCALE_SHIFT; 209 val32 |= SDHCI_FSL_CLK_IPGEN | SDHCI_FSL_CLK_SDCLKEN; 210 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 211} 212 213static uint8_t 214sdhci_fsl_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 215{ 216 struct sdhci_fsl_fdt_softc *sc; 217 uint32_t wrk32, val32; 218 219 sc = device_get_softc(dev); 220 221 switch (off) { 222 case SDHCI_HOST_CONTROL: 223 wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL); 224 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | 225 SDHCI_CTRL_FORCE_CARD); 226 if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_4BIT) 227 val32 |= SDHCI_CTRL_4BITBUS; 228 else if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_8BIT) 229 val32 |= SDHCI_CTRL_8BITBUS; 230 return (val32); 231 case SDHCI_POWER_CONTROL: 232 return (SDHCI_POWER_ON | SDHCI_POWER_300); 233 default: 234 break; 235 } 236 237 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX); 238} 239 240static uint16_t 241sdhci_fsl_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 242{ 243 struct sdhci_fsl_fdt_softc *sc; 244 uint32_t val32; 245 246 sc = device_get_softc(dev); 247 248 switch (off) { 249 case SDHCI_CLOCK_CONTROL: 250 return (sdhci_fsl_fdt_get_clock(sc)); 251 case SDHCI_HOST_VERSION: 252 return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX); 253 case SDHCI_TRANSFER_MODE: 254 return (sc->cmd_and_mode & UINT16_MAX); 255 case SDHCI_COMMAND_FLAGS: 256 return (sc->cmd_and_mode >> 16); 257 case SDHCI_SLOT_INT_STATUS: 258 /* 259 * eSDHC hardware manages only a single slot. 260 * Synthesize a slot interrupt status register for slot 1 below. 261 */ 262 val32 = RD4(sc, SDHCI_INT_STATUS); 263 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); 264 return (!!val32); 265 default: 266 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX); 267 } 268} 269 270static uint32_t 271sdhci_fsl_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 272{ 273 struct sdhci_fsl_fdt_softc *sc; 274 uint32_t wrk32, val32; 275 276 sc = device_get_softc(dev); 277 278 if (off == SDHCI_BUFFER) 279 return (bus_read_4(sc->mem_res, off)); 280 if (off == SDHCI_CAPABILITIES2) 281 off = SDHCI_FSL_CAPABILITIES2; 282 283 val32 = RD4(sc, off); 284 285 switch (off) { 286 case SDHCI_CAPABILITIES: 287 val32 &= ~(SDHCI_CAN_DO_SUSPEND | SDHCI_CAN_VDD_180); 288 break; 289 case SDHCI_PRESENT_STATE: 290 wrk32 = val32; 291 val32 &= SDHCI_FSL_PRES_COMPAT_MASK; 292 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; 293 val32 |= (wrk32 << 1) & SDHCI_STATE_CMD; 294 break; 295 default: 296 break; 297 } 298 299 return (val32); 300} 301 302static void 303sdhci_fsl_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 304 uint32_t *data, bus_size_t count) 305{ 306 struct sdhci_fsl_fdt_softc *sc; 307 308 sc = device_get_softc(dev); 309 bus_read_multi_4(sc->mem_res, off, data, count); 310} 311 312static void 313sdhci_fsl_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 314 uint8_t val) 315{ 316 struct sdhci_fsl_fdt_softc *sc; 317 uint32_t val32; 318 319 sc = device_get_softc(dev); 320 321 switch (off) { 322 case SDHCI_HOST_CONTROL: 323 val32 = RD4(sc, SDHCI_FSL_PROT_CTRL); 324 val32 &= ~SDHCI_FSL_PROT_CTRL_WIDTH_MASK; 325 val32 |= (val & SDHCI_CTRL_LED); 326 327 if (val & SDHCI_CTRL_8BITBUS) 328 val32 |= SDHCI_FSL_PROT_CTRL_WIDTH_8BIT; 329 else 330 /* Bus width is 1-bit when this flag is not set. */ 331 val32 |= (val & SDHCI_CTRL_4BITBUS); 332 /* Enable SDMA by masking out this field. */ 333 val32 &= ~SDHCI_FSL_PROT_CTRL_DMA_MASK; 334 val32 &= ~(SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD); 335 val32 |= (val & (SDHCI_CTRL_CARD_DET | 336 SDHCI_CTRL_FORCE_CARD)); 337 WR4(sc, SDHCI_FSL_PROT_CTRL, val32); 338 return; 339 case SDHCI_POWER_CONTROL: 340 return; 341 case SDHCI_SOFTWARE_RESET: 342 val &= ~SDHCI_RESET_ALL; 343 /* FALLTHROUGH. */ 344 default: 345 val32 = RD4(sc, off & ~3); 346 val32 &= ~(UINT8_MAX << (off & 3) * 8); 347 val32 |= (val << (off & 3) * 8); 348 WR4(sc, off & ~3, val32); 349 return; 350 } 351} 352 353static void 354sdhci_fsl_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 355 uint16_t val) 356{ 357 struct sdhci_fsl_fdt_softc *sc; 358 uint32_t val32; 359 360 sc = device_get_softc(dev); 361 362 switch (off) { 363 case SDHCI_CLOCK_CONTROL: 364 fsl_sdhc_fdt_set_clock(sc, val); 365 return; 366 /* 367 * eSDHC hardware combines command and mode into a single 368 * register. Cache it here, so that command isn't written 369 * until after mode. 370 */ 371 case SDHCI_TRANSFER_MODE: 372 sc->cmd_and_mode = val; 373 return; 374 case SDHCI_COMMAND_FLAGS: 375 sc->cmd_and_mode = 376 (sc->cmd_and_mode & UINT16_MAX) | (val << 16); 377 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 378 sc->cmd_and_mode = 0; 379 return; 380 default: 381 val32 = RD4(sc, off & ~3); 382 val32 &= ~(UINT16_MAX << (off & 3) * 8); 383 val32 |= ((val & UINT16_MAX) << (off & 3) * 8); 384 WR4(sc, off & ~3, val32); 385 return; 386 } 387} 388 389static void 390sdhci_fsl_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 391 uint32_t val) 392{ 393 struct sdhci_fsl_fdt_softc *sc; 394 395 sc = device_get_softc(dev); 396 397 switch (off) { 398 case SDHCI_BUFFER: 399 bus_write_4(sc->mem_res, off, val); 400 return; 401 /* 402 * eSDHC hardware lacks support for the SDMA buffer boundary 403 * feature and instead generates SDHCI_INT_DMA_END interrupts 404 * after each completed DMA data transfer. 405 * Since this duplicates the SDHCI_INT_DATA_END functionality, 406 * mask out the unneeded SDHCI_INT_DMA_END interrupt. 407 */ 408 case SDHCI_INT_ENABLE: 409 case SDHCI_SIGNAL_ENABLE: 410 val &= ~SDHCI_INT_DMA_END; 411 /* FALLTHROUGH. */ 412 default: 413 WR4(sc, off, val); 414 return; 415 } 416} 417 418static void 419sdhci_fsl_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot, 420 bus_size_t off, uint32_t *data, bus_size_t count) 421{ 422 struct sdhci_fsl_fdt_softc *sc; 423 424 sc = device_get_softc(dev); 425 bus_write_multi_4(sc->mem_res, off, data, count); 426} 427 428static void 429sdhci_fsl_fdt_irq(void *arg) 430{ 431 struct sdhci_fsl_fdt_softc *sc; 432 433 sc = arg; 434 sdhci_generic_intr(&sc->slot); 435 return; 436} 437 438static int 439sdhci_fsl_fdt_get_ro(device_t bus, device_t child) 440{ 441 struct sdhci_fsl_fdt_softc *sc; 442 443 sc = device_get_softc(bus); 444 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 445} 446 447static bool 448sdhci_fsl_fdt_get_card_present(device_t dev, struct sdhci_slot *slot) 449{ 450 struct sdhci_fsl_fdt_softc *sc; 451 452 sc = device_get_softc(dev); 453 return (sdhci_fdt_gpio_get_present(sc->gpio)); 454} 455 456static int 457sdhci_fsl_fdt_attach(device_t dev) 458{ 459 struct sdhci_fsl_fdt_softc *sc; 460 uint32_t val, buf_order; 461 uintptr_t ocd_data; 462 uint64_t clk_hz; 463 phandle_t node; 464 int rid, ret; 465 clk_t clk; 466 467 node = ofw_bus_get_node(dev); 468 sc = device_get_softc(dev); 469 ocd_data = ofw_bus_search_compatible(dev, 470 sdhci_fsl_fdt_compat_data)->ocd_data; 471 sc->soc_data = (struct sdhci_fsl_fdt_soc_data *)ocd_data; 472 sc->dev = dev; 473 sc->slot.quirks = sc->soc_data->quirks; 474 475 rid = 0; 476 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 477 RF_ACTIVE); 478 if (sc->mem_res == NULL) { 479 device_printf(dev, 480 "Could not allocate resources for controller\n"); 481 return (ENOMEM); 482 } 483 484 rid = 0; 485 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 486 RF_ACTIVE); 487 if (sc->irq_res == NULL) { 488 device_printf(dev, 489 "Could not allocate irq resources for controller\n"); 490 ret = ENOMEM; 491 goto err_free_mem; 492 } 493 494 ret = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 495 NULL, sdhci_fsl_fdt_irq, sc, &sc->irq_cookie); 496 if (ret != 0) { 497 device_printf(dev, "Could not setup IRQ handler\n"); 498 goto err_free_irq_res; 499 } 500 501 ret = clk_get_by_ofw_index(dev, node, 0, &clk); 502 if (ret != 0) { 503 device_printf(dev, "Parent clock not found\n"); 504 goto err_free_irq; 505 } 506 507 ret = clk_get_freq(clk, &clk_hz); 508 if (ret != 0) { 509 device_printf(dev, 510 "Could not get parent clock frequency\n"); 511 goto err_free_irq; 512 } 513 514 sc->baseclk_hz = clk_hz / 2; 515 516 /* Figure out eSDHC block endianness before we touch any HW regs. */ 517 if (OF_hasprop(node, "little-endian")) { 518 sc->read = read_le; 519 sc->write = write_le; 520 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_NATIVE; 521 } else { 522 sc->read = read_be; 523 sc->write = write_be; 524 buf_order = SDHCI_FSL_PROT_CTRL_BYTE_SWAP; 525 } 526 527 /* 528 * Setting this register affects byte order in SDHCI_BUFFER only. 529 * If the eSDHC block is connected over a big-endian bus, the data 530 * read from/written to the buffer will be already byte swapped. 531 * In such a case, setting SDHCI_FSL_PROT_CTRL_BYTE_SWAP will convert 532 * the byte order again, resulting in a native byte order. 533 * The read/write callbacks accommodate for this behavior. 534 */ 535 val = RD4(sc, SDHCI_FSL_PROT_CTRL); 536 val &= ~SDHCI_FSL_PROT_CTRL_BYTE_MASK; 537 WR4(sc, SDHCI_FSL_PROT_CTRL, val | buf_order); 538 539 /* 540 * Gate the SD clock and set its source to peripheral clock / 2. 541 * The frequency in baseclk_hz is set to match this. 542 */ 543 val = RD4(sc, SDHCI_CLOCK_CONTROL); 544 WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN); 545 val = RD4(sc, SDHCI_FSL_ESDHC_CTRL); 546 WR4(sc, SDHCI_FSL_ESDHC_CTRL, val | SDHCI_FSL_ESDHC_CTRL_CLK_DIV2); 547 sc->slot.max_clk = sc->baseclk_hz; 548 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); 549 550 /* 551 * Set the buffer watermark level to 128 words (512 bytes) for both 552 * read and write. The hardware has a restriction that when the read or 553 * write ready status is asserted, that means you can read exactly the 554 * number of words set in the watermark register before you have to 555 * re-check the status and potentially wait for more data. The main 556 * sdhci driver provides no hook for doing status checking on less than 557 * a full block boundary, so we set the watermark level to be a full 558 * block. Reads and writes where the block size is less than the 559 * watermark size will work correctly too, no need to change the 560 * watermark for different size blocks. However, 128 is the maximum 561 * allowed for the watermark, so PIO is limitted to 512 byte blocks. 562 */ 563 WR4(sc, SDHCI_FSL_WTMK_LVL, SDHCI_FSL_WTMK_WR_512B | 564 SDHCI_FSL_WTMK_RD_512B); 565 566 ret = sdhci_init_slot(dev, &sc->slot, 0); 567 if (ret != 0) 568 goto err_free_gpio; 569 sc->slot_init_done = true; 570 sdhci_start_slot(&sc->slot); 571 572 return (bus_generic_attach(dev)); 573 574err_free_gpio: 575 sdhci_fdt_gpio_teardown(sc->gpio); 576err_free_irq: 577 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie); 578err_free_irq_res: 579 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res); 580err_free_mem: 581 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 582 return (ret); 583} 584 585static int 586sdhci_fsl_fdt_detach(device_t dev) 587{ 588 struct sdhci_fsl_fdt_softc *sc; 589 590 sc = device_get_softc(dev); 591 if (sc->slot_init_done) 592 sdhci_cleanup_slot(&sc->slot); 593 if (sc->gpio != NULL) 594 sdhci_fdt_gpio_teardown(sc->gpio); 595 if (sc->irq_cookie != NULL) 596 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie); 597 if (sc->irq_res != NULL) 598 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res); 599 if (sc->mem_res != NULL) 600 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 601 return (0); 602} 603 604static int 605sdhci_fsl_fdt_probe(device_t dev) 606{ 607 608 if (!ofw_bus_status_okay(dev)) 609 return (ENXIO); 610 611 if (!ofw_bus_search_compatible(dev, 612 sdhci_fsl_fdt_compat_data)->ocd_data) 613 return (ENXIO); 614 615 device_set_desc(dev, "NXP QorIQ Layerscape eSDHC controller"); 616 return (BUS_PROBE_DEFAULT); 617} 618 619static int 620sdhci_fsl_fdt_read_ivar(device_t bus, device_t child, int which, 621 uintptr_t *result) 622{ 623 struct sdhci_slot *slot = device_get_ivars(child); 624 625 if (which == MMCBR_IVAR_MAX_DATA && (slot->opt & SDHCI_HAVE_DMA)) { 626 /* 627 * In the absence of SDMA buffer boundary functionality, 628 * limit the maximum data length per read/write command 629 * to bounce buffer size. 630 */ 631 *result = howmany(slot->sdma_bbufsz, 512); 632 return (0); 633 } 634 return (sdhci_generic_read_ivar(bus, child, which, result)); 635} 636 637static const device_method_t sdhci_fsl_fdt_methods[] = { 638 /* Device interface. */ 639 DEVMETHOD(device_probe, sdhci_fsl_fdt_probe), 640 DEVMETHOD(device_attach, sdhci_fsl_fdt_attach), 641 DEVMETHOD(device_detach, sdhci_fsl_fdt_detach), 642 643 /* Bus interface. */ 644 DEVMETHOD(bus_read_ivar, sdhci_fsl_fdt_read_ivar), 645 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 646 647 /* MMC bridge interface. */ 648 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 649 DEVMETHOD(mmcbr_request, sdhci_generic_request), 650 DEVMETHOD(mmcbr_get_ro, sdhci_fsl_fdt_get_ro), 651 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 652 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 653 654 /* SDHCI accessors. */ 655 DEVMETHOD(sdhci_read_1, sdhci_fsl_fdt_read_1), 656 DEVMETHOD(sdhci_read_2, sdhci_fsl_fdt_read_2), 657 DEVMETHOD(sdhci_read_4, sdhci_fsl_fdt_read_4), 658 DEVMETHOD(sdhci_read_multi_4, sdhci_fsl_fdt_read_multi_4), 659 DEVMETHOD(sdhci_write_1, sdhci_fsl_fdt_write_1), 660 DEVMETHOD(sdhci_write_2, sdhci_fsl_fdt_write_2), 661 DEVMETHOD(sdhci_write_4, sdhci_fsl_fdt_write_4), 662 DEVMETHOD(sdhci_write_multi_4, sdhci_fsl_fdt_write_multi_4), 663 DEVMETHOD(sdhci_get_card_present, sdhci_fsl_fdt_get_card_present), 664 DEVMETHOD_END 665}; 666 667static devclass_t sdhci_fsl_fdt_devclass; 668static driver_t sdhci_fsl_fdt_driver = { 669 "sdhci_fsl_fdt", 670 sdhci_fsl_fdt_methods, 671 sizeof(struct sdhci_fsl_fdt_softc), 672}; 673 674DRIVER_MODULE(sdhci_fsl_fdt, simplebus, sdhci_fsl_fdt_driver, 675 sdhci_fsl_fdt_devclass, NULL, NULL); 676SDHCI_DEPEND(sdhci_fsl_fdt); 677 678#ifndef MMCCAM 679MMC_DECLARE_BRIDGE(sdhci_fsl_fdt); 680#endif 681