Searched refs:Sign (Results 26 - 38 of 38) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2797 Register Sign;
2799 Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0);
2801 Sign = LHSign.getReg(0); // Remainder sign is the same as LHS
2803 UDivRem = B.buildXor(Ty, UDivRem, Sign).getReg(0);
2804 B.buildSub(DstReg, UDivRem, Sign);
H A DSIISelLowering.cpp5047 SDValue Sign = isSigned local
5051 SDValue Overflow = DAG.getSetCC(SL, MVT::i1, Top, Sign, ISD::SETNE);
/freebsd-13-stable/contrib/llvm-project/clang/utils/TableGen/
H A DNeonEmitter.cpp222 void makeInteger(unsigned ElemWidth, bool Sign) { argument
224 Kind = Sign ? SInt : UInt;
/freebsd-13-stable/contrib/llvm-project/clang/lib/Sema/
H A DDeclSpec.cpp1092 writtenBS.Sign = getTypeSpecSign();
1148 // Sign specifiers are not allowed with vector bool. (PIM 2.1)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DMemorySanitizer.cpp4778 enum class ShadowExtension { None, Zero, Sign };
4816 return ShadowExtension::Sign;
4932 /*Signed*/ SE == ShadowExtension::Sign);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp2701 StringRef Sign = Token.range();
2705 return error("expected an integer literal after '" + Sign + "'");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp55 static Value *getNewICmpValue(unsigned Code, bool Sign, Value *LHS, Value *RHS, argument
58 if (Constant *TorF = getPredForICmpCode(Code, Sign, LHS->getType(), NewPred))
H A DInstCombineCalls.cpp112 bool Sign = V->getElementType()->isIntegerTy() local
115 BoolVec.push_back(ConstantInt::get(BoolTy, Sign));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp5412 int Sign = 1;
5424 Sign = -1;
5434 Offset = MI.getOperand(2).getImm() * Sign;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2090 SDValue Sign = DAG.getNode(ISD::AND, SL, MVT::i32, Bitcast, local
2094 DAG.getNode(ISD::OR, SL, MVT::i32, Sign,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp11012 // Sign bit set in i8 mask means zero element.
19374 SDValue Sign = DAG.getNode(ISD::OR, DL, MVT::v4i64,
19378 SDValue SignSrc = DAG.getSelect(DL, MVT::v4i64, IsNeg, Sign, Src);
21273 SDValue Sign = Op.getOperand(1);
21278 if (Sign.getSimpleValueType().bitsLT(VT))
21279 Sign = DAG.getNode(ISD::FP_EXTEND, dl, VT, Sign);
21282 if (Sign.getSimpleValueType().bitsGT(VT))
21283 Sign = DAG.getNode(ISD::FP_ROUND, dl, VT, Sign, DA
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp913 // FIXME: This does not work for vectors on most targets. Sign-
1514 SDValue Sign = Node->getOperand(1);
1518 getSignAsIntValue(SignAsInt, DL, Sign);
H A DDAGCombiner.cpp3936 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
3938 AddToWorklist(Sign.getNode());
3941 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact);
9593 // Sign bits will be lost after a zext.

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