Searched refs:Sign (Results 26 - 38 of 38) sorted by relevance
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULegalizerInfo.cpp | 2797 Register Sign; 2799 Sign = B.buildXor(Ty, LHSign, RHSign).getReg(0); 2801 Sign = LHSign.getReg(0); // Remainder sign is the same as LHS 2803 UDivRem = B.buildXor(Ty, UDivRem, Sign).getReg(0); 2804 B.buildSub(DstReg, UDivRem, Sign);
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H A D | SIISelLowering.cpp | 5047 SDValue Sign = isSigned local 5051 SDValue Overflow = DAG.getSetCC(SL, MVT::i1, Top, Sign, ISD::SETNE);
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/freebsd-13-stable/contrib/llvm-project/clang/utils/TableGen/ |
H A D | NeonEmitter.cpp | 222 void makeInteger(unsigned ElemWidth, bool Sign) { argument 224 Kind = Sign ? SInt : UInt;
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/freebsd-13-stable/contrib/llvm-project/clang/lib/Sema/ |
H A D | DeclSpec.cpp | 1092 writtenBS.Sign = getTypeSpecSign(); 1148 // Sign specifiers are not allowed with vector bool. (PIM 2.1)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/ |
H A D | MemorySanitizer.cpp | 4778 enum class ShadowExtension { None, Zero, Sign }; 4816 return ShadowExtension::Sign; 4932 /*Signed*/ SE == ShadowExtension::Sign);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
H A D | MIParser.cpp | 2701 StringRef Sign = Token.range(); 2705 return error("expected an integer literal after '" + Sign + "'");
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineAndOrXor.cpp | 55 static Value *getNewICmpValue(unsigned Code, bool Sign, Value *LHS, Value *RHS, argument 58 if (Constant *TorF = getPredForICmpCode(Code, Sign, LHS->getType(), NewPred))
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H A D | InstCombineCalls.cpp | 112 bool Sign = V->getElementType()->isIntegerTy() local 115 BoolVec.push_back(ConstantInt::get(BoolTy, Sign));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 5412 int Sign = 1; 5424 Sign = -1; 5434 Offset = MI.getOperand(2).getImm() * Sign;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 2090 SDValue Sign = DAG.getNode(ISD::AND, SL, MVT::i32, Bitcast, local 2094 DAG.getNode(ISD::OR, SL, MVT::i32, Sign,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 11012 // Sign bit set in i8 mask means zero element. 19374 SDValue Sign = DAG.getNode(ISD::OR, DL, MVT::v4i64, 19378 SDValue SignSrc = DAG.getSelect(DL, MVT::v4i64, IsNeg, Sign, Src); 21273 SDValue Sign = Op.getOperand(1); 21278 if (Sign.getSimpleValueType().bitsLT(VT)) 21279 Sign = DAG.getNode(ISD::FP_EXTEND, dl, VT, Sign); 21282 if (Sign.getSimpleValueType().bitsGT(VT)) 21283 Sign = DAG.getNode(ISD::FP_ROUND, dl, VT, Sign, DA [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 913 // FIXME: This does not work for vectors on most targets. Sign- 1514 SDValue Sign = Node->getOperand(1); 1518 getSignAsIntValue(SignAsInt, DL, Sign);
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H A D | DAGCombiner.cpp | 3936 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0, 3938 AddToWorklist(Sign.getNode()); 3941 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); 9593 // Sign bits will be lost after a zext.
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