| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 1109 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel, argument
1114 return SchedModel.LoadLatency;
1116 return SchedModel.HighLatency;
1135 bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel, argument
1138 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
1250 return defaultDefLatency(ItinData->SchedModel, DefMI);
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| H A D | MachineLICM.cpp | 124 TargetSchedModel SchedModel; member in class:__anon3512::MachineLICMBase
348 SchedModel.init(&ST);
1160 if (TII->hasHighOperandLatency(SchedModel, MRI, MI, DefIdx, UseMI, i))
1188 if (!TII->hasLowDefLatency(SchedModel, MI, i))
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| H A D | IfConversion.cpp | 192 TargetSchedModel SchedModel; member in class:__anon3479::IfConverter
456 SchedModel.init(&ST);
1125 unsigned NumCycles = SchedModel.computeInstrLatency(&MI, false);
2197 unsigned NumCycles = SchedModel.computeInstrLatency(&I, false);
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1506 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1520 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, argument
1530 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCTargetTransformInfo.cpp | 499 TargetSchedModel SchedModel; local
500 SchedModel.init(ST);
511 if (Metrics.NumInsts <= (6 * SchedModel.getIssueWidth()))
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| H A D | PPCInstrInfo.h | 308 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMSubtarget.h | 502 /// SchedModel - Processor specific instruction costs.
503 MCSchedModel SchedModel; member in class:llvm::ARMSubtarget
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| H A D | ARMBaseInstrInfo.h | 420 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
425 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
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| H A D | ARMBaseInstrInfo.cpp | 4751 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel, argument
4765 SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);
4772 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel, argument
4775 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 479 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
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| H A D | X86InstrInfo.cpp | 7911 bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel, argument
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ResourcePriorityQueue.cpp | 317 if (Packet.size() >= InstrItins->SchedModel.IssueWidth) {
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNSchedStrategy.cpp | 164 TryCand.initResourceDelta(Zone.DAG, SchedModel);
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| H A D | SIInstrInfo.h | 50 TargetSchedModel SchedModel; member in class:llvm::final
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| H A D | SIInstrInfo.cpp | 97 SchedModel.init(&ST);
7154 Lat = std::max(Lat, SchedModel.computeInstrLatency(&*I));
7159 return SchedModel.computeInstrLatency(&MI);
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| /freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenSchedule.cpp | 332 const Record *SchedModel = Def->getValueAsDef("SchedModel"); local
333 unsigned ProcIndex = ProcModelMap.find(SchedModel)->second;
468 CodeGenProcModel &PM = getProcModel(RCU->getValueAsDef("SchedModel"));
483 CodeGenProcModel &PM = getProcModel(Queue->getValueAsDef("SchedModel"));
559 ProcDef->getValueAsDef("SchedModel"), ModelKey);
803 if (Rec->getValueInit("SchedModel")->isComplete()) {
804 Record *ModelDef = Rec->getValueAsDef("SchedModel");
938 getProcModel(RWDef->getValueAsDef("SchedModel"));
1079 Record *RWModelDef = InstRWDef->getValueAsDef("SchedModel");
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